AXI 3 / 4

Number of
Sl No Feature Title Description Source Types Feature ID Signal Values Category Spec Section number
Features
This signal is the identification tag for the write Write address channel
1 Write Address ID Master AWID [3:0] 1 -- Block Level
address group of signals signals
The write address bus gives the address of the
first transfer in a write burst transaction. The
Write Address Channel
2 Write Address associated control signals are used to determine Master AWADDR[31:0] 1 -- Block Level
signals
the address of the remaining transfers in the
burst.

The burst length gives the exact length number of

transfers in a burst. This information determines Write Address Channel
3 Burst Length Master AWLEN[3:0] 1 b0000 - b1111 Block Level
the number of data transfers associated with the signals
address.

Normal access b00

This signals provides additional information about Exclusive access b01
4 Lock type Master AWLOCK[1:0] 1 Block Level
the atomic characteristics of the transfers Locked access b10
Reserved b11

This signal indicates the bufferable, cacheable,

Write Address Channel
5 Cache type write-through, write-back,and allocate attributes Master AWCACHE[3:0] 1 b0000 - b1111 Block Level
signals
of the transaction.

1 = privileged access 0 =
[0]
This signal indicates the normal, privileged, or normal access
secure protection levelof the transaction and 1 = nonsecure access 0 =
6 Protection type Master AWPROT[2:0] 1 [1] Block Level
whether the transaction is a data access or an secure access
instruction access. 1 = instruction access 0 =
[2]
data access
1 byte in transfer b000
2 bytes in transfer b001
4 bytes in transfer b010
This signal indicates the size of each transfer in 8 bytes in transfer b011
7 Burst Size the burst. Byte lane strobesindicate exactly which Master AWSIZE [2:0] 1 Block level
byte lanes to update. 16 bytes in transfer b100
32 bytes in transfer b101
64 bytes in transfer b110
128 bytes in transfer b111
FIXED b00
The burst type, coupled with the size information, INCR b01
8 Burst Type details how the address foreach transfer within Master AWBURST[1:0] 1 Block Level
the burst is calculated. WRAP b10
Reserved b11
This signal indicates that valid write address and 1 = address and control
b0
controlinformation. The address and control information available
9 Write Address/Control valid Master AWVALID 1 Block Level
information remain stable until the address 0 = address and control
acknowledge signal,AWREADY, goes HIGH. b1
information not available.

Slave 0 = slave not ready. AWREADY b0

This signal indicates that the slave is ready to
10 Write Address/Control accepted 1 Block Level
accept an address andassociated control signals:
 This signal indicates that the slave is ready to
10 Write Address/Control accepted 1 Block Level
accept an address andassociated control signals:
1 = slave ready b1

This signal is the ID tag of the write data transfer.

11 Write ID tag The WID value must match the AWID value of Master Write ID tag WID[3:0] 1 -- Block Level
the write transaction.
Write data. The write data bus can be 8, 16, 32,
12 Write Data Master Write data WDATA[31:0] 1 --
64, 128, 256, 512, or 1024 bits wide.
This signal indicates which byte lanes to update
in memory. There is one write strobe for each
13 Write Strobe eight bits of the write data bus. Therefore, Master Write strobes WSTRB[3:0] 1 -- Block Level
WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8
× n)].
This signal indicates the last transfer in a write
14 Write Last Master Write last WLAST 1 b1 Block Level
burst.
1 = write data and strobes
This signal indicates that valid write data and available
15 Write Valid Master WVALID 1 -- Block Level
strobes are available. 0 = write data and strobes
not available.

0 = slave not ready. b0

This signal indicates that the slave can accept the
16 Write Ready Slave WREADY 1 Block Level
write data.
1 = slave ready b1

The identification tag of the write response. The

17 BID [3:0] BID value must match the AWID value of the Slave Response ID. BID 1 -- Block Level
write transaction to which the slave is responding
Response type-OKAY 1 b00 Block Level
This signal indicates the status of the write Response type- EXOKAY 1 b01 Block Level
18 Write response Slave BRESP[1:0]
transaction. Response type-SLVERR 1 b10 Block Level
Response type-DECERR 1 b11 Block Level
Response type-OKAY 1 b00 Block Level
This signal indicates the status of the read Response type- EXOKAY 1 b01 Block Level
19 Read response Slave RRESP[1:0]
transfer Response type-SLVERR 1 b10 Block Level
Response type-DECERR 1 b11 Block Level
1 = write response available 1 b1 Block Level
This signal indicates that a valid write response is
20 Write response valid Slave 0 = write response not BVALID
available. 1 b0 Block Level
available

1 = master ready 1 b1 Block Level

This signal indicates that the master can accept
21 Response ready. Master BREADY
the response information.
0 = master not ready 1 b0 Block Level

This signal is the identification tag for the read

22 Read Address ID Master Identification Tag ARID[3:0] 1 -- Block Level
address group of signals.
Address of Read burst
23 Read Address The first address in a read burst. Master ARADDR[31:0] 1 -- Block Level
transaction
1-16 transfers in a burst. The burst length gives
the exact number of transfers in a burst. This Defines the no. of data
24 Burst Length Master ARLEN[3:0] 1 b0000-b1111 Block Level
information determines the number of data transfer
transfers associated with the address.
1 byte of transfer 1 b000
2bytes of transfer 1 b001
4bytes of transfer 1 b010
This signal indicates the size of each transfer in 8bytes of transfer 1 b011
25 Burst Size Master ARSIZE[2:0] Block Level
the burst. 1,2,4...64,128 bytes per transfer.
 This signal indicates the size of each transfer in
25 Burst Size Master ARSIZE[2:0] Block Level
the burst. 1,2,4...64,128 bytes per transfer. 16bytes of transfer 1 b100
32bytes of transfer 1 b101
64bytes of transfer 1 b110
128bytes of transfer 1 b111
Fixed Address burst FIXED 1 b00 Block Level
Incrementing address burst INCREMENT 1 b01 Block Level
26 Burst Type Incrementing-address burst that wraps Master ARBURST[1:0]
WRAP 1 b10 Block Level
to a lower address at the wrap boundary
- RESERVED 1 b11 Block Level
Normal access b00
This signal provides additional information about Exclusive access b01
27 Lock Type Master ARLOCK[1:0] 1 Block Level
the atomic characteristicsof the transfer. Locked access b10
Reserved b11
The interconnect or any component can delay the
transaction reaching its final destination for an Bufferable 1 ARCACHE[0] Block Level
arbitrary number of cycles
Transaction should be cached this bit should be
used in conjunction with the Read Allocate (RA) Cacheable 1 ARCACHE[1] Block Level
and Write Allocate (WA) bits
28 Cache Type Master ARCACHE[3:0]
RA bit is HIGH, it means that if the transfer is a
read The RA bit must not be HIGH if the C bit is Read Allocate(RA) 1 ARCACHE[2] Block Level
low.
WA bit is HIGH, it means that if the transfer is a
write.The WA bit must not be HIGH if the C bit is Write Allocate 1 ARCACHE[3] Block Level
low
1 = privileged access 0 =
[0]
normal access
This signal provides protection unit information 1 = nonsecure access 0 =
29 Protection Type Master ARPROT[2:0] 1 [1] Block Level
for the transaction. secure access
1 = instruction access 0 =
[2]
data access
This signal indicates, when HIGH, that the read 1 = address and control
1 ARVALID=1
address and control information is valid and will information valid
30 Read address valid Master ARVALID Block Level
remain stable until the address acknowledge 0 = address and control
signal, ARREADY, is high. 1 ARVALID=0
information not valid.

1 = slave ready 1 ARREADY=1

This signal indicates that the slave is ready to
31 Read address ready. Slave ARREADY Block Level
accept an address andassociated control signals
0 = slave not ready 1 ARREADY=0

All input signals are sampled on the rising edge All signals are sampled on
32 Global clock signal. of ACLK. All output signal changes must occur Clock the rising edge of the global ACLK 1 ACLK=1 Block Level
after the rising edge of ACLK. clock.
The reset Signal can be asserted
asynchronously, but deassertion must be
33 Global reset signal. Reset This signal is active LOW. ARESETn 1 ARESETn=0 Block Level
synchronous after the
rising edge of ACLK.
1 RID=000
1 RID=001
The slave must ensure that
This signal is the ID tag of the read data group of the RID value of any 1 RID=010
signals. The RID value is generated by the slave returned read data matches 1 RID=011
34 Read ID tag. Slave RID[3:0] Block Level
and must match the ARID value of the read the ARID value of the 1 RID=100
transaction to which it is responding. address to which it is
responding.
 The slave must ensure that
This signal is the ID tag of the read data group of the RID value of any
signals. The RID value is generated by the slave returned read data matches
34 Read ID tag. Slave RID[3:0] Block Level
and must match the ARID value of the read the ARID value of the
transaction to which it is responding. address to which it is
1 RID=101
responding.
1 RID=110
1 RID=111
In case of 32 bits
The read data bus can be 8, 16, 32, 64, 128, 256,
35 Read data. Slave Read data channel signal RDATA[31:0] 1 32'h0 to Block Level
512, or 1024 bits wide.
32'hffff_ffff
RLAST=1
This signal indicates the last transfer in a read indicates the last
36 Read last. Slave Read data channel signal RLAST 1 Block Level
burst. transfer of the
read burst

1 = read data available 1 RVALID=1 Block Level

This signal indicates that the required read data
37 Read valid. Slave RVALID
is available and the read transfer can complete
0 = read data not available 1 RVALID=0 Block Level

1= master ready 1 RREADY=1 Block Level

This signal indicates that the master can accept
38 Read ready. Master RREADY
the read data and response information
0 = master not ready 1 RREADY=0 Block Level

Reference

Sl No File name Document

1 AXI 3 Specification
2 AXI 4 Specification