Overview

About Arm Flexible Access

Arm Flexible Access provides up-front, zero or low cost access to a wide range of Arm IP, tools, and training.
Experiment and design with the entire portfolio—license fees are only due at the point of manufacture and
calculated only on the IP included in the final SoC design.

The Standard and Entry Tiers of Flexible Access include an extensive range of Arm IP and dedicated support,
training, and development tools.

The DesignStart Tier offers $0 access to physical IP and a select mix of Arm IP, forum support, access to online
training materials and development tools.

Flexible Access includes free use of thousands of Arm Artisan Physical IP libraries for implementing silicon for
manufacture across the broadest range of foundries and process technology nodes.

For more information, visit https://www.arm.com/products/flexible-access.

Early-stage startups can benefit from the Arm Flexible Access for Startups program, giving free access to the
Entry Tier of Flexible Access. For more information visit https://www.arm.com/products/flexible-access/startup.

How does Arm Flexible Access work?

1
How much does Arm Flexible Access cost?

Tiers DesignStart Entry Standard

$80k per annum

Access fees $0 $212k per annum
$0 for startups*

License fees (due on project manufacture) Calculated per design based on IP used. **

Royalty Calculated per project and paid per unit shipped **

*Qualifying startups with <$20M funding, <$1M annual revenue, privately held
**Thousands of Arm Artisan Physical IP libraries are free of charge

What is included in Arm Flexible Access?

Tier DesignStart Entry Standard

Ideal for larger semiconductor

Ideal for smaller semiconductor design teams
development teams with
doing no more than 1 tape out per year
multiple concurrent projects

DesignStart CPU Package:

Mainstream Package:
Cortex-M0, Cortex-M23,
IP portfolio Broad portfolio of Cortex CPUs, Mali GPUs, Corstone IP,
Cortex-M3 and related Corstone
CoreLink and CoreSight System IP
example systems

DesignStart Physical IP
√ √ √
(Free Library Program)

Support from Arm expert engineers Forum support √ √

1 1+ *
Number of tape-outs per year Unlimited
(Unlimited for Physical IP) (Unlimited for Physical IP)

Online training 2 Seats Unlimited on-demand training seats

1 Hardware Success Kit 9 Hardware Success Kit User 18 Hardware Success Kit User
Tools and models
User License Licenses Licenses

$0 for qualifying startups

Membership Fee $0 $212k per annum
or $80k per annum

* Entry Tier: Up to 3 tape outs where any of Cortex-M0/M0+/M23/M3/M4 is the main processor, or 1 tape out per year

2
Standard and Entry Tiers

Product Description Learn more about this product

Cortex Processors

Cortex-A76 enables the always-on ease of large-screen

compute, to deliver laptop-class performance with mobile https://www.arm.com/products/silicon-ip-cpu/
Cortex-A76 Processor
efficiency. A significant step forward in mobile computing, cortex-a/cortex-a76
whether on a smartphone or laptop.

Built on DynamIQ technology, designed for extreme scalability in

constrained environments and featured with the latest Armv8-A
https://www.arm.com/products/silicon-ip-cpu/
Cortex-A55 Processor architecture extensions that introduce new NEON instructions
cortex-a/cortex-a55
for machine learning, advanced safety features and more
support for Reliability, Accessibility and Serviceability (RAS).

Low-power processor with 32-bit and 64-bit capabilities,

applicable in a range of devices requiring high performance
https://www.arm.com/products/silicon-ip-cpu/
Cortex-A53 Processor in power-constrained environments. Reference design &
cortex-a/cortex-a53
supporting system IP available in Corstone-1000. Subsystem
requires minor modifications to integrate this processor.

Ultra-high efficiency smart device processor, the smallest

and most power-efficient 32-bit and 64-bit Arm application
processor. https://www.arm.com/products/silicon-ip-cpu/
Cortex-A35 Processor
Reference design & supporting system IP available in cortex-a/cortex-a35
Corstone-1000. Subsystem requires minor modifications to
integrate this processor.

Low-power 64-bit only processor with ultra-high efficiency.

Reference design & supporting system IP available in https://www.arm.com/products/silicon-ip-cpu/
Cortex-A34 Processor
Corstone-1000. Subsystem requires minor modifications to cortex-a/cortex-a34
integrate this processor.

Low-power 32-bit only processor with ultra-high efficiency.

https://www.arm.com/products/silicon-ip-cpu/
Cortex-A32 Processor Reference design & supporting system IP available in
cortex-a/cortex-a32
Corstone-700.

Power-efficient processor, designed for a wide range of devices

https://www.arm.com/products/silicon-ip-cpu/
Cortex-A7 Processor with differing requirements demanding balance between power and
cortex-a/cortex-a7
performance.
Highest-performance Cortex-R processor with memory
management unit (MMU), enabling real-time and rich operating
systems (OS), such as Linux, on the same core or cluster. As the
first Arm 64-bit Cortex-R processor, the Cortex-R82 can address https://www.arm.com/products/silicon-ip-cpu/
Cortex-R82 Processor
up to 1TB of dynamic random-access memory (DRAM) for cortex-r/cortex-r82
efficient, high-performance compute. Ideal for solid-state drives
(SSDs), hard-disk drives (HDDs) and built-in storage solutions, as
well as computational storage applications.

Designed for advanced silicon processes requiring

https://www.arm.com/products/silicon-ip-cpu/
Cortex-R52 Processor high-performance and cost-effective processing.
cortex-r/cortex-r52
Delivers real-time performance for functional safety.

Builds on its predecessor, the Arm Cortex-R52, to assist

https://www.arm.com/products/silicon-ip-cpu/
Cortex-R52+ Processor integration and virtualization for functional safety applications,
cortex-r/cortex-r52-plus
while maintaining software compatibility.

Designed for products with high performance requirements https://www.arm.com/products/silicon-ip-cpu/

Cortex-R8 Processor
where timing deadlines must always be met. cortex-r/cortex-r8

Offers high-performance computing solutions for embedded

https://www.arm.com/products/silicon-ip-cpu/
Cortex-R5 Processor systems that require reliability, high availability, fault tolerance,
cortex-r/cortex-r5
and real-time responses.

Highest performing Cortex-M that integrates Helium vector

https://www.arm.com/products/silicon-ip-cpu/
Cortex-M85 Processor processing. Delivers highest scalar and vector processing "on-
cortex-m/cortex-m85
time" for the most demanding use-cases.

3
 First Cortex-M processor to integrate Helium vector processing
technology. It brings a significant uplift in DSP and ML https://www.arm.com/products/silicon-ip-cpu/
Cortex-M55 Processor
performance, while meeting the efficiency requirements of cortex-m/cortex-m55
constrained endpoint use-cases.

The highest performance CPU in the energy-efficient Cortex-M

https://www.arm.com/products/silicon-ip-cpu/
Cortex-M7 Processor processor family and includes digital signal processing (DSP)
instructions.
cortex-m/cortex-m7

Optimized for cost and power-sensitive microcontroller and

mixed- signal applications. Designed for applications requiring
efficient security or digital signal control. New Arm Custom https://www.arm.com/products/silicon-ip-cpu/
Cortex-M33 Processor
Instructions allow optimization for specific workloads. cortex-m/cortex-m33
Reference design & supporting system IP available in
Corstone-201.

Designed to address applications requiring digital signal

processing, with a blend of efficient, easy-to-use control and https://www.arm.com/products/silicon-ip-cpu/
Cortex-M4 Processor
signal processing capabilities. Supporting system IP available in cortex-m/cortex-m4
Corstone-101.

Designed for cost-sensitive and power-constrained solutions in a

broad range of devices. Balanced between area, performance, and
https://www.arm.com/products/silicon-ip-cpu/
Cortex-M3 Processor power.
Reference design & supporting system IP available in
cortex-m/cortex-m3
Corstone-101.

Smallest and lowest-power microcontroller with Arm TrustZone security,

ideal for applications requiring software isolation and security. https://www.arm.com/products/silicon-ip-cpu/
Cortex-M23 Processor
Reference design & supporting system IP available in cortex-m/cortex-m23
Corstone-102.

The smallest footprint and lowest power requirements of all

Cortex-M processors, suitable for a wide variety of applications,
https://www.arm.com/products/silicon-ip-cpu/
Cortex-M0+ Processor including sensors and wearables.
cortex-m/cortex-m0-plus
Reference design & supporting system IP available in
Corstone-101.

Small footprint and high efficiency, ideal for simple,

cost-sensitive devices. https://www.arm.com/products/silicon-ip-cpu/
Cortex-M0 Processor
Reference design & supporting system IP available in cortex-m/cortex-m0
Corstone-101.

Ethos Machine Learning Processors

Ethos-U65 enables new AI capabilities into edge and endpoint

devices in applications including high resolution smart cameras,
smart home solutions, voice assistants, drones, and wearables
with 2x the performance over Ethos-U55, and achieving 1TOPs
using our microNPU architecture. Ethos-U65 is designed for use https://www.arm.com/products/silicon-ip-cpu/
Ethos-U65
with DRAM based systems, which leads to higher bandwidth ethos/ethos-u65
availability. This allows Ethos-U65 to be used with all classes
of embedded systems: higher performance Cortex-A based
SoCs or low power Cortex-M based SoCs for battery powered
devices (with or without DRAM)

Ethos-U55 is a first generation uNPU for accelerating neural

networks. It is targeted at the embedded market and works
alongside Cortex-M processors. Ethos-U55 hits multiple https://www.arm.com/products/silicon-ip-cpu/
Ethos-U55
performance points with 4 different possible configurations and ethos/ethos-u55
hence can target a wide variety of applications like smart home
appliances, DTV, smart speakers etc.

4
Corstone IP

Cortex processor reference packages and supporting system IP. Simplifies silicon design and reduces time to market.

Corstone-1000 is a reference package that integrates Cortex-A

and Cortex-M processors. It is meant to help efficiently build a
secure and efficient 64-bit Linux-capable IoT System-on-Chip
(SoC), targeting applications such as endpoints, gateways,
embedded applications. Its system architecture combines a
choice of the Cortex-A53, Cortex-A35 or Cortex-A32 processor https://www.arm.com/products/silicon-ip-
Corstone-1000 with up to two Cortex-M based systems. It includes a verified
subsystems/corstone-1000
subsystem with advanced power management, authenticated
debug, a stand-alone Secure Enclave for PSA hardware root
of trust, and a dedicated firewall IP for enhanced security.
All required system IP and a reference software stack are
included, enabling rendering and further modifications of the
design.

A package to help SoC designers build Cortex-M85/Ethos-U65

based systems faster. Corstone-315 combines an example
subsystem, System IP, software, and tools to streamline IoT device https://www.arm.com/products/silicon-ip-
Corstone-315
development. Corstone-315 integrates Cortex-M85 along with an subsystems/corstone-315
optional Ethos-U65 NPU and Mali-C55 ISP to build low-power, low-
cost, high-performance endpoint AI devices that support CNNs.

An example system designed around Cortex-M85 with system-

wide TrustZone for Arm v8-M over AXI and power management https://www.arm.com/products/silicon-ip-
Corstone-310
capability. The memory system is also optimized to support subsystems/corstone-310
Ethos-U55.

Arm Corstone-300 is a reference package and system IP

package providing a starting point for signal processing and
machine learning applications. It is designed around the
Arm Cortex-M55 processor, and demonstrates system-wide https://www.arm.com/products/iot/soc/
Corstone-300
TrustZone over AMBA AXI and integrated power management. corstone-300
The IP, along with FPGA
and FVP platforms, and open-source software such as TF-M,
gives a both a head start and reduces risk in SoC development.

Reference package and system IP for building a secure system

on chip with the Cortex-M33 processor. The Corstone-201
contains various system IP components and a reference design https://www.arm.com/products/iot/soc/
Corstone-201
subsystem integrating the processor, memory, debug, security corstone-201
and power control. It is designed for the mainstream market
targeting performance balanced with power efficiency.

The Arm Corstone-102 provides a flexible reference package

and system IP for small, low cost and energy efficient SoC https://www.arm.com/products/iot/soc/
Corstone-102 development. Based on the Arm Cortex-M23 processor, the
corstone-102
Corstone-102 is targeted at the constrained market segment for
secure IoT applications.

The Arm Corstone-101 contains a reference package based on

the Cortex-M3, as well as various other system IP components. https://www.arm.com/products/iot/soc/
Corstone-101 It provides all of the fundamental system elements to design a
corstone-101
SoC around Arm Cortex-M0/Cortex-M0+/Cortex-M3/Cortex-M4
processors.

5
Mali Multimedia Processing

Mali G510 inherits features from premium GPUs, such as

command stream frontend and asynchronous top level, a
https://www.arm.com/products/silicon-ip-
Mali-G510 Graphics Processor completely redesigned execution and texturing unit. It also adds
multimedia/gpu/mali-g510
formats for better HDR support AFBC uncompressed buffers,
and Arm Fixed Rate Compression (AFRC).

G310 is the latest ultra-efficient Mali GPU, offering a high

degree of scalability with 5 shader core configurations (V1-V5).
G310 can be scaled in both area and performance to create
https://www.arm.com/products/silicon-ip-
Mali-G310 Graphics Processor competitive products, ranging from low-perfomance IoT and
multimedia/gpu/mali-g310
wearable solutions, all the way up to premium 4K DTV solutions,
and more. In addition, G310 introduces key features such as
lossy compression and HDR format support.

In order to make use of the G310 GPU RTL a separate license

Valhall Android DDK is required for the Valhall DDK. There are Android and Linux
versions of the DDK and at lease one will be required.

In order to make use of the G310 GPU RTL a separate license

Valhall Linux DDK is required for the Valhall DDK. There are Android and Linux
versions of the DDK and at lease one will be required.

Mali-C55 is a highly configurable, energy-efficient Image Signal

Processor (ISP) for IoT markets. It provides outstanding precision
and dynamic range with excellent image quality in a small
Mali-C55 Image Signal https://www.arm.com/products/silicon-ip-
silicon footprint. It’s easy to integrate between Mali-C55 and ML
Processor multimedia/image-signal-processor/mali-c55
accelerators. Ideal for various use scenarios, from Smart Vision,
Smart Home hub, and consumer/commercial security camera to
Smart Display products.

State-of-the-art image signal processing with class-leading

Mali-C52 Image Signal https://www.arm.com/products/silicon-ip-
high dynamic range image quality in real-time. Can be optimized
Processor multimedia/image-signal-processor/mali-c52
for performance or area.

High precision and high dynamic range image signal processor.

Mali-C32 Image Signal https://www.arm.com/products/silicon-ip-
Optimized for area. Ideal for low-power, cost-sensitive
Processor multimedia/image-signal-processor/mali-c32
embedded vision devices.

Mali-C10 is a highly configurable Geometrical Distortion

Correction engine, capable of performing up to four
simultaneous geometric warp functions, each displayed in a
Mali-C10 Image Signal Processor sub-window, at video resolutions up to 4K UHD. The Mali-C10
GDC engine is suitable for video surveillance, fisheye correction,
automotive reversing cameras, and panoramic correction and
dome cameras.

AFBC is a lossless image compression format that provides

random access to pixel data to a 4x4 pixel block granularity. It is
AFBC Codec Cores
employed to reduce memory bandwidth both internally within
the GPU and externally throughout the SoC
https://www.arm.com/technologies/graphics-
technologies/arm-frame-buffer-compression
Ready to be integrated with non-Arm multimedia IP blocks to
bring the advantages of Arm Frame Buffer Compression (AFBC)
AFBC Standalone System IP
across the SoC. AFBC minimizes multimedia system bandwidth
requirements, significantly reducing SoC power consumption.

AFRC is a lossy image compression format. AFRC can be

used for compressing external texture inputs and framebuffer
AFRC Codec Hardware outputs from the GPU. Configurable compression ratio provides
guaranteed bandwidth reduction for such surfaces and memory
footprint saving.

6
CoreLink Interconnect

Full coherency with up to six clusters including big.LITTLE and

CoreLink CCI-550 Cache https://www.arm.com/products/silicon-ip-system/
coherent accelerators. High performance and power efficiency
Coherent Interconnect corelink-interconnect/cci-550
with integrated snoop filter.

Full coherency with up to four clusters including big.LITTLE and

CoreLink CCI-500 Cache https://www.arm.com/products/silicon-ip-system/
coherent accelerators. High performance and power efficiency
Coherent Interconnect corelink-interconnect/cci-500
with integrated snoop filter.

Provides full cache coherency between two clusters of multi-

CoreLink CCI-400 Cache
core https://www.arm.com/products/silicon-ip-system/
Coherent Interconnect
CPUs. Enables big.LITTLE processing and I/O coherency corelink-interconnect/cci-400
with CPE-425 for devices.

Corelink NI-700 is a Configurable and Scalable Network-

CoreLink NI-700 Network https://developer.arm.com/Processors/
on-Chip(NoC) for High Bandwidth accelerators,rest-of-SoC
Interconnect CoreLink%20NI-700
connectivity and peripherals.

Highly configurable topology with network-on-chip properties

CoreLink NIC-450 https://www.arm.com/products/silicon-ip-system/
for building high-performance, optimized, AMBA-compliant SoC
Network Interconnect corelink-interconnect/nic
connectivity, including QoS and Thin links.

Highly configurable topology with network-on-chip properties

CoreLink NIC-400 https://www.arm.com/products/silicon-ip-system/
for building high-performance, optimized, AMBA-compliant
Network Interconnect corelink-interconnect/nic
SoC connectivity.

Licensable extension of CoreLink NIC-400 Network

CoreLink DPE-400 Interconnect, DPE-400 provides transportation of read and https://developer.arm.com/
Data Parity Extn write data payload parity information, using the AXI WUSER documentation/100591/0100/dpe-400-overview
and RUSER, and AHB HWUSER and HRUSER, signals.

https://developer.arm.com/ip-products/
CoreLink ADB-400 AMBA An asynchronous bridge between two components or systems
system-ip/corelink-interconnect/corelink-
Domain Bridge that can be in a different power, clock, or voltage domains.
network-interconnect-family

CoreLink PCK-600 Power Control Kit with a suite of system IP to ease system https://www.arm.com/products/silicon-ip-
Power Control Kit power and clock management infrastructure integration. system/system-controllers/pck-600

https://developer.arm.com/ip-products/
CoreLink XHB-400 Converts AXI4 protocol to AHB-Lite protocol via an AXI4 slave
system-ip/corelink-interconnect/corelink-
AXI4-AHB Bridge interface and an AHB-Lite master interface.
network-interconnect-family

XHB-500 provides an AMBA AXI5 to AHB5 bridge and an AHB5 https://developer.arm.com/docs/101375/latest/

CoreLink XHB-500
to AXI5 bridge. introduction/about-the-xhb-500-bridges

Provides a set of configurable AXI5 security-aware components

that can protect peripherals and memories that are unaware of https://developer.arm.com/ip-products/
CoreLink SIE-300 security, so that a peripheral or memory is only accessible to system-ip/corelink-interconnect/corelink-
trusted software. The SIE-300 also provides clock synchronizing sie-300
bridges and an access control gate.

7
CoreLink System Controllers

AHB Cache can be implemented as a processor cache (data

or generic), or a system cache. It can be used for both code
https://developer.arm.com/ip-products/system-
CoreLink AHB Cache and data. The cache provides AHB5 data interfaces and an
ip/system-controllers/cache-controllers
APB configuration interface, both with TrustZone for Armv8-M
support.

The CoreLink SIE-200 system IP includes a collection of

https://developer.arm.com/ip-products/system-
CoreLink SIE-200 AHB System IP interconnect, peripheral, and TrustZone controller components
to help build secure AHB systems more easily. ip/corelink-interconnect/corelink-sie-200

CoreLink DMA-350 is an AXI DMA controller targeted

at endpoint AI systems, particularly those based on the
https://developer.arm.com/Processors/
Corelink DMA-350 Cortex-M55 processor. It has been designed to enable efficient
data movement, thereby reducing system power consumption CoreLink%20DMA-350
and improving performance.

A high-performance DMA controller that can boost the

CoreLink DMA-330 AXI https://www.arm.com/products/silicon-ip-system/
performance and reduce the power consumption in AXI-based
DMA Controller embedded-system-design/dma-330
systems.

The Arm CoreLink DMA-250 direct memory access (DMA)

controller offloads memory movement tasks from the CPU to
improve system performance and energy-efficiency. It includes
support for scatter gather, memory to memory, memory to https://www.arm.com/products/silicon-ip-system/
CoreLink DMA-250 AHB DMA
peripheral (and vice versa) transfers. This DMA controller pairs embedded-system-design/dma-250
well with the Cortex-M52 and Cortex-M33 processors or any
AHB-systems where area and power constraints are key design
considerations.

CoreLink DMA-230 AHB Low gate count (3-10k gates) micro-DMA engine targeting https://www.arm.com/products/silicon-ip-system/
Micro DMA Controller AHB-based Cortex-M systems. embedded-system-design/dma-230

The GIC-625 is a generic interrupt controller that handles

CoreLink GIC-625 interrupts from peripherals to the cores, and interrupts between https://developer.arm.com/
Generic Interrupt Controller cores. The GIC supports up to 8 clusters and supports the documentation/102143/0100
GICv3 and GICv3.1 architecture.

Detects, manages, virtualizes, and distributes interrupts for

CoreLink GIC-600 https://www.arm.com/products/silicon-ip-system/
Armv8.0-A processors. Configurable - up to 512 processor
Generic Interrupt Controller system-controllers/gic
threads per chip, up to 16 chips, and 960 shared interrupts.

Detects, manages, virtualizes, and distributes interrupts for

CoreLink GIC-500 https://www.arm.com/products/silicon-ip-system/
Armv8.0-A processors. Configurable up to 128 single-threaded
Generic Interrupt Controller system-controllers/gic
cores and 960 shared interrupts.

Detects, manages, and virtualizes interrupts for Armv7

CoreLink GIC-400 https://www.arm.com/products/silicon-ip-system/
processors. Configurable up to 8 cores and 480 shared
Generic Interrupt Controller system-controllers/gic
interrupts.

MHU-320AE Message Handling Unit facilitates interrupt-based https://developer.arm.com/

CoreLink MHU-320AE communication between processing elements executing documentation/107612/0001/Overview-of-MHU-
independent software stacks. 320AE

CoreLink TZC-400 TrustZone Performs security checks on transactions to memory or https://www.arm.com/products/silicon-ip-

Address Space Controller peripherals, configurable up to 8 regions. security/address-space-controllers

High-performance, AXI level 2 cache controller designed and

CoreLink L2C-310 AXI Level 2 https://www.arm.com/products/silicon-ip-system/
optimized to address Arm AXI processors, normally used with
Cache Controller embedded-system-design/l2c-310
Cortex-A5.

Highly scalable with support for millions of translation contexts.

CoreLink MMU-600 System Designs can be scaled from small to large-scale systems while https://www.arm.com/products/silicon-ip-system/
Memory Management Unit maintaining a common driver framework. TrustZone Media system-controllers/mmu
Protection protects high-value 4K premium content.

8
 System memory management unit that includes caching and
memory virtualization. Enforces memory protection and access
CoreLink MMU-500 System https://www.arm.com/products/silicon-ip-system/
control, and is designed for use in a virtualized system where
Memory Management Unit system-controllers/mmu
multiple guest operating systems are managed by a hypervisor.
Supports Armv8-A and Armv7-A.

https://developer.arm.com/ip-products/
PL192 Vectored An advanced vectored interrupt controller supporting up to 32
vectored interrupts with programmable priority level and masking. system-ip/system-controllers/peripheral-
Interrupt Controller
controllers

BP140 AXI Internal

AXI to on-chip SRAM interface. https://developer.arm.com/docs/dto0009/a
Memory Interface

BP141 TrustZone AXI AXI to on-chip SRAM interface with support for Arm TrustZone https://developer.arm.com/products/system-ip/
Memory Interface protection for secure memory regions. system-controllers/other-system-controllers

Peripheral Controllers

PL011 UART Universal

https://developer.arm.com/ip-products/system-
Asynchrounous Receiver/
ip/system-controllers
Transmitter

PL022 SPI Synchronous Peripheral controllers for UART, SPI and real-time clock. https://developer.arm.com/ip-products/system-
Serial Port ip/system-controllers

https://developer.arm.com/ip-products/system-
PL031 RTC Real Time Clock
ip/system-controllers

CoreSight Debug & Trace

For high-bandwidth debug and trace solutions. Includes remote
CoreSight SoC-600 https://www.arm.com/products/silicon-ip-system/
and local debug access, trace routing and termination, cross-
Debug and Trace coresight-debug-trace/soc-600
triggering and time stamping.

Debug and trace components for multi-core Cortex-M based https://www.arm.com/products/silicon-ip-system/

CoreSight SoC-600M
SocS. Includes remote and local debug access, trace routing
Debug and Trace coresight-debug-trace/soc-600M
and termination, cross-triggering and time stamping.

Configurable components, including debug access trace https://www.arm.com/products/silicon-ip-system/

CoreSight SoC-400
generation manipulation and output, cross triggering,
Debug and Trace coresight-debug-trace/soc-400
and time stamping.

Addresses device security needs by allowing silicon and tool

CoreSight SDC-600 vendors to enforce protection and police debug access, and https://www.arm.com/products/silicon-ip-system/
Secure Debug Channel by working closely with cryptographic elements and debug coresight-debug-trace/sdc-600
certificate authentication.

Embedded Logic Analyzer with highest data tracing efficiency https://www.arm.com/products/silicon-ip-

CoreSight ELA-600
and capacity. Improves system efficiency with run-time signal system/coresight-debug-trace/coresight-
Emb Logic Analyzer
monitoring and control. ela-600

Embedded Logic Analyzer providing an effective way to observe https://www.arm.com/products/silicon-ip-

CoreSight ELA-500
low-level signals in an SoC, offering a way to zoom into the root system/coresight-debug-trace/coresight-
Emb Logic Analyzer
cause of data corruption. ela-500

Trace source for real-time software instrumentation with no https://www.arm.com/products/silicon-ip-

CoreSight STM-500 impact on system behavior or performance. Extends the low-
system/coresight-debug-trace/coresight-
System Trace Macrocell cost, real-time visibility of software and hardware execution to all
stm-500
software developers. Supports 64-bit memory interfaces.

https://developer.arm.com/ip-products/
CoreSight System Trace system-ip/coresight-debug-and-trace/
System Trace Macrocell supporting 32-bit memory interfaces.
Macrocell coresight-components/system-trace-
macrocell

A configurable trace component to terminate trace buses into https://www.arm.com/products/silicon-ip-

CoreSight Trace Memory
buffers, FIFOs, or alternatively, to route trace data over AXI to
Controller system/coresight-debug-trace/coresight-tmc
memory or off-chip to interface controllers.
9
Artisan Physical IP

Reference flow offering a low-risk path to implementation of the

Cortex-M85 PIK for TSMC 22ULL
Cortex-M85 with Artisan Physical IP on TSMC 22ULL process node.

Reference flow offering a low-risk path to implementation of the

Cortex-M55 PIK for TSMC 22ULL
Cortex-M55 with Artisan Physical IP on TSMC 22ULL process node.
https://www.arm.com/products/silicon-ip-
physical
Reference flow offering a low-risk path to implementation of the
Cortex-M33 PIK for TSMC 22ULL
Cortex-M33 with Artisan Physical IP on TSMC 22ULL process node.

Reference flow offering a low-risk path to implementation of the

Ethos-U55 PIK for TSMC 22ULL
Ethos-U55 with Artisan Physical IP on TSMC 22ULL process node.

10
Artisan Physical IP – Free Library Program

For details of the thousands of Physical IP libraries included in the Artisan Physical IP - Free Library Program see
https://www.arm.com/products/silicon-ip-physical

5 7 12 14 22 28 40 45 55 65 80 90 110 130 150 152 160 180 250

nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm

TSMC • • • • • • • • • • • • • • • •

Samsung • • • • • •

Global
Foundries/ • • • • • • • • • • • •
IBM

UMC • • • • • • • • • • •

SMIC • • • • • • • •

XMC •

SK hynix •

Silterra • • • •

HHGrace • • •

DB HiTek • • •

Vanguard • • •

MagnaChip • •

CSMC •

TowerJazz • •

HeJian • •

1st Silicon • •

HHNEC •

For each geometry in this table, multiple process flavours may exist. Not all Arm Artisan Physical IP for each process flavour within the listed geome-
tries and marked with a dot are available as part of the Free Library Program included in the DesignStart Tier of AFA. Additional fee-based IP may be
available for technologies not marked in this table.

Please contact your Arm Account Manager for further information.

11
Safety Packages

Cortex-A55 Safety Package

Cortex-A53 Safety Package

Cortex-A35 Safety Package

Cortex-A32 Safety Package

Cortex-A34 Safety Package

Cortex-R52+ Safety Package

Safety Packages provide information used by chip developers
Cortex-R52 Safety Package when creating SoCs for functional safety applications and for
easing the process of obtaining safety certification. They contain
Cortex-R5 Safety Package documentation specific for an individual processor.
https://www.arm.com/why-arm/technologies/
safety
Cortex-M85 Safety Package Cortex-A55, Cortex-A53, Cortex-R52+, Cortex-R52, Cortex-R5,
Cortex-M33, Cortex-M4, Cortex-M3, and Cortex-M0+ Safety
Packages also provide access to their respective Software Test
Cortex-M55 Safety Package
Library (STLs) to enable integration of the library.

Cortex-M33 Safety Package

Cortex-M23 Safety Package

Cortex-M7 Safety Package

Cortex-M4 Safety Package

Cortex-M3 Safety Package

Cortex-M0+ Safety Package

Training

Arm on-demand training provides access to a wealth of training

content, speeding up silicon development and providing the
knowledge you need, when and where you need it. Topics
including Arm CPU Architectures, Cortex-M hardware, AMBA
https://developer.arm.com/Training/Arm%20
Arm On-Demand bus protocols, Arm tools and models are delivered via over 1000
On-demand%20Training%20-%20Flexible%20
Online Training pieces of content and accompanying knowledge checks.
Access
Transcripts for online training are available in Korean, Simplified
and Traditional Chinese and Japanese. Contact your account
manager for access.

12
DesignStart Tier

Product Description Learn more about this product

Cortex Processors

Designed for cost-sensitive and power-constrained solutions in

a broad range of devices. Balanced between area, performance,
https://www.arm.com/products/silicon-ip-cpu/
Cortex-M3 Processor and power.
cortex-m/cortex-m3
Reference design & supporting system IP available in
Corstone-101.

Smallest and lowest-power microcontroller with Arm TrustZone

security, ideal for applications requiring software isolation and
https://www.arm.com/products/silicon-ip-cpu/
Cortex-M23 Processor security.
cortex-m/cortex-m23
Reference design & supporting system IP available in
Corstone-102.

Small footprint and high efficiency, ideal for simple, cost-

sensitive devices. https://www.arm.com/products/silicon-ip-cpu/
Cortex-M0 Processor
Reference design & supporting system IP available in cortex-m/cortex-m0
Corstone-101.

Corstone IP

Cortex processor reference packages and supporting system IP. Simplifies silicon design and reduces time to market.

The Arm Corstone-102 provides a flexible reference package

and system IP for small, low cost and energy efficient SoC
https://www.arm.com/products/iot/soc/
Corstone-102 development. Based on the Arm Cortex-M23 processor, the
corstone-102
Corstone-102 is targeted at the constrained market segment for
secure IoT applications.

The Arm Corstone-101 contains a reference package based on

the Cortex-M3, as well as various other system IP components.
https://www.arm.com/products/iot/soc/
Corstone-101 It provides all of the fundamental system elements to design a
corstone-101
SoC around Arm Cortex-M0/Cortex-M0+/Cortex-M3/Cortex-M4
processors.

13
Artisan Physical IP – Free Library Program

for details of the thousands of Physical IP libraries included in the Artisan Physical IP - Free Library Program see
https://www.arm.com/products/silicon-ip-physical

5 7 12 14 22 28 40 45 55 65 80 90 110 130 150 152 160 180 250

nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm

TSMC • • • • • • • • • • • • • • • •

Samsung • • • • • •

Global
Foundries/ • • • • • • • • • • • •
IBM

UMC • • • • • • • • • • •

SMIC • • • • • • • •

XMC •

SK hynix •

Silterra • • • •

HHGrace • • •

DB HiTek • • •

Vanguard • • •

MagnaChip • •

CSMC •

TowerJazz • •

HeJian • •

1st Silicon • •

HHNEC •

DesignStart Training

Arm on-demand training provides access to a wealth of training content, speeding up silicon development and providing the knowledge you need, when and
where you need it. Topics including Arm CPU Architectures, Cortex-M hardware, AMBA bus protocols, Arm tools and models are delivered via over 1000 pieces
of content and accompanying knowledge checks.

Transcripts for online training are available in Korean, Simplified and Traditional Chinese and Japanese. Contact your account manager for access.

The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All rights reserved. All other marks featured may be trademarks of their respective owners.

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