[sae] (amen i) Design specifications Specification of a design is as a guide to choose the right technology and for knowing the needs of the vendor. Specifications allows each engineer to understand the entire design. It helps the engineer for designing correct interface with rest of the circuit or system. It reduces time required for design and also misassumptions if any. if % si Am tion includes following information 1. A block diagram providing details how designed chip fit into the entire system. te 2, Internal block diagram for every subsection and its function. 3 input threshold levels of all input pins and driving capability of output pins 4 Timing specifications like setup and hold times, propagation delays and clock-eyele time. Z‘where gate and netlist constructs both are used along with hain ede ache inns dv Ae ig tow ional simulator test the logic of synthesis process. Logic cells and their st is an EDIF (Electronic Data Interchange Format) file. Thus during synthesis behavioral information in the HDL file is translated into a structural netlist. ¥) System Partitionit Its the process Vi) Prelayout sit This is required specific time period and recordi vii) Floorplanner ‘The main function of floorplanner is cell or module of the design. It is res tool that lets user generate and edit 12 a Large and complex system into smaller modules ign through software programs Here is to design over a ng the respective response from the model required chip area that will be used for each standard formance improvement to the design. Floorplanner is joorplans. vill) Place and Route ‘After design mapping, flow engine places and routes the design. All logic blocks including configurable Logic blocks (CLB) and input-output Blocks (IOB) are assigned specific locations on the die at place stage In the route stage, the logic blocks are assigned, particular interconnect elements on die.is carried out. While carrying out this simulation ections delays of interconnect are taken into account. If specifications, designer can proceed for chip finishing part ng and full custom editing layout data to out. It is the process of wut data to determine whether it conforms to the electrical design rules, schematic. Design Rule Check (DRC), Electrical Rule Check (ERC), it check are the processes which comes under physical verification foduetion of chips, itis necessary to have some sort of built-in tests for designed system {esis the system over long period of time. Chip will fail because of some electrical or that will usually show up with such testing procedure "Before submitting design for fabrication, input-output pads should be included in the design and “t's connectivity should be verified. Then appropriate package selection for the design and selecting ing plan. for the package is required. Details of how each pad of design is connected to each pin of package is required ‘Top-down and Bottom-up Design Approach ‘Top-down methodology This methodology is used for optimizing the design cells.which are at the top level of design hierarchy Floorplanning top-down methodology allows user to determine how signal should be bussed and assigned atthe top level of the design ‘After floorplanning, place and route of top-level cells, layout of lower-level cells in the hierarchy is. ‘completed. Here an accurate estimate of layout area is generated by placement and routing Bottom-up methodology “This methodology is used for optimizing the design cells which are atthe bottom level of design hierarchy Here first floor planning is carried out on leaf cells, which contain no underlying hierarchy Important features of bottom-up approach are 4) In the higher levels of the design hierarchy, placed and routed leaf cells are considered as instances. b) At every stage, layout area is exact, but layout process might be lengthy as more rework is necessary in ‘order to achieve required results ¢¢) Global optimization of layout area is not carned outBased cf weing on acttecnre cchhaly none of thse sya we can mk bo or more, esting a mized style. (1) Dataflow Style of Modelling: ‘Dataflow style describes system in terms of how data flows through the system. Data dependencies in ‘the description match those in a typical hardware implementation. | 2. A dataflow description directly implies a corresponding gate-level implementation. 3. Datafiow descriptions consist of one or more concurrent signal assignment statements. Eg Dataflow style half-adder description. The first assignment statement describes how input data flows from inputs a and b through an XOR function to create sum. ‘+ The second assignment statement describes how input data flows through an AND function to produce erry out, ‘+ Anytime there is an event on either input. the statements concurrently compute an updated value for each output= and component declaration ‘+The half adder is described as an interconnection of an XOR gate design entity and an AND gate design entity how the XOR gate and the AND gate are connected to implement a half : has a structural style description ‘© Design entity half_adder descr adder tis this top-level entity «= InVHDL, a component is actually a placeholder for a design entity. A structural design that uses components simply specifies the interconnection of the components used, each must be declared. A component declaration is similar to an entity es a listing ofthe component's name and its ports. Component declarations 1A gate-level logic implementation is sometimes referred to as a register transfer level (RTL) implementation.° ° Design methodologies and their features. Sequential and concurrent activities. Design exchange Standardization Documentation Readability Large-scale design ‘A wide range of descriptive capability srdware Description Languages) for describing electronic circuits and hardware simulation and synthesis. a2aempiey jo sisayuts ayy 304 0 aimpanysie warshs jo uonewnsa asuewuopiad Auea 104 0 asempiey jo UONeINWIS e104 © aGenbuel Buyjapow e sy 0 asempiey Buiquasaq 104 © ssasodind Bulmojjo} a4 40} PsN Si GHA é1GHA AUM “paseajai sem (saumyeaj MAN) 800Z-9/01 PuePUeIS 3331 “BOOZ © (SWY-TQHA) uorsuarxe jeubis pax Bojeuy :666L ° z “puepuers 9/01 3331 au jo wed e aweraq pue sjoor sisaynUAs Yum pasn a6ex2ed TGHA v :966L © aBenBue} ayy a>ueyus 01 pazipiepuers-a4 Sem TGHA E661 © “L864 "9401 psepuers 3331 awe22q IGHA pue ‘asodind jeoiauwo> 10} payed GOd =L86pports all CAD tools. strongly supports code reusability and code sharing. Disadvantages of VHDL A list of disadvantages of VHDL is given below: © It requires specific knowledge of the structure and syntax of the language. © Itis more difficult to visualize and troubleshoot a design. © Some VHDL programs cannot be synthesized. © VHDL is more difficult to learn. Basic Elements of VHDL ‘There are the following three basic elements of VHDL: 1. Entity The Entity is used to specify the input and output ports of the circuit. An Entity usually has one -an be inputs (in), outputs (out), input-outputs (inout), or buffer. ed to declare properties of the ‘or more ports that c ‘An Entity may also include a set of generic values that are us circuit. Entity Declaration nos new javatpoint. com ———————————L—<then it must be declared before the ports. Generic does not have a mode, f If an entity is generic, E s0 it can only pass information into the entity. Syntax: ae entity entity_name is generic ( generic_1_name : data_type; generic_2_name : data type; generic_n_name : data_type ‘nts java. comv“entity Logic Gates is “generic (Delay : Time := 10ns); | port ( | Input : in std_logic; | Input2 : in std_logic; Output : out std logic ys end Logic Gates; Rules for writing Port name: - Port name consist of letters, digits, and underscores. - It always begins with a letter. - Port name is case insensitive. Modes of Port in Input port out Output port | inout _ Bidirectional port buffer Buffered output port 2. Architecture Architecture is the actual description of the design, which is used to describe how the circuit operates. It can contain both concurrent and sequential statements. Tree tos www javatpoint.com/vhdlarchitecture synthesis of andg: begin <= a AND b; end synthesis; 3. Configuration A configuration defines how the design hierarchy is linked together. It is also used to associate architecture with an entity. Configuration Declaration configuration configuration_name of entity_name is --configuration declarations for architecture name for instance_label : component_name Use entity library_name.entity_name(architecture_name); end for, end for, end [configuration] {configuration name]; Example: np sNaajavatpoint com!There are 4 types of modeling styles in VHDL: = 1. Data flow modeling (Design Equations) Data flow modeling can be described based on the Boolean expression. It shows how the data flows from input to output. It works on Concurrent execution. % 2. Behavioral modeling (Explains Behaviour) Behavioral modeling is used to execute statements sequentially. It shows that how the system performs according to the current statement. Behavioral modeling may contain Process statements, Sequential statements, Signal assignment statements, and wait statements. 3, Structural modeling (Connection of sub modules) Structural modeling is used to specify the functionality and structure of the circuit. Structural modeling contain signal declarations, component instances, and port maps in component instance. VHDL objects VHDL uses the following three types of objects: 1. Constants Constant is an object which can only hold a single value that cannot be changed during the whole code. -ntps:wwacavatpoin. comvha! onin VHDL e abstract representation of stored data. ing data types in VHDL - data types are the set of positive and negative whole numbers. ting point data types are the set of positiv Enumeration data type is used to increase the readability of the code. © Physical f a base unit, multiples of base unit, anda Physical data type describes objects in terms of specified range. ee a ‘used anywhere within the architecture. Signals are point e and negative numbers that contain a1, Logical Operators Logical Operators are used to control the program flow. When the logical operators combined with signals or variables, then itis used to create combinational logic. VHDL supports the following logical operators: © and ° or © xnor © not 2. Relational Operators In VHDL, relational operators are used to compare two operands of the same data type, and the received result is always of the Boolean type. VHDL supports the following Relational Operators: © = Equal to © /= Not Equal to © <_Less than ‘tps-wwewjavatpoit. comb-yoysuaesns mojaq ayn ul MoUs se (QB BL'9 - AIYO/UVA) 29095 AX/L nel aajjeasuy ying 122195 pue UONe|TeASU] JaNPOAd [IN L'vL - SHINS u6ysaq 351 01 06 MON :zd way pL---¥ CLOZV/SIOOd Weil aah ua/xuiyx/iuaquo /Uny xapul/peojumop/oddns o> xu) mwwy/ /'scaY 400} 351 XUI]X au Peo|UMOP 0} Ul] MOJAq au UO Y>1I9 *LdarS = JO], 3S) XUIIIX aU) jTeISU! OF sdays BuIMo|TO} a4 218 S194. JOO] SI XUIIIX OLA |TEISUI