III Sem EC Components for Electronic Circuit Design Summer-2025

Priyadarshini Bhagwati College of Engineering

Department of Electronics & Communication Engineering
Rashtrasant Tukadoji Maharaj Nagpur University Examination
Summer-2025
Paper Solution
Semester : III Sem Marks: 70
Subject : Components for Electronic Circuit Design Paper Code :

Que. 1 (a)
Differentiate among conductor, insulator and semiconductor using energy band
concept. Also differentiate between N-type and P-type semiconductor material.

Solution :

• Based on Energy gap EG , the materials are classified as conductors, insulators and
semiconductors.

• In conductors, large number of free electrons exist at normal room temperature.

So EG does not exist. The valence and conduction bands are overlapped. This is
shown in figure 1(a). The examples are copper, aluminium, silver etc.

Figure 1: Energy band diagrams

• In insulators, the EG is very high about 7 eV. Hence at very high voltage or tem-
perature also, the electrons cannot move from valence to conduction band. Hence

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Summer-2025 Components for Electronic Circuit Design III Sem EC

these materials cannot conduct at all and called insulators. This is shown in the
figure 1(b). The examples are wood, mica, paper etc.

• In semiconductors, at absolute zero temperature (−273o C), the conduction band is

empty and they behave like perfect insulators. The energy gap EG is about 1 eV. At
normal termperature, some electrons move from valence to conduction band hence
few free electrons are available. Hence materials can conduct partially. At room
temperature EG = 1.12 eV for silicon and 0.78 eV for germanium. As temperature
increases the EG decreases and large number of free electrons are available. This is
shown in figure 1(c). The examples are silicon and germanium.

The p-type and n-type materials are two types of extrinsic semiconductors formed by
doping pure (intrinsic) semiconductors like silicon (Si) or germanium (Ge) with specific
impurities. Here is a clear differentiation:
Feature p-type Material n-type Material
Doping Element Trivalent (3 valence elec- Pentavalent (5 valence elec-
trons) e.g., Boron (B), Gal- trons) e.g., Phosphorus (P),
lium (Ga) Arsenic (As)
Majority Charge Carri- Holes (positive charge carri- Electrons (negative charge
ers ers) carriers)
Minority Charge Carri- Electrons Holes
ers
Charge Carrier Move- Current is mainly due to Current is mainly due to
ment movement of holes movement of electrons
Fermi Level Position Closer to the valence band Closer to the conduction band
Symbolic Representa- Often shown with an arrow Often shown with an arrow
tion in Circuits pointing inward in a diode pointing outward (cathode)
(anode)
Electrical Conductivity Slightly less than n-type due Slightly higher due to greater
to lower mobility of holes mobility of electrons

Que. 1 (b)

The saturation current density of Ge-diode is 200 mA/m3 at 300◦ K. Find voltage
to be applied across the junction to cause a forward current density of 105 A/m2 .

Solution :
The diode equation for current density is given by -
 qV 
J = Js e kT − 1

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III Sem EC Components for Electronic Circuit Design Summer-2025

Where:
J = Forward current density = 105 A/m2
Js = Saturation current density = 200 mA/m3 = 0.2 A/m2
V = Voltage across the junction
q = Charge of electron = 1.6 × 10−19 C
k = Boltzman’s Constant = 1.38 × 10−23 J/k
T = Temperature = 300 ◦ K
Now, putting the values in the above equation -
 
1.6×10−19 V
105 = 0.2 e 1.38×10−23 ×300 −1

Simplifying exponential term -

q 1.6 × 10−19
= = 38.6
kT 1.38 × 10−23 × 300

So,
105 = 0.2 e38.6V − 1

105
= e38.6V − 1
0.2
∴ e38.6V = 526
38.6V = ln(526) = 6.266
6.266
∴V =
38.6
∴ V = 0.162 V

Que. 2 (a)
Explain drift current and diffusion current in semiconductor.

Solution :
In semiconductors the flow of current is due to two actions namely drift and diffusion.

Drift Current
• When a voltage is applied to a semiconductor, the free electrons try to move in a
straight line towards the positive terminal of the battery.

• The electrons, moving towards positive terminal collide with the atoms of semicon-

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Summer-2025 Components for Electronic Circuit Design III Sem EC

ductor and connecting wires, along its way. Each time the electrons strikes an atom,
it rebounds in a random direction.

• But still the applied voltage make the electrons drift towards the positive terminal.
This drift causes current to flow in a semiconductor, under the influence of the
applied voltage.

• This current produced due to drifting of free electrons is called drift current and the
velocity with which electrons drift is called drift velocity.

• Thus drift current means the flow of current due to bouncing of electrons from one
atom to another, traveling from negative terminal to positive terminal of the applied
voltage.

The direction of conventional current is always opposite to the direction of

drifting electrons.

This is shown in figure 2.

Figure 2: Drift mechanism causing drift current

Diffusion Current
• This is the current which is due to the transport of charges occurring because of
nonuniform concentration of charged particles in a semiconductor.

• Consider a piece of semiconductor which is non-uniformly doped. Due to such

nonuniform doping, one type of charge carriers occur at one end of a piece of semi-
conductor.

• The charge carriers are either electrons or holes, of one type depending upon the
impurity used.

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III Sem EC Components for Electronic Circuit Design Summer-2025

• They have the same polarity and hence experience a force of repulsion between
them.

• The result is that there is a tendency of the charge carriers to move gradually i.e.
to diffuse from the region of high carrier density to the low carrier density. this
process is called diffusion.

• This movement of charge carriers under the process of diffusion constitutes a cur-
rent called diffusion current. This is shown in the figure 3.

• The diffusion current continues till all the carriers are evenly distributed throughout
the material.

• A diffusion current is possible only in case of non-uniformly doped semiconductors

while drift current is possible in semiconductors as well as conductors.

Figure 3: Diffusion Current

The diffusion current exists without external voltage applied while drift cur-
rent cannot exist without an external voltage applied.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Que. 2 (b)
What is meant by extrinsic semiconductor? Explain its types.

Solution :

Extrinsic Semiconductor
• As pure intrinsic semiconductor has poor conductivity, some impurity is added to it
to increase the conductivity. Such impurity is purposely added to make the material
suitable for manufacturing of the semiconductor devices. Such impure semicon-
ductor is called an extrinsic semiconductor.

• The process of adding other materials to an intrinsic semiconductor, to improve its

conductivity is called extrinsic semiconductor.

• The impurity added is called dopant and the resulting doped semiconductor mate-
rial is called extrinsic semiconductor.

• There are two types of impurities used to obtain two differnt types of extrinsic
semiconductors called p-type and n-type.

• The impurity having five valence electrons is called pentavalent impurity. When it
is added, its each atom donates one free electron and such doping is called donor
doping. The examples of pentavalent impurity are arsenic, bismuth, phosphorous
etc. this creates n-type extrinsic semiconductor.

• The impurity which has three valence electrons is called trivalent impurity. When
this is added, its each atom creates one hole which is ready to accept an electron.
Hence this is called acceptor doping. The examples of trivalent impurity are gal-
lium, indium and boron,. This creates p-type extrinsic semiconductor.

n-type Semiconductor

• Consider a pentavalent impurity like arsenic (As) is added to Silicon (Si). It is a

donor impurity with five valence electroncs.

• The arsenic atom fits in the silicon crystal in such a way that its four valent elec-
trons form covalent bonds with four adjacent silicon atoms. Remember that both
germanium and silicon have four electrons in the valence orbit.

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III Sem EC Components for Electronic Circuit Design Summer-2025

• The fifth electron of arsenic has no chance to form covalent bond, hence this elec-
tron enters in conduction band as a free electron. Thus each As atom added to Si
atom donates one free electron. This is shown in the figure 4.

Figure 4: N-type material formation.

• The number of free electrons can be controlled by the amount of impurity added.

• Since the free electrons have negative charges, the material obtained is called n-type
extrinsic semiconductor.

p-type Semiconductor

• Consider a trivalent impurity like Gallium (Ga) is added to Silicon (Si). It is an

impurity with three valence electrons.

Figure 5: p-type material formation

• The gallium atom fits into the silicon crystal in such a way that its three valence
electrons form covalent bonds with the three adjacent silicon atoms. There is short-
age of one electron to form a covalent bond. This creates a vacancy in the forth

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Summer-2025 Components for Electronic Circuit Design III Sem EC

covalent bond which is nothing but a hole. Thus each Ga atom added into Si atom
creates one hole which is ready to accept an electron. This is shown in the figure 5.

• The number of such holes can be controlled by the amount of impurity added to the
silicon.

• As the holes are treated as positively charged, the material obtained is called p-type
extrinsic semiconductor.

Que. 3 (a)
Draw and explain V-I characteristics of P-N junction diode.

Solution :
The response of p-n junction diode can be easily indicated with the help of characteristics
called V-I characteristics of p-n junction. It is the graph of voltage applied across the p-n
junction and the current flowing through the p-n junction.

Forward V-I characteristics of Diode

The figure 6 shows the forward biased diode. The applied voltage is V while the voltage
across the diode if Vf . The current flowing in the circuit is the forward current If . The
graph of forward current If against the forward voltage Vf across the diode is called
forward characteristics of a diode.

Figure 6: Forward Biased Diode

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III Sem EC Components for Electronic Circuit Design Summer-2025

The forward characteristics of a diode is shown in the figure 7.

Basically forward characteristics can be divided into two regions :

• Region O to P : As long as Vf is less than cut-in votage Vγ , the current flowing is

very small. Practically this current is assumed to be zero.

• Region P to Q and onwards : As Vf increases towards Vγ the width of depletion

region goes on reducing. When Vf exceeds Vγ i.e. cut-in voltage, the depletion
region becomes very thin and current If increases suddenly. This increase in the
current is exponential as shown in the figure ?? by the region P to Q.

• The point P, after which the forward current starts increasing exponentially is called
knee of the curve and the corresponding voltage is called knee voltage.

• The forward current is the conventional current hence it is treated as positive and
the forward voltage Vf is also treated positive. Hence the forward characteristics is
plotted in the first quadrant.

Figure 7: Forward characteristics of diode

Reverse Characteristics of P-N junction diode

The figure 8 shows the reverse biased diode. The reverse voltage across the diode is VR
while the current flowing is reverse current IR flowing due to minority charge carriers.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Figure 8: Reverse biased diode

The graph of IR against VR is called reverse characteristics of a diode.

Figure 9:

The polarity of reverse votage applied is opposite to that of forward voltage. Hence
in practice reverse voltage is taken as negative. Similarly the reverse saturation current is
due to minority carriers and is opposite to the forward current. Hence in practice reverse
saturation current is also taken as negative. Hence the reverse characteristics is plotted in
the third quadrant as shown in figure 9.

As reverse voltage is increased, reverse current increases initially but after a certain
voltage, the current remains constant equal to reverse saturation current I0 though reverse
voltage is increased. The point A where breakdown occurs and reverse current increases
rapidly is called knee of the reverse characteristics. The voltage corresponding to point A
is called reverse breakdown voltage VBR of diode.

The complete V-I characteristics of a diode is drawn as -

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III Sem EC Components for Electronic Circuit Design Summer-2025

Figure 10: Complete V-I characteristics of diode

Que. 3 (b)
What is meant by voltage regulator? How zener diode can be used as Voltage
Regulator?

Solution :

A voltage regulator is an electronic device or circuit that maintains a constant out-

put voltage regardless of changes in Input voltage (supply fluctuations) and Load
conditions (change in current drawn).

Voltage regulators are critical in power supplies to protect sensitive electronic compo-
nents from voltage variations.

Zener Diode as a Voltage Regulator

A Zener diode is a special type of diode designed to operate in the reverse breakdown
region without damage. It is widely used as a voltage regulator because it maintains a
constant voltage across its terminals when reverse biased and operating in breakdown.

Figure 11: Zener Diode as Shunt Regulator

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Summer-2025 Components for Electronic Circuit Design III Sem EC

• The simplest shunt voltage regulator circuit uses a zener diode, to regulate the load
voltage. The figure 11 shows the arrangement of zener diode in regulator circuit.

• The zener diode has the characteristic that as long as the current through it is in
between Izmin and Izmax , the voltage across it is constant equal to zener voltage Vz .

• As zener diode is connected in shunt with the load resistance, the output voltage is
equal to zener voltage.

• The value of R can be obtained mathematically as -

Vin − Vz Vin − Vz
R= i.e. I =
I R

• The relation between the various current is given by -

I = Iz + IL

• Figure 12 shows the zener regulator under varying input condition.

Figure 12: Varying input condition

• It is seen that the output is - Vo = Vz = Constant.

Vo Vz
∴ IL = = = constant
RL RL

• Now if Vin increases, then the total current I increases. But IL is constant as Vz is
constant. Hence the current Iz increases to keep IL constant.

• But as long as Iz is in between Izmin and Izmax , the Vz i.e. Vo is constant. Thus the
changes in input voltage is compensated and output is maintained constant.

• Similarly if Vin decreases, then current I decreases. But to keep IL constant, Iz

decreases. As long as Iz is in between Izmin and Izmax , the output voltage remains
constant.

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III Sem EC Components for Electronic Circuit Design Summer-2025

• The figure ?? shows the zener regulator under varying load conditions and constant
input voltage.

Figure 13: Varying load conditions

• The input voltage is constant, while the load resistance RL is variable.

• As Vin is constant and Vo = Vz is constant, then for constant R, the current I is

constant.
Vin − Vz
I= constant = IL + Iz
R

• Now if RL decreases, so IL increases, so to keep I constant, Iz decreases. But as

long as Iz is in between Izmin and Izmax , output voltage Vo will be constant.

• Similarly if RL increases, so IL decreases, so to keep current I constant, Iz in-

creases. But as long as it is in between Izmin and Izmax , output voltage Vo remains
constant.

• Thus irrespective of the changes in the line voltage or changes in the load, the output
voltage remains constant.

Que. 4 (a)
Draw and explain the working of half wave rectifier with diode current and output
voltage waveforms. Derive the expression for various terms Im , Idc , Iac , ripple
factor and efficiency η.

Solution :

Half Wave Rectifier

In half wave rectifier, rectifying element conducts only during positive half cycle of input
a.c. supply. The negative half cycles of a.c. supply are eliminated from the output.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Construction of HWR

This rectifier circuit consists of resistive load, rectifying element, i.e. p-n junction diode,
and the source of a.c. voltage, all connected in series. The circuit diagram is shown in fig.
14. Usually, the rectifier circuit is operated from a.c. mains supply. To obtain the desired
d.c. voltage across the load, the a.c. voltage is applied to rectifier circuit using suitable
step-up or step-down transformer, mostly a step-down one, with necessary turns ratio.
The input voltage to the half wave rectifier circuit shown in fig 14 is a sinusoidal a.c.
voltage, having a frequency which is the supply frequency, 50 Hz.
The transformer decides the peak value of the secondary voltage. If the N1 are primary
number of turns and N2 are secondary number of turns and Epm is the peak value of the
primary voltage then,
N2 Esm
=
N1 Epm
where Esm is the peak value of the secondary a.c. voltage.

Figure 14: Half Wave Rectifier

As the nature of Esm is sinusoidal the instantaneous value will be

es = Esm sin ωt

ω = 2πf

f = supply frequency

Let Rf represents the forward resistance of the diode. Assume that, under reverse bias
condition, the diode acts almost as open circuit, conducting no current.

Operation of Circuit

During the positive half cycle of secondary a.c voltage, terminal (A) becomes more posi-
tive with respect to terminal (B). The diode is forward biased and the current flows in the
circuit in the clockwise direction, as shown in fig ??. The current will flow for almost full

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III Sem EC Components for Electronic Circuit Design Summer-2025

positive cycle. This current is also flowing through load resistance RL , hence denoted as
iL , the load current.
During negative half cycle when terminal (A) is negative with respect to terminal (B),
diode becomes reverse biased. Hence no current flows in the circuit. Thus the circuit
current, which is also the load current, is in the form of half sinusoidal pulses.
The load voltage, being the product of load current and load resistance, will also be in
the form of half sinusoidal pulses. The different waveforms are illustrated in fig. 15.
The d.c. output waveform is expected to be a straight line but the half wave rectifier
gives output in the form of positive sinusoidal pulses. Hence the output is called pulsating
d.c. It is discontinuous in nature.

Figure 15: Load current and Load voltage waveforms for half wave rectifier

Expression for Average DC Load Current / Output Current (IDC )

The average or dc value of alternating current is obtained by integration. For finding out
the average value of an alternating waveform, we have to determine the area under the
curve over one complete cycle i.e. from 0 to 2π and then dividing it by the base i.e. 2π .
Mathematically, the expression for load current is given by,

iL = Im sin ωt f or0 ≤ ωt ≤ π

iL = 0 f orπ ≤ ωt ≤ 2π

where, Im is the peak value of load current.

Z 2π Z 2π
1 1
IDC = iL d(ωt) = Im sin(ωt)d(ωt)
2π 0 2π 0

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Summer-2025 Components for Electronic Circuit Design III Sem EC

As no current flows during negative half cycle of a.c. input voltage, ie. between ωt = π
to ωt = 2π we change the limits of integration.

Im π
Z
IDC = sin(ωt)d(ωt)
2π 0
Im
IDC = [− cos(ωt)]π0
2π
Im
IDC = [cos(π) − cos(0)]
2π

Im
IDC = − [−1 − 1]
2π
Im
IDC = = average value
π

Applying Kirchoff’s voltage law, we can write,

Esm
Im =
Rf + RL + RS
where, Rs = resistance of secondary winding of transformer. If Rs is not given it should
be neglected while calculating Im .

RMS Load Current IRM S

The R.M.S. value of current, IRM S is obtained as follows:

s
Z 2π
1
IRM S = i2L d(ωt)
2π 0

Since two half wave rectifier are similar in operation we can write,
s Z π
2
IRM S = [Im sin ωt]2 d(ωt)
2π 0
s Z 
1 π 1 − cos 2ωt

IRM S = Im d(ωt)
π 0 2
s   π 
1 π sin 2ωt
IRM S = Im [ωt]0 −
2π 2 0
r
1
IRM S = Im [π − 0]
2π

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III Sem EC Components for Electronic Circuit Design Summer-2025
r
1
IRM S = Im (π)
2π
Im
IRM S = √
2

Rectifier Efficiency (η)

PDC output
η=
PAC input
4 2
I R
π2 m L
η= 2 (R +R +R )
Im f S L
2
8RL
η=
π 2 (Rf + RL + RL )

But , if Rf + RS is very small as compared to RL , neglecting it from denominator, we get

8 RL
η=
π 2 RL
8
η= 2
π
8
%ηmax = 2 × 100 = 81.2%
π

This is the maximum theoretical efficiency of full wave rectifier.

Ripple Factor (γ)

The general expression for ripple factor is :

s 2
IRM S
γ= −1
IDC

Now for Full wave rectiifer circuit,

Im
IRM S = √
2
2Im
IDC =
π

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Putting these values in expression for ripple factor, we get

v"
u Im # 2
u √
γ = t 2Im2 −1
π
r
π2
γ= −1
8
γ = 0.48

This indicates that the ripple contents in the output are 48 % of the d.c. component which
is much less than that for half wave circuit.

Que. 4 (b)
A full wave centre tapped rectifier is driven from 20-0-20 Vrms voltage, 50 Hz
transformer. The load resistance is 10 Ω.Find DC voltage, DC current, ripple factor,
efficiency η.

Solution :
The center tapped transformer is fed from 20-0-20 Vrms votlage transformer.
√
∴ (Es (rms)) = 20 V, ∴ Esm = 2 × Es(rms)
∴ Esm = 28. 28 V
RL = 10Ω
The d.c. voltage of full wave rectifier is given by -

2Esm
Edc =
π
2 × 28.28
∴ Edc = = 18 V
π

The maximum load current is given by -

Esm
Im =
(Rs + Rf + RL )
28.28
∴ Im = = 2.828 A
10

Since Rs , Rf are not given, they are assumed to be zero.

The d.c. output current is given by -

2Im
Idc =
π
2 × 2.828
∴ Idc = = 1.8 A
π

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III Sem EC Components for Electronic Circuit Design Summer-2025

The RMS load current for full wave rectifier is given as -

Im 2.828
Irms = √ = √ = 2 A
2 2

The Ripple factor for full wave rectifier is -

s 2
Irms
r= −1
Idc
s 
2
2
∴r= −1
1.8
∴ r = 0.48

The input a.c. power to the rectifier is -

2
Pac = Irms × (Rs + Rf + RL )
∴ Pac = (2)2 × 10 = 40 Watts

The D.c. output power is given by -

Pdc = Idc2 RL
∴ Pdc = (1.8)2 × 10
∴ Pdc = 32.4 Watts

Therefore, the efficiency of the center tapped full wave rectifier is -

Pdc
%η = × 100
Pac
32.4
%η = × 100
40
∴ %η = 81%

Que. 5 (a)
Draw the experimental setup for CE configuration of transistor. Explain its I/P, O/P
characteristics with the help of graph.

Solution :
In this configuration, input is applied between base and emitter, and output is taken from
collector and emitter. Here, emitter of the transistor is common to both, input and output
circuits, and hence the name common emitter configuration.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

The input voltge in the common-emitter configuration is the base-emitter voltage VBE
and the output voltageis the collector-emitter voltage VCE .The input current is IB and the
output current is IC .

Figure 16: Transistors connected in Common Emitter Configuration

Input Characteristics
It is the curve between input current IB (base current) and input voltage VBE (base-emitter
voltage) at constant collector-emitter voltage VCE . The base current is taken along Y- axis
and base-emitter voltage VBE is taken along X-axis.
From this characteristics we observe the following important points :

1. As the input to a transistor in the CE configuration is between the base-to-emitter

junction, the CE input characteristics resembles a family of forward biased diode
curve.

2. After the cut-in voltage the base current IB increases rapidly with small increase
in base emitter voltage VBE . it means that dynamic input resistance is small in
CE configuration. It is the ratio of change in base-emitter voltage (△VBE ) to the
resulting change in base current (△IB ) at constant collector-emitter voltage VCE . It
is given by –
△VBE
ri = (1)
△IB

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Figure 17: Input Characteristics of Common Emitter Configuration

3. For a fixed value of VBE , IB decreases as VCE is increased. A large value of VCE
results in a large reverse bias at collector-base P-N junctions. This increases the
depletion region and reduces the effective width of the base. Hence, there are fewer
recombinations in the base region, reducing the base current IB .

Output Characteristics
1. This characteristics shows the relation between the collector current IC and collec-
tor voltage VCE , for various fixed values of IB . This characteristics is often called
collector characteristics.

Figure 18: Output Characteristics of Common Emitter Configuration

2. The value of βdc of the transistor can be found at any point on the characteristics by
taking the ratio of IC to IB at that point, βdc = IIBC . This is known as DC beta for

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Summer-2025 Components for Electronic Circuit Design III Sem EC

the transistor. For a fixed value of VCE , if we take the ratio of small change in IC
△IC
(i.e. △IC ) to small change in IB (i.e. △IB ), we get a.c. beta; βac = △I B
.

3. From the output characteristics we can see that change in collector-emitter voltage
(△VCE ) causes the little change in the collector current (△IC ) for constant base
current IB . Thus the output dynamic resistance is high in CE configuration.

△VCE
ro = (2)
△IC

4. The output characteristics of common emitter configuration consists of three re-

gions : Active, Saturation and Cut-off region.

Que. 5 (b)
Explain the term Base Width Modulation.

Solution :

• As shown in figure ??, the width of the base region occupied by charge particles is
known as electrical witdth or physical width of the base region.

• Since doping in the base is ordinarily substantially smaller than that of the collector,
the penetration of the transition region into the base is much larger than into the
collector. Hence the base depletion region is large.

Figure 19: Base width

• Here, when reverse bias voltage VCB increases, the width of the depletion region in
base region also increases, which reduces the electrical base width (WB′ ).

• Due to reduction of electrical base width, now there are more charge particles per
unit area. In other words, due to reduction of electrical base width, concentration
of the charge gradient increases in the base region. This increase in concentration

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III Sem EC Components for Electronic Circuit Design Summer-2025

of charge carriers causes more diffusion of electrons from n-type emitter to p-type
base increasing emitter current slightly.

Figure 20: Change in base and depletion region width with change in reverse biased
voltage

• The increase in reverse bias voltage VCB , the width of depletion region increases,
which reduces the electrical base width. This effect is called as ’Early Effect’ or
Base width modulation’. This effect can be explained with the help of equation -

e · NA · W 2
V =
2ϵ

where, V = Reverse bias voltage and W = Width of the space charge region/depletion
region.

• As we know, the depletion width is more on the lightly doped region, i.e. base
region, this effect is more in the base region reducing the effective (electrical) base
width.

• This decrease in base width has two consequences :

1. There is less chance for recombination within the base region. Hence the
transport factor β and also α, increase with an increase in the magnitude of
the collector junction voltage.
2. The charge gradient is increased within the base and consequently, the current
of minority carriers injected across the junction increases.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Que. 6 (a)
Why biasing of BJT is necessary? Explain the types of biasing.

Solution :

Need of Biasing
We can operate transistor in any of the three regions ; cut-off, active and saturation by
applying proper biasing condition as shown in table

Region of operation Emitter Junction Collector Junction

Cut-off Region Reverse Biased Reverse Biased
Active Region Forward Biased Reverse Biased
Saturation Region Forward Biased Forward Biased
Table 1: Region of operation of transistor

In order to operate transistor in the desired region, we have to apply external d.c.
voltages of correct polarity and magnitude to the two junctions of the transistor. This
is nothing but the biasing of the transistor. Because d.c. voltages are used to bias the
transistor, biasing is known as d.c. biasing of the transistor.

Types of Biasing
The different types of biasing circuits that are used for transistors are :

1. Fixed Bias Circuit

2. Collector to Base Bias Circuit
3. Voltage Divider Bias Circuit

Fixed Bias Circuit

Figure 21 shows the fixed bias circuit. Applying Kirchoff’s voltage law to the base circuit,
we get,

VCC − IB RB − VBE = 0 (3)

∴ IB RB = VCC − VBE (4)
VCC − VBE
∴ IB = (5)
R

PBCOE, Nagpur 24 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

As VBE ≪ VCC , we get,

VCC
IB ≈ (6)
RB

Figure 21: Fixed Bias Circuit

The supply voltage VCC is of fixed value. Once the resistance RB is selected, IB is
also fixed. Hence this circuit is called fixed bias circuit.
Applying Kirchoff’s voltage law to the collector circuit, we get,

VCC − IC RC − VCE = 0 (7)

∴ VCE = VCC − IC RC (8)

The collector current in CE configuration is given as ,

IC = βIB + ICEO ≈ βIB (9)

Since βIB ≫ ICEO

∴ VCC = IC RC + VCE (10)

VCC − VCE
∴ IC = (11)
RC

i.e. supply voltage provides the voltage across RC and the collector to emitter voltage.
Therefore voltage drop across RC can never be more than VCC .

∴ IC RC < VCC (12)

VCC
∴ IC < (13)
RC

If IC becomes greater than the value limited by above expression, the operating point will
lie in the saturation region of the characteristics.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Collector to Base Bias Circuit

Figure 22 shows collector to base bias circuit. It is an improvement over the fixed bias
method. In this the biasing resistor is connected between the collector and the base ter-
minals of the transistor. Thus IB flows through RB and (IC + IB ) flows through the
RC .

Figure 22: Collector-Base Bias circuit

Applying KVL to the base circuit, we get,

VCC − (IB + IC )RC − IB RB − VBE = 0 (14)

∴ VCC = (RB + RC )IB + IC RC + VBE (15)

(VCC − IC RC ) − VBE
∴ IB = (16)
RB + RC
IC (VCC − IC RC ) − VBE
∴ = (17)
β RB + RC
β(VCC − IC RC − VBE )
∴ IC = (18)
RB + RC

Applying Kirchoff’s voltage law to the collector circuit, we get,

VCC − (IC + IB )RC − VCE = 0 (19)

∴ VCE = VCC − (IC + IB )RC (20)
∴ VCE = VCC − IC RC − IB RC (21)
∴ VCC − IC RC = VCE + IB RC (22)

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III Sem EC Components for Electronic Circuit Design Summer-2025

Substituting this value of VCC − IC RC in equation (16) , we get,

VCE + IB RC − VBE
IB = (23)
RB + RC

If there is a change in β due to piece to piece variation between transistors or if there is a

change in β and ICO due to change in temperature, then the collector current IC tends to
increase, since IC = βIB + ICEO . As a result, voltage drop across RC increases. Since
supply voltage VCC is constant, due to increase in IC RC , VCE decreases. Due to reduction
in VCE , IB reduces. As IC depends on IB , decrease in IB reduces the original increase
in IC . The result is that the circuit tends to maintain a stable value of collector current,
keeping the Q point fixed.
In this circuit, RB appears directly across input (Base) and output (Collector). A
part of the output is fed back to the input and increase in collector current decreases the
base current. Thus negative feedback exists in the circuit, so this circuit is called voltage
feedback bias circuit.

Self Bias Circuit of BJT

Figure 23 shows the voltage divider bias circuit.
In this circuit, the biasing is provided by three resistors : R1 , R2 and RE . The resistor
R1 and R2 acts as a potential divider giving a fixed voltage to point B which is base. If
the collector current increases due to change in temperature or change in β, the emitter
current IE also increases and the voltage drop across RE increases, reducing the voltage
difference between base and emitter VBE . Due to reduction in VBE , the base current IB
and hence the collector current IC also reduces. This reduction in collector current IC
compensates for the original change in IC .

Figure 23: Voltage Divider Bias Circuit

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Let us consider the base circuit. Voltage drop across R2 is the base voltage VB . Ap-
plying voltage divider theorem to find VB , we get,

R2
VB = VCC (24)
R1 + R2

Let us now consider the collector circuit. Voltage across RE i.e. VE can be obtained as ,

VE = IE RE = VB − VBE (25)
VB − VBE
∴ IE = (26)
RE

Applying KVL to the collector circuit, we get,

VCC − IC RC − VCE − IE RE = 0 (27)

∴ VCE = VCC − IC RC − IE RE (28)

Figure 23 shows simplified circuit of voltage divider bias. Here R1 and R2 are replaced by
RB and VT , where RB is the parallel combination of R1 and R2 and VT is the Thevenin’s
voltage.
RB can be calculated as –
R1 R2
RB = (29)
R1 + R2
Applying KVL to the base circuit, we get,

VT − IB RB − VBE − IE RE = 0 (30)
∴ VT = IB RB + VBE + IE RE (31)
∴ VT = VBE + (RB + RE )IB + IC RE (32)
∴ VBE = VT − (RB + RE )IB − IC RE (33)

PBCOE, Nagpur 28 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

Que. 6 (b)
In the circuit shown, VCC = 24 V, RC = 10 kΩ, RE = 270 Ω. A silicon transistor
is used with β = 45 and VCE = 5 volt. Find resistor ‘R’. Neglect reverse saturation
current.

Solution :

Applying KVL to the collector circuit we get,

VCC − (IB + IC )RC − VCE − (IB + IC )RE = 0

∴ VCC − (1 + β)IB RC − VCE − (1 + β)IB RE = 0
∴ VCC − VCE − (1 + β)IB (RC + RE ) = 0
∴ 24 − 5 − (1 + 45)IB (10 × 103 + 270) = 0
19
∴ IB =
46 × (10 × 103 + 270)
∴ IB = 40.2 µA

Now, applying KVL to the base circuit we get,

VCC − (IB + IC )RC − IB RB − VBE − (IB + IC )RE = 0

∴ VCC − VBE − (1 + β)IB RC − IB RB − (1 + β)IB RE = 0
∴ 24 − 0.6 − (46)(40.2 × 10−6 )(10 × 1063 + 270) − 40.2 × 10−6 RB = 0
 

∴ 4.4 = 40.2 × 10−6 RB

∴ RB = 109.5 kΩ

L: Dr. P.R. Bokde 29 PBCOE, Nagpur

Summer-2025 Components for Electronic Circuit Design III Sem EC

Que. 7 (a)
Explain the construction and working of N-channel MOSFET in enhancement and
depletion modes with the help of static drain characteristics.

Solution :

N-channel MOSFET in Depletion Mode

Figure 24 shows the basic construction of n-channel depletion type MOSFET. Two highly
doped n-regions are diffused into a lightly doped p-type substrate. These two highly doped
n-regions represent source and drain. In some cases, substrate is internally connected to
the source terminal.

Figure 24: n-channel depletion type MOSFET

The source and drain terminals are connected through metallic contacts to n-doped
regions linked by an n-channel as shown in figure 24. The gate is also connected to a
metal contact surface but remains insulated from the n-channel by a very thin layer of
dielectric material, silicon dioxide (SiO2 ). Thus, there is no direct electrical connection
between the gate terminal and the channel of a MOSFET, increasing the input impedance
of the device.
Operation :

On the application of drain to source voltage VDS and keeping gate to source voltage
to zero by directly connecting gate terminal to the source terminal, free electrons from
the n-channel are attracted towards positive potential of drain terminal. This establishes
current through the channel to be denoted as IDSS at VGS = 0 V as shown in figure 25.
If we apply negative voltage, the negative charges on the gate repel conduction elec-
trons from the channel, and attracts holes from the P-type substrate. This initiates recom-

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III Sem EC Components for Electronic Circuit Design Summer-2025

bination of repelled electrons and attracted holes as shown in figure 26.

Figure 25: Operation of n-channel Depletion type MOSFET

Figure 26: Figure showing recombination of electrons and holes

The level of recombination between electrons and holes depends on the magnitude of
the negative voltage applied at the gate. This recombination reduces the number of free
electrons in the n-channel for the conduction, reducing the drain current.
In other words, we can say that, due to recombinations, n-channel is depleted of some
of its electrons, thus decreasing the channel conductivity. The greater the negative voltage
applied at the gate, the greater the depletion of n-channel electrons. The level of drain
current will reduce with increasing negative bias for VGS as shown in figure27 transfer
characteristics of depletion type MOSFET.
For positive values of vGS the positive gate will draw additional electrons from the
p-type substrate due to reverse leakage current and establish new carrier through the col-
lisions between accelerating particles. Because of this, as gate to source voltage increases
in positive direction, the drain current also increases as shown in figure 27.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Figure 27: Transfer characteristics of n-channel Depletion type MOSFET

The application of a positive gate to source voltage has "enhanced" the level of free
carriers in the channel compared to that encountered with VGS = 0 V. For this reason
the region of positive gate voltages on the drain or transfer characteristics is referred to
as enhancement region and the region between cut-off and the saturation levels of IDSS
referred to as depletion region.

Figure 28: Drain characteristics of n-channel Depletion type MOSFET

Figure 28 shows the drain characteristics for an n-channel depletion type MOSFET.
It is similar to that of JFET. The only difference is that it has positive part of VGS . The
following points can be noted :

1. ID = 0 corresponds to VGS(of f ) = −Vp

2. VGS = 0 corresponds to IDSS .

3. Both positive and negative values of VGS can be used to bias D-MOSFET.

N-channel MOSFET in Enhancement Mode

Figure 29 shows the basic construction of n-channel enhancement type MOSFET.

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III Sem EC Components for Electronic Circuit Design Summer-2025

Figure 29: n-channel Enchancement type MOSFET

Like depletion type MOSFET, two highly doped N-regions are diffused into a lightly
doped P-type substrate. The source and drain are taken out through metallic contacts to
N-doped regions as shown in figure. But the channel between two N-regions is absent in
the enhancement type MOSFET. The SiO2 layer is still present to isolate the gate metal-
lic platform from the region between the drain and source, but now it is simply separated
from a section of the P-type material.
Operation :

Figure 30: Operation of n-channel Enhancement type MOSFET

On application of drain to source voltage VDS and keeping gate to source voltage zero
by directly connecting gate terminal to the source terminal, practically zero current flows.
If we increase magnitude of VGS in the positive direction, the concentration of electrons
near the SiO2 surface increases. At a particular value of VGS there is a measurable current
flow between drain and source. This value of VGS is called threshold voltage denoted
by VT . Thus we can say that in an enhancement type n-channel MOSFET, a positive
gate voltage above the threshold value induces a channel and hence the drain current by
creating a thin layer of negative charges in the substrate region adjacent to the SiO2 layer
as shown in figure. The conductivity of the channel is enhanced by increasing the gate to
source voltage and thus pulling more electrons into the channel. For any voltage below
the threshold value, there is no channel.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Since the channel does not exist with VGS = 0V and enhanced by the application of
a positive gate to source voltage, this type of MOSFET is called an enhancement type
MOSFET.

Figure 31: Drain Characteristics of n-channel Enhancement type MOSFET

Figure 31 shows the drain characteristics of an n-channel enhancement type MOSFET.

From figure we can say that as VGS increases beyond the threshold level, the density of
free carriers (electrons) in the induced channel increases, increasing the drain current.
However, at some point of VDS , for constant VGS , the drain current reaches a saturation
level. The leveling off of ID is due to a pinch-off process.

Figure 32: Transfer Characteristics of n-channel Enhancement type MOSFET

Figure 32 shows the transfer characteristics for n-channel enhancement type MOS-
FET. For an n-channel enhancement type MOSFET, it is totally in the positive VGS region
and ID does not flow until VGS = VT .
For VGS > VT the relationship between drain current and VGS is non-linear and it is
given as -
ID = K(VGS − VT )2 (34)

The term K is a constant that is a function of the construction of the device. The value of
K can be determined from equation,

ID(ON )
K=
2 (35)
VGS(ON ) − VT

PBCOE, Nagpur 34 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

Que. 7 (b)
Compare merits and demerits of Bipolar Junction Transistor (BJT) with Field Ef-
fect Transistor (FET).

Solution :

Structure & Operation

Feature BJT FET

Type Current-controlled device Voltage-controlled device
Structure Consists of three layers (NPN or Consists of a gate, source, and
PNP) drain
Operation Princi- Uses both electrons and holes for Uses either electrons (in n-
ple conduction (bipolar) channel) or holes (in p-channel)
(unipolar)
Control Mecha- Controlled by base current Controlled by gate voltage
nism
Both Bipolar Junction Transistors (BJTs) and Field Effect Transistors (FETs) are
widely used in electronic circuits, but they differ in their structure, operation, and ap-
plications. Below is a detailed comparison of their merits and demerits.

Merits

Advantages of BJT:

1. High Gain - BJTs provide a high current gain (β), making them useful in amplifi-
cation applications.

2. Better Transconductance – BJTs generally have higher transconductance, allow-

ing better performance in analog circuits.

3. Fast Switching Speed – In some applications, BJTs can switch faster due to their
conduction mechanism.

4. Stronger Drive Capability – BJTs provide strong current output, useful for driving
low-impedance loads.

5. Lower ON Resistance – BJTs have a lower ON-state resistance compared to MOS-

FETs in certain cases.

Advantages of FET:

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Summer-2025 Components for Electronic Circuit Design III Sem EC

1. High Input Impedance – FETs have a very high input impedance (typically in
megaohms), reducing the loading effect on preceding stages.

2. Low Power Consumption – Since FETs are voltage-controlled, they consume very
little power at the gate.

3. Thermal Stability – FETs exhibit better thermal stability, making them less prone
to thermal runaway.

4. Low Noise – FETs generate less noise, which is important for signal processing
and RF applications.

5. Smaller Size – FETs, especially MOSFETs, are smaller and widely used in VLSI
and IC technology.

Demerits (Disadvantages)

Disadvantages of BJT:

1. Higher Power Consumption – Since BJTs require continuous base current, they
consume more power.

2. Low Input Impedance – BJTs have a lower input impedance, which can affect
signal amplification.

3. Thermal Runaway – BJTs are more prone to thermal runaway due to their negative
temperature coefficient.

4. Larger Size in ICs – Compared to MOSFETs, BJTs are less suitable for integration
into large-scale ICs.

Disadvantages of FET:

1. Lower Gain – FETs generally have lower voltage gain than BJTs.

2. More Susceptible to Static Damage – FETs, particularly MOSFETs, are highly

sensitive to electrostatic discharge (ESD).

3. Slower Response Time – In some cases, FETs switch slower than BJTs, especially
at high frequencies.

4. Higher ON Resistance – FETs may exhibit higher ON resistance, leading to in-

creased power loss.

PBCOE, Nagpur 36 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

Que. 8 (a)
Draw and explain drain and transfer characteristics of N-channel JFET in detail
with waveforms.

Solution :
To understand electrical behavior of a JFET, it is necessary to study the interrelation of
the current and voltage in JFET. These relationships can be plotted graphically which are
commonly known as the characteristics of JFET.
The important characteristics of JFET are drain characteristics and transfer character-
istics.

Drain characteristics of N-channel JFET

Figure 33: Drain V-I characteristics of n-channel JFET

• Figure 33 shows the drain characteristics of a n-channel JFET. The curves represent
relationship between the drain current ID and drain to source voltage VDS for dif-
ferent values of VGS . Figure 34 shows the experimental setup requdired to plot this
characteristics.

• VGS and VDS both = 0 : when VGS = 0 the channel is entirely open. But VDS = 0,
so there is no attractive force for the majority carriers (electrons in n-channel JFET)
and hence drain current does not flow.

L: Dr. P.R. Bokde 37 PBCOE, Nagpur

Summer-2025 Components for Electronic Circuit Design III Sem EC

Figure 34: Experimental Setup to plot JFET characteristics

• Self pinch-off at no bias (VGS = 0) : As VGS = 0, in response to a small applied

voltage VDS , the n-type bar acts as a simple semiconductor resistor, and the current
ID increasaes linearly with VDS . As VDS increases, the voltage drop along the
channel also increases. This increase in voltage drop increases the reverse bias on
gate-source junction and causes the depletion region to penetrate into the channel,
reducing channel width. The effect of reduction in channel width provides more
opposition to increase in drain current ID . Thus rate of increase in ID with respect
to VDS is now reduced. this is shown by the curved shape in the characteristics.

• At som value of VDS , drain current ID cannot be increased further, due to reduction
in channel width. Any further increase in VDS does not increase the drain current
ID . ID approaches the constant saturation value. The voltage VDS at which the
current ID reaches to its constant saturation level is called ’Pinch-off Voltage’ Vp .

• VGS with negative bias : When an external bias of say -1 V, is applied between the
gate and the source, the gate channel junctions are further reversed biased, reducing
the effective width of the channel available for the conduction. Because of this,
drain current will reduce and pinch off voltage is reached at a lower drain current
than when VGS = 0 as shown in figure 33.

• By applying several values of negative external bias voltage VGS , a family of curves
are obtained as shown in figure 33. From figure it can be observed that for more
negative values of VGS , the pinch-off voltage is reached at lesser values of ID .

• Breakdown region : WE can observe from the figure 33 that if we increase value
of VDS beyond pinch off voltage Vp , the drain current ID remains constant, upto
certain value of VDS . IF we further exceed VDS , the voltage will be reached at
which the gate-channel junction breaks down, due to avalanche effect. At this point
the drain current increases rapidly, and the device may be destroyed.

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III Sem EC Components for Electronic Circuit Design Summer-2025

• It can be observed that the values of VDS for breakdown are reduced as the negative
gate bias is increased. this is because the total reverse breakdown voltage is the ad-
dition of the reverse voltage due to self pinch-off and the externally applied voltage
VGS .

• Ohmic and saturation regions : It is seen that the drain characteristics of JFET is
divided into two regions :ohm,ic region and saturation region. In the ohmic region,
the drain current ID varies with VDS and the JFET is said to behave as voltage
variable resistance. In the saturation region, the drain current ID remains fairly
constant and does not vary with VDS .

• Cut-off : As we know, for an n-channel JFET, the more negative VGS causes drain
current to reduce and pinch-off voltage to reach at a lower drain current. When VGS
is made sufficiently neegative, ID is reduced to 0. as shown in figure 33. This is
caused by the widening of the depletion region to a point where it completely closes
the channel. The value of VGS at the cut-off point is designated as VGS(of f ) .

Transfer characteristics of n-channel JFET

Figure 35: Transfer characteristics of n-channel JFET

• The relationship between the drain current ID and gate to source voltage VGS is
non-linear as shown in the gire 35. This relationship is defined by Schockley’s
equation.
 2
VGS
ID = IDSS 1 −
VP

• The squared term of the equation will result in a non-linear relationship between ID
and VGS , producing a cure that grows exponentially with decreasing magnitudes of

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Summer-2025 Components for Electronic Circuit Design III Sem EC

VGS . From equation we can also write,

r !
ID
VGS = VP 1−
IDSS

• In the equation values of IDSS and VP are constants, value of VGS controls ID .

• A point A at the bottom end of the curve on the VGS axis represents VGS(of f ) and
point B at the top end of the curve on the ID axis represents IDSS .

Que. 8 (b)
For JFET, if IDSS = 20 mA, VGS(of f ) = -5 volt and gmo = 4 mS. Determine the
transconductance for VGS = -4 volt. Find ID at this point.

Solution :
For JFET, the transconductance is given by-
 
VGS
gm = gmo 1 −
VGS(of f )
 
−3 −4
∴ gm = 4 × 10 1−
−5
∴ gm = 4 × 10−3 × 0.2
∴ gm = 0.8 × 10−3 A/V

The drain current in JFET is given by -

 2
VGS
ID = IDSS 1 −
VGS(of f )
 2
−3 −4
∴ ID = 20 × 10 1−
−5
∴ ID = 20 × 10−3 × 0.04
∴ ID = 0.8 × 10−3 Amp

PBCOE, Nagpur 40 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

Que. 9
Explain in brief different processes carried out in Integrated Circuit Fabrication

Solution :

Process involved in IC fabrication

The fabrication of a monolithic transistor includes the following steps:

1. Epitaxial growth

2. Oxidation

3. Photolithography

4. Diffusion

(a) i. Isolation diffusion

(b) Base diffusion
(c) Emitter diffusion

5. Ion implantation

6. Isolation Technique

7. Contact mask

8. Aluminium metallization

9. Passivation

Note : The letters P and N in the figures refer to type of doping, and a minus (-) or plus
(+) with P and N indicates lighter or heavier doping respectively

Epitaxial Growth
1. Epitaxy means growing a single crystal silicon structure upon an original silicon
substrate, so that the resulting layer is an extension of the substrate crystal structure.

2. The basic chemical reaction in the epitaxial growth process of pure silicon is the
hydrogen reduction of silicon tetrachloride.

SiCl4 + 2H2 ¸ßSi + 4HCl

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Figure 36:

3. The first step in transistor fabrication is creation of the collector region.

4. It normally requires a low resistivity path for the collector current.

5. This is due to the fact that, the collector contact is normally taken at the top, thus
increasing the collector series resistance and the VCE(Sat) of the device.

6. Thehigher collector resistance is reduced by a process called buried layer as shown

in figure 36

7. In this arrangement, a heavily doped N region is sandwiched between the N-type

epitaxial layer and P– type substrate.

8. This buried N+ layer provides a low resistance path in the active collector region to
the collector contact C.

9. In effect, the buried layer provides a low resistance shunt path for the flow of cur-
rent.

10. For fabricating an NPN transistor, we begin with a P-type silicon substrate having
a resistivity of typically 1 Ω − cm, corresponding to an acceptor ion concentration
of 1.4 × 1015 atoms/cm3 .

11. An oxide mask with the necessary pattern for buried layer diffusion is prepared.

12. This is followed by masking and etching the oxide in the buried layer mask.

13. The N-type buried layer is now diffused into the substrate.

14. A slow-diffusing material such as arsenic or antimony is used, so that the buried
layer will stay-put during subsequent diffusions.

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III Sem EC Components for Electronic Circuit Design Summer-2025

15. The junction depth is typically a few microns, with sheet resistivity of around 20 Ω
per square.

16. Then, an epitaxial layer of lightly doped N-silicon is grown on the P-type substrate
by placing the wafer in the furnace at 1200o C and introducing a gas containing
phosphorus (donor impurity).

17. The subsequent diffusions are done in this epitaxial layer.

18. All active and passive components are formed on the thin N-layer epitaxial layer
grown over the P-type substrate.

2. Oxidation
1. The process of oxidation consists of growing a thin film of silicon dioxide on the
surface of the silicon wafer at 1000o C.

Si + 2HO → SiO2 + 2H2

2. Silicon dioxide plays an important role in shielding of the surface so that dopant
atoms, by diffusion or ion implantation, may be driven into other selected regions.

3. SiO2 is an extremely hard protective coating & is unaffected by almost all reagents
except by hydrochloric acid. Thus it stands against any contamination.

Figure 37:

3. Photolithography
1. The prime use of photolithography in IC manufacturing is to selectively etch or
remove the SiO2 layer.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

2. As shown in figure, the surface of the oxide is first covered with a thin uniform
layer of photosensitive emulsion (Photo resist).

3. The mask, a black and white negative of the required pattern, is placed over the
structure.

4. When exposed to ultraviolet light, the photo resist under the transparent region of
the mask becomes polymerized.

5. The mask is then removed and the wafer is treated chemically that removes the
unexposed portions of the photo resist film.

6. The polymerized region is cured so that it becomes resistant to corrosion.

7. Then the chip is dipped in an etching solution of hydrofluoric acid which removes
the oxide layer not protected by the polymerized photoresist.

8. This creates openings in the SiO2 layer through which P-type or N-type impurities
can be diffused using the isolation diffusion process as shown in figure.

Figure 38:

9. After diffusion of impurities, the polymerized photoresist is removed with sulphuric

acid and by a mechanical abrasion process.

4. Diffusion

Isolation Diffusion
1. The integrated circuit contains many devices.

PBCOE, Nagpur 44 L: Dr. P.R. Bokde

III Sem EC Components for Electronic Circuit Design Summer-2025

2. Since a number of devices are to be fabricated on the same IC chip, it becomes

necessary to provide good isolation between various components and their inter-
connections.

3. The most important techniques for isolation are:

(a) PN junction Isolation

(b) Dielectric Isolation

4. In PN junction isolation technique, the P+ type impurities are selectively diffused

into the N-type epitaxial layer so that it touches the P-type substrate at the bottom.

5. This method generated N-type isolation regions surrounded by P type moats.

6. If the P-substrate is held at the most negative potential, the diodes will become
reverse-biased, thus providing isolation between these islands.

7. The individual components are fabricated inside these islands.

8. This method is very economical, and is the most commonly used isolation method
for general purpose integrated circuits.

9. In dielectric isolation method, a layer of solid dielectric such as silicon dioxide or

ruby surrounds each component and this dielectric provides isolation.

10. The isolation is both physical and electrical.

11. This method is very expensive due to additional processing steps needed and this
is mostly used for fabricating IC‘s required for special application in military and
aerospace.

12. The PNjunction isolation diffusion method is shown in figure. The process takes
place in a furnace using boron source.

13. The diffusion depth must be at least equal to the epitaxial thickness in order to
obtain complete isolation.

14. Poor isolation results in device failures as all transistors might get shorted together.

15. The N-type island shown in figure forms the collector region of the NPN transistor.

16. The heavily doped P-type regions marked P+ are the isolation regions for the active
and passive components that will be formed in the various N-type islands of the
epitaxial layer.

L: Dr. P.R. Bokde 45 PBCOE, Nagpur

Summer-2025 Components for Electronic Circuit Design III Sem EC

Base Diffusion

1. Formation of the base is a critical step in the construction of a bipolar transistor.

2. The base must be aligned, so that, during diffusion, it does not come into contact
with either the isolation region or the buried layer.

3. Frequently, the base diffusion step is also used in parallel to fabricate diffused re-
sistors for the circuit.

4. The value of these resistors depends on the diffusion conditions and the width of
the opening made during etching.

5. The base width influences the transistor parameters very strongly. Therefore, the
base junction depth and resistivity must be tightly controlled.

6. The base sheet resistivity should be fairly high (200- 500 per square) so that the
base does not inject carriers into the emitter.

7. For NPN transistor, the base is diffused in a furnace using a boron source.

8. The diffusion process is done in two steps, pre-deposition of dopants at 900o C and
driving them in at about 1200o C.

9. The drive-in is done in an oxidizing ambience, so that oxide is grown over the base
region for subsequent fabrication steps.

10. Figure shows that P-type base region of the transistor diffused in the N-type island
(collector region) using photolithography and isolation diffusion processes.

Emitter Diffusion

1. Emitter Diffusion is the final step in the fabrication of the transistor.

2. The emitter opening must lie wholly within the base.

3. Emitter masking not only opens windows for the emitter, but also for the contact
point, which provides a low resistivity ohmic contact path for the emitter terminal.

4. The emitter diffusion is normally a heavy N-type diffusion, producing low-resistivity

layer that can inject charge easily into the base.

5. A Phosphorus source is commonly used so that the diffusion time id shortened and
the previous layers do not diffuse further.

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6. The emitter is diffused into the base, so that the emitter junction depth very closely
approaches the base junction depth.

7. The active base is then a P-region between these two junctions which can be made
very narrow by adjusting the emitter diffusion time.

8. Various diffusion and drive in cycles can be used to fabricate the emitter. The
Resistivity of the emitter is usually not too critical.

9. The N-type emitter region of the transistor diffused into the P-type base region is
shown below.

10. However, this is not needed to fabricate a resistor where the resistivity of the P-type
base region itself will serve the purpose.

11. In this way, an NPN transistor and a resistor are fabricated simultaneously.

5. Ion Implantation

Figure 39: Ion Implantation

1. It is another technique to introduce impurities into a silicon wafer.

2. In this process silicon wafer are placed in a vacuum chamber, and are scanned by a
beam of high energy ions. (boron for p- type, phosphorus for n- type)

3. These ions are accelerated by energies between 20 kV to 259 kV.

4. These ions strike the silicon wafers, they penetrate some distance into wafer.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

5. The depth of any penetration of any particular type of ion increasing accelerating
voltage.

6. It is performed at low temperature. Therefore, previously diffused regions have a

lesser tendency for lateral spreading.

7. In diffusion process, temperature has to be controlled over a large area inside the
oven, where as in ion implantation process, accelerating potential & beam content
are dielectrically controlled from outside.

Advantages of Ion Implantation

• Doping levels can be precisely controlled since the incident ion beam can be accu-
rately measured as an electric current.

• The depth of the dopant can be easily regulated by control of the incident ion ve-
locity. It is capable of very shallow penetrations.

• Extreme purity of the dopant is guaranteed.

• The doping uniformity across the surface can be accurately controlled.

• Because the ions enter the solid as a directed beam, there is very little spread of the
beam, thus the doping area can be clearly defined.

• Since this is a low-temperature process, the movement of impurities is minimized.

6. Isolation Techniques

P-N Junction Isolation

1. Consider a p-substrate with n-type epitaxial layer grown over it.

2. To provide isolation, a p-type impurity with high concentration is diffused selec-

tively into an epitaxial layer such that it reaches to the p-substrate as shown below.

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III Sem EC Components for Electronic Circuit Design Summer-2025

Figure 40:

3. From the fig. it is clear that n-epitaxial region forms a region which is surrounded
by p-type regions. This region is called island.

4. Two regions are connected back-to-back and these two back-to back diodes serve
as isolation regions if both are reverse biased.

5. The main advantage of p-n junction isolation is that different components can be
fabricated within the isolation islands.

6. But the disadvantage is the presence of undesirable and unavoidable parasitic ca-
pacitances at the islands.

Dielectric Isolation

1. In dielectric isolation, a layer of solid dielectric such as SiO2 or ruby completely

surrounds each components thereby producing isolation, both electrical & physical.

2. This isolating dielectric layer is thick enough so that its associated capacitance is
negligible.

3. Also, it is possible to fabricate both pnp & npn transistors within the same silicon
substrate which is the main advantage of this technique.

4. But the disadvantage is the increase in cost. As the technique requires additional
steps in fabrication to deposit a dielectric layer, this technique is expensive.

7. Contact Mask
1. After the fabrication of emitter, windows are etched into the N-type regions where
contacts are to be made for collector and emitter terminals.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

2. Heavily concentrated phosphorus N+ dopant is diffused into these regions simulta-

neously.

3. Thereason for the use of heavy N+diffusion is explained as follows:

(a) Aluminium, being a good conductor used for interconnection, is a P-type of

impurity when used with silicon.
(b) Therefore, it can produce an unwanted diode or rectifying contact with the
lightly doped N- material.
(c) Introducing a high concentration of N+ dopant caused the Si lattice at the
surface semi- metallic.
(d) Thus the N+ layer makes a very good ohmic contact with the Aluminium
layer. This is done by the oxidation, photolithography and isolation diffusion
processes.

8. Metallization

Figure 41: Metallization

1. The IC chip is now complete with the active and passive devices, and the metal
leads are to be formed for making connections with the terminals of the devices.

2. Aluminium is deposited over the entire wafer by vacuum deposition. The thickness
for single layer metal is 1 µm.

3. Metallization is carried out by evaporating aluminium over the entire surface and
then selectively etching away aluminium to leave behind the desired interconnec-
tion and bonding pads as shown in figure.

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4. Metallization is done for making interconnection between the various components

fabricated in an IC and providing bonding pads around the circumference of the IC
chip for later connection of wires.

9. Passivation / Assembly and Packaging

1. Metallization is followed by passivation, in which an insulating and protective layer

is deposited over the whole device.

2. This protects it against mechanical and chemical damage during subsequent pro-
cessing steps.

3. Doped or un doped silicon oxide or silicon nitride, or some combination of them,

are usually chosen for passivation of layers.

4. The layer is deposited by chemical vapour deposition (CVD) technique at a tem-

perature low enough not to harm the metallization.

Que. 10 (a)
Write short notes on (any two) :

1. Photolithography

2. Twin-tub CMOS process

3. Design of resistors

Solution :

1. Photolithography
1. The prime use of photolithography in IC manufacturing is to selectively etch or
remove the SiO2 layer.

2. As shown in figure, the surface of the oxide is first covered with a thin uniform
layer of photosensitive emulsion (Photo resist).

3. The mask, a black and white negative of the required pattern, is placed over the
structure.

4. When exposed to ultraviolet light, the photo resist under the transparent region of
the mask becomes polymerized.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

Figure 42:

5. The mask is then removed and the wafer is treated chemically that removes the
unexposed portions of the photo resist film.

6. The polymerized region is cured so that it becomes resistant to corrosion.

7. Then the chip is dipped in an etching solution of hydrofluoric acid which removes
the oxide layer not protected by the polymerized photoresist.

8. This creates openings in the SiO2 layer through which P-type or N-type impurities
can be diffused using the isolation diffusion process as shown in figure.

9. After diffusion of impurities, the polymerized photoresist is removed with sulphuric

acid and by a mechanical abrasion process.

2. Twin Tub Process

In Duel-well process both p-well and n-well for NMOS and PMOS transistors respec-
tively are formed on the same substrate. The main advantage of this process is that the
threshold voltage, body effect parameter and the transconductance can be optimized sepa-
rately. The starting material for this process is p+ substrate with epitaxially grown p-layer
which is also called as epilayer. The process steps of twin-tub process are shown in Figure
below.

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III Sem EC Components for Electronic Circuit Design Summer-2025

Figure 43:

The process starts with a p-substrate surfaced with a lightly doped p-epitaxial layer.

1. A thin layer of SiO2 is deposited which will serve as the pad oxide.

2. A thicker sacrificial silicon nitride layer is deposited by chemical vapour deposition.

3. A plasma etching process is used to create trenches used for insulating the devices.

4. The trenches are filled with SiO2 which is called as the field oxide.

5. To provide flat surface chemical mechanical planarization is performed and also

sacrificial nitride and pad oxide is removed.

6. The p-well mask is used to expose only the p-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by second
implant step to adjust the threshold NMOS transistor.

7. The n-well mask is used to expose only the n-well areas, after this implant and
annealing sequence is applied to adjust the well doping. This is followed by a
second implant step to adjust the threshold voltage of PMOS transistor.

8. A thin layer of gate oxide and polysilicon is chemically deposited and patterned
with the help of polysilicon mask.

9. Ion implantation to dope the source and drain regions of the PMOS (p +) and NMOS
(n+) transistors is used this will also form n+ polysilicon gate and p+ polysilicon
gate for NMOS and PMOS transistors respectively.

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Summer-2025 Components for Electronic Circuit Design III Sem EC

10. Then the oxide or nitride spacers are formed by chemical vapour deposition (CVD).

11. In this step contact or holes are etched, metal is deposited and patterned. After the
deposition of last metal layer final passivation or overglass is deposited for protec-
tion.

Figure 44:

Figure 45:

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3. Design of Resistors
The design of resistors plays a crucial role in their fabrication process, ensuring desired
electrical characteristics, reliability, and integration into electronic circuits. Key factors
in resistor design include:

1. Material Selection: The resistive element is typically made from materials like
nichrome, carbon, or metal films. The choice depends on required resistance toler-
ance, temperature stability, and application.

2. Geometry and Size: The resistance value is determined by the material’s resis-
tivity, length, and cross-sectional area. Designers manipulate these parameters to
achieve precise resistance values.

3. Power Rating and Heat Dissipation: Resistors must be designed to handle ex-
pected power without overheating. Proper surface area and materials with good
thermal conductivity are essential.

4. Substrate and Packaging: The resistor is fabricated on substrates like ceramic

or silicon. Packaging protects the resistor and influences thermal and electrical
performance.

5. Tolerance and Stability: Tight tolerance resistors require precise fabrication tech-
niques like laser trimming. Stability over time and temperature is achieved through
material selection and protective coatings.

6. Integration: In integrated circuits, resistors are fabricated using thin or thick film
technologies, ensuring compatibility with semiconductor processes.

Que. 10 (b)
Describe in detail various stages involved in the fabrication of resistor.

Solution :
The fabrication of resistors involves several stages, including wafer preparation, oxida-
tion, diffusion, photolithography, etching, metallization, and possibly ion implantation,
depending on the type of resistor and the desired characteristics.

1. Wafer Preparation:

(a) Starting Material:

The fabrication begins with a silicon wafer, which is the foundation for the
resistor and other components.

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(b) Cleaning and Polishing:

The wafer undergoes rigorous cleaning and polishing to ensure a smooth and
defect-free surface.

2. Oxidation:

Figure 46:

Here’s a more detailed breakdown of the process:

(a) Creating Insulating Layers:

A thin layer of silicon dioxide (SiO2) is grown on the wafer surface through
oxidation, which serves as an insulating layer.
(b) Controlling Thickness:
The thickness of the oxide layer is precisely controlled, as it plays a crucial
role in the performance of the resistor.

3. Diffusion and Ion Implantation (for doped resistors):

(a) Introducing Impurities:

Impurities (e.g., phosphorus for n-type doping, boron for p-type doping) are
introduced into the silicon wafer to create regions with specific electrical prop-
erties.
(b) Diffusion:
Impurities can be introduced through diffusion, where atoms are allowed to
move into the silicon lattice at high temperatures.
(c) Ion Implantation:
Alternatively, impurities can be implanted into the silicon lattice using high-
energy ions, providing precise control over the doping profile.

4. Photolithography and Etching:

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(a) Patterning:
Photolithography is used to create patterns on the wafer’s surface, defining the
areas where the resistor and other components will be formed.
(b) Photoresist Coating:
A photosensitive material (photoresist) is applied to the wafer, and then ex-
posed to ultraviolet (UV) light through a mask.
(c) Etching:
The exposed areas of the photoresist are removed, and then the underlying
material (e.g., silicon dioxide, silicon, or metal) is etched away, creating the
desired patterns.

5. Metallization:

(a) Connecting Resistors:

Metal layers are deposited on the wafer surface to create electrical connections
to the resistor and other components.
(b) Thin Film Deposition:
Thin films of metals (e.g., aluminum, copper) are deposited using techniques
like sputtering or chemical vapor deposition.
(c) Patterning and Etching (again):
Photolithography and etching are used to pattern the metal layers, creating the
desired interconnects and contact pads.

6. Thin Film Resistor Fabrication:

(a) Metal Film Deposition: Thin-film resistors are fabricated by depositing a

thin layer of a resistive material (e.g., tantalum nitride, titanium-tungsten) on
an insulating substrate.
(b) Patterning:
The metal film is patterned using photolithography and etching to create the
desired resistor geometry.
Advantages: Thin-film resistors offer high precision, stability, and tolerance,
making them suitable for applications requiring high accuracy.

7. Thick Film Resistor Fabrication:

• Conductive Paste: Thick-film resistors are fabricated by screen-printing or

painting a conductive paste (containing metal powders or metal oxides) onto
a ceramic substrate.

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• Firing: The paste is then fired at high temperatures to form a conductive layer.
• Trimming: The resistance value can be adjusted by laser trimming or other
techniques.

8. Packaging:

(a) Final Assembly: The fabricated resistors, along with other components, are
packaged to form a functional circuit.
(b) Mounting: The components are mounted on a substrate or header using sol-
der, adhesive, or chip bonding techniques.
(c) Electrical Connections: Electrical connections are made using wire bonding
or other techniques.

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