Scribd
Upload
84 views20 pages

ENGIN 112 Intro To Electrical and Computer Engineering: Binary Adders and Subtractors

This document discusses binary addition and subtraction. It describes how a single-bit full adder can be created using XOR gates and chained together to perform multi-bit addition and subtraction. The same adder circuit can perform both operations by using two's complement representation for subtraction. Overflow is an important issue that is detected when adding two numbers of the same sign produces a result with the opposite sign.

Uploaded by

Richie Latchman
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
84 views20 pages

ENGIN 112 Intro To Electrical and Computer Engineering: Binary Adders and Subtractors

This document discusses binary addition and subtraction. It describes how a single-bit full adder can be created using XOR gates and chained together to perform multi-bit addition and subtraction. The same adder circuit can perform both operations by using two's complement representation for subtraction. Overflow is an important issue that is detected when adding two numbers of the same sign produces a result with the opposite sign.

Uploaded by

Richie Latchman
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 20

ENGIN 112 Intro to Electrical and Computer Engineering

Lecture 14

Binary Adders and Subtractors

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Overview Addition and subtraction of binary data is fundamental


Need to determine hardware implementation

Represent inputs and outputs


Inputs: single bit values, carry in Outputs: Sum, Carry

Hardware features
Create a single-bit adder and chain together

Same hardware can be used for addition and subtraction with minor changes Dealing with overflow
What happens if numbers are too big?

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Half Adder Add two binary numbers


A0 , B0 -> single bit inputs S0 -> single bit sum C1 -> carry out

A0 B0 S0 C 1

0 0 1 1

0 1 0 1

0 1 1 0

0 0 0 1

A0 B0

S0

C1

Dec Binary

1 +1 2
ENGIN112 L14: Binary Adder Subtractor

1 +1 10
October 3, 2003

Multiple-bit Addition Consider single-bit adder for each bit position. A3 A2 A1 A0 B3 B2 B1 B0

A 0 1 0 1

B 0 1 1 1

A B

1 0 0 1

1 1 1 1

1 0 1 1 1 0 0

Ci+1

Ci Ai +Bi Si

Each bit position creates a sum and carry


October 3, 2003

ENGIN112 L14: Binary Adder Subtractor

Full Adder Full adder includes carry in Ci Notice interesting pattern in Karnaugh map. Ci Ai Bi Si Ci+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 AiBi 00 Ci 0 1 1

01 1

11

10 1

Si

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Full Adder Full adder includes carry in Ci Alternative to XOR implementation Ci Ai Bi Si Ci+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 Si = # # # !Ci & !Ai & Bi !Ci & Ai & !Bi Ci & !Ai & !Bi Ci & Ai & Bi

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Full Adder Reduce and/or representations into XORs Si = # # # !Ci & !Ai & Bi !Ci & Ai & !Bi Ci & !Ai & !Bi Ci & Ai & Bi

Si = !Ci & (!Ai & Bi # Ai & !Bi) # Ci & (!Ai & !Bi # Ai & Bi) Si = !Ci & (Ai $ Bi) # Ci & !(Ai $ Bi) Si = Ci $ (Ai $ Bi)
ENGIN112 L14: Binary Adder Subtractor October 3, 2003

Full Adder Now consider implementation of carry out Two outputs per full adder bit (Ci+1, Si) Ci Ai Bi Si Ci+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 AiBi 00 Ci 0 1 1

01

11 1 1

10

Ci+1
Note: 3 inputs
October 3, 2003

ENGIN112 L14: Binary Adder Subtractor

Full Adder Now consider implementation of carry out Minimize circuit for carry out - Ci+1 Ci Ai Bi Si Ci+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 AiBi 00 Ci 0 1 1 01 11 1 1 1 10

Ci+1
Ci+1 = Ai & Bi # Ci & Bi # Ci & Ai
October 3, 2003

ENGIN112 L14: Binary Adder Subtractor

Full Adder

Ci+1 = Ai & Bi # Ci !Ai & Bi # Ci & Ai & !Bi Ci+1 = Ai & Bi # Ci & (!Ai & Bi # Ai & !Bi) Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

Recall:
Si = Ci $ (Ai $ Bi) Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
ENGIN112 L14: Binary Adder Subtractor October 3, 2003

Full Adder Full adder made of several half adders Si = Ci $ (Ai $ Bi) Ci+1 = Ai & Bi # Ci & (Ai $ Bi)
Ci Ai Bi
Si

C i+1

Half-adder
ENGIN112 L14: Binary Adder Subtractor

Half-adder
October 3, 2003

Full Adder Hardware repetition simplifies hardware design

Ci Ai Bi S half-adder C half-adder C

Si C i+1

A full adder can be made from two half adders (plus an OR gate).

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Full Adder Putting it all together


Single-bit full adder Common piece of computer hardware

Ai

Bi

C i+1

Full Adder

Ci

Si

Block Diagram
ENGIN112 L14: Binary Adder Subtractor October 3, 2003

4-Bit Adder Chain single-bit adders together. What does this do to delay?
A3 B3 A2 B2 A1 B1 A0 B0

Full Adder C3

Full Adder C2

Full Adder C1

Full Adder

C4

S3

S2

S1

S0

C A B S
ENGIN112 L14: Binary Adder Subtractor

1 0 0 1

1 1 1 1

1 0 1 0

0 1 1 0
October 3, 2003

Negative Numbers 2s Complement. Subtracting a number is the same as:


1. Perform 2s complement 2. Perform addition

If we can augment adder with 2s complement hardware?

110 = 0116 = 00000001 -110 = FF16 = 11111111 12810 = 8016 = 10000000 -12810 = 8016 = 10000000

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

4-bit Subtractor: E = 1

A3

B3

A2

B2

A1

B1

A0

B0 E

Full Adder C3

Full Adder C2

Full Adder C1

Full Adder

+1
SD0

C4

SD3

SD2

SD1

Add A to B (ones complement) plus 1 That is, add A to twos complement of B D=A-B
ENGIN112 L14: Binary Adder Subtractor October 3, 2003

Adder- Subtractor Circuit

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

Overflow in twos complement addition Definition: When two values of the same signs are added:
Result wont fit in the number of bits provided Result has the opposite sign.

AN-1 BN-1 CN-1

Overflow?

Assumes an N-bit adder, with bit N-1 the MSB


ENGIN112 L14: Binary Adder Subtractor October 3, 2003

Addition cases and overflow

00 01 0010 0011 0011 0110 -------- -------0101 1001 2 3 5 3 6 -7 OFL

11 10 00 1110 1101 0010 1101 1010 1100 -------- -------- -------1011 0111 1110 -2 -3 -5 -3 -6 7 OFL
October 3, 2003

11 1110 0100 -------0010 -2 4 2

2 -4 -2

ENGIN112 L14: Binary Adder Subtractor

Summary

Addition and subtraction are fundamental to computer systems Key create a single bit adder/subtractor
Chain the single-bit hardware together to create bigger designs

The approach is call ripple-carry addition


Can be slow for large designs

Overflow is an important issue for computers


Processors often have hardware to detect overflow

Next time: encoders/decoder.

ENGIN112 L14: Binary Adder Subtractor

October 3, 2003

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy