Chapter 8 CPU

Organization
G.Rajendra
Assistant Professor,
MCA Department, LBRCE

Central Processing Unit

The part of the computer performs the bulk

of data processing operations is called the
central processing unit

The CPU is made up of three major parts:

Register set
ALU
Control units

CPU
The central processing unit (CPU) of a
computer is the main unit that dictates
the rest of the computer organization

1. Register set: Stores intermediate

data during the execution of
instructions;
2. Arithmetic logic unit (ALU):
Performs the required micro-operations
for executing the instructions;
3. Control unit: supervises the transfer
of information among the registers and
instructs the ALU as to which operation
to perform by generating control signals.

Control
Unit
Arithmetic
Logic Unit
Registers

Control
Unit
Arithmetic
Logic Unit
Registers

Main
Memory

Central Processing Unit = brain

Executes programs by:
Fetching and decoding the next
instruction from memory
Execute it
Consists of:
Control Unit
Arithmetic Logic Unit (ALU)
Registers (high-speed memory)
Program Counter (PC)
Instruction Register (IR)
I/O Devices
Disk

Bus

Printer

8-2. General Register

Organization

CPU must have some working space (fast

access and close to CPU)

This space is efficiently used to store

intermediate values

The most convenient way to communicate

registers is trough common bus system

Register Transfer
Language
Register: A register consists of a group of flip flops with
a clock input. Registers are commonly used to store and
shift binary data.
Register Transfer Language:
The symbolic notation used to describe the micro
operation transfers among registers is called a register
transfer language.
The operations executed on data stored in registers are
called microoperations.

A Micro operation is an elementary operation performed

on the information stored in one or more registers.

Register Transfer
Language
The internal hardware organization of a digital
computer is best defined by specifying
1. The set of registers it contains and their function
2. The sequence of micro operations performed on
the binary information stored in the registers.
3. The control that initiates the sequence of micro
operations.
Register Transfer:
Computer registers are designated by capital
letters
( sometimes followed by numerals) to
denote the function of the register.

Register Transfer
Language

For example: The register that holds an address for the

memory unit is called memory address register and is
designated by the name MAR.
Other designations for registers are
PC (for Program Counter)
IR ( for Instruction Register)
R1 ( for processor register)
The individual flip-flops in an n-bit register are
numbered in sequence from 0 to n-1, starting from 0 in
the right most position and increasing the numbers
towards the left

Register Transfer
Language

Block Diagram of Register:

R1

(a) Register R
individual bits

15

R2
( C) Numbering of
bits

(b). Showing
0

PC(H)

PC(L)

(d) Divided into two

parts

Register Transfer
Language

The most common way to represent a register is by a

rectangular box with the name of the register inside.
The symbol PC(0-7) or PC(L) or Lower Order Byte,
PC(8-15) or PC(H) or Higher Order Byte
The information transfer from one register to another is
designated by symbolic form by means of replacement
operator. The statement R2 R1
The statement denotes a transfer of the contents of
register R1 into register R2. It designates a replacement
of the content of R2 by the content of R1.
By definition, the content of the source register R1 does
not change after the transfer.

Register Transfer
Language
Often we want the transfer to occur only under a
predetermined control condition,
IF(P=1) then (R2 R1) where p is a
control signal generated in the control section.
The control function is a Boolean variable that is
equal to 1 or 0.
The control function is included in the statement as
follows:
P: R2 R1, control function is terminated by colon.
Which means if p =1, then load the contents of
register R1 into register R2.

Register Transfer
Language

Hardware Implementation of controlled transfer

Fig: Transfer from R1 to R2 when p=1
Control Unit

Load

R2

clock

R1

Register Transfer
Language

Fig: Basic symbols of the register transfer

Symbol

Description

examples

Letters
( and Numerals)

Denotes a Register

MAR, R2

Parenthesis

Denotes a part of a
register

R2(0-7), R2(L)
R2(8-15), R2(H)

Arrow

Denotes the
transfer of
information

R2 R1

Comma

Separates two
micro operations

R2R1, R1R2

Computer Registers

Computer instructions are normally stored in

consecutive memory locations and are
executed sequentially one at a time.
The control reads an instruction from specific
address in memory and executes it. It then
continues by reading the next instruction in
sequence and executes it, and so on.
The computer needs a processor register for
manipulating data and a register for holding a
memory address

Computer Registers

Fig: Basic computer registers and memory

0
11
PC
11

0
AR

15

0
IR

15

Memory
4096 words
16 bits per word

0 15
TR

0
OUTR

DR

0 15
INTR

AC

Computer Registers

The memory unit has a capacity of 4096 words

and each word contains 16 bits.
Data Register(DR) : hold the operand(Data)
read from memory
Accumulator Register(AC) : general purpose
processing register
Instruction Register(IR) : hold the instruction
read from memory
Temporary Register(TR) : hold a temporary
data during processing
Address Register(AR) : hold a memory
address, 12 bit width

Computer Registers

Program Counter(PC) :

hold the address of the next instruction to be read from

memory after the current instruction is executed
Instruction words are read and executed in sequence
unless a branch instruction is encountered
A branch instruction calls for a transfer to a
nonconsecutive instruction in the program
The address part of a branch instruction is transferred
to PC to become the address of the next instruction
To read instruction, memory read cycle is initiated, and
PC is incremented by one(next instruction fetch)

Computer Registers

Input Register(INPR) : receive an 8-bit

character from an input device
Output Register(OUTR) : hold an 8-bit character
for an output device

Computer Registers

List of registers for the basic computer

Register
symbol
DR
AR
AC
IR
PC
TR
INPR
OUTR

Number
Register
of bits
name
16
Data register
12
Address register
16
Accumulator
16
Instruction register
12
Program counter
16
Temporary register
8
Input register
8
Output register

Register
Function----------------------Holds memory operands
Holds address for memory
Processor register
Holds instruction code
Holds address of instruction
Holds temporary data
Holds input character
Holds output character

Bus and Memory Transfer

A typical digital computer has many registers,

and paths must be provided to transfer
information from one register to another.
The number of lines will be excessive if separate
lines are used between each register and all
registers in the system.
A more efficient scheme for transferring
information between registers in a multiple
register is a common bus system.
A bus structure consists of a set of common lines
one for each bit of a register, through which
binary information is transferred one at a time.

Bus and Memory Transfer

Control signals are determine which register is

selected by the bus during each particular
register transfer.
One way of constructing a common bus system
is with multiplexers
The construction of a bus system for four
registers is shown in figure.

Bus and Memory Transfer

S1
S0

4 *1
M UX 3

4 *1
M UX 2

4 *1
M U X 1

4 *1
M UX 0

Register D

Register C

Register B

Register A

Bus and Memory Transfer

S1
0
0
1
1

S0
0
1
0
1

Register selected
A
B
C
D

Memory Transfer

The transfer of information from a memory word to

the outside environment is called a read operation
The transfer of new information to be stored into
the memory is called a write operation.
A memory word will be symbolized by letter M.
Memory Read and Write
AR: address register
DR: data register
Read: DR M[AR]
Write: M[AR] R1

Common Bus System

The basic computer has eight registers, a

memory unit, and a control unit. Paths must be
provided to transfer information from one
register to another and between memory and
registers. The number of wires will be excessive
if connections are made between the outputs of
each register and the inputs of other registers.
A more efficient scheme for transferring
information in a system with many registers is
to use a common bus. The connection of the
registers and memory of the basic computer to

Common Bus System

Fig: Basic computer registers connected to a common bus

Common Bus System

The outputs of seven registers and memory are

connected to the common bus. The specific
output that is selected for the bus lines at any
given time is determined from the binary value
of the selection variables S2, S1, and S0.
The number along each output shows the
decimal equivalent of the required binary
selection. For example, the number along the
output of DR is 3. The 16-bit outputs of DR are
placed on the bus lines when S2S1S0=011
since this is the binary value of decimal 3.

Common Bus System

The lines from the common bus are connected

to the inputs of each register and the data
inputs of the memory.
The memory receives the contents of the bus
when its write input is activated. The memory
places its 16-bit output onto the bus when the
read input is activated and S2S1S0=111.
Four registers DR, AC, IR, and TR, have 16 bits
each.
Two registers, AR and PC have 12 bits each
since they hold a memory address.

Common Bus System

The input registers INPR and the output register

OUTR have 8 bits each and communicate with the
eight least significant bits in the bus.
INPR is connected to provide information to the bus
but OUTR can only receive information from the bus.
The input data and output data of the memory are
connected to the common bus, but the memory
address is connected to AR. Therefore, AR must
always be used to specify a memory address.
The 16 inputs of AC come from an Adder and logic
circuit.

Common Bus System

This circuit has 3 sets of inputs. One set of 16 bit inputs

come from the outputs of the AC. They are used to
implement register micro operations such as
complement AC and shift AC.
Another set of 16-bit inputs come from the data register
DR. The inputs from DR and AC are used for arithmetic
and logic micro operations, such as add DR to AC or
AND DR to AC. The result of an addition is transferred to
AC and the end carry-out of the addition is transferred
to the flip flop E (extended AC bit).
A third set of 8-bit inputs come from the input register
INPR.

Computer Instructions

Basic Computer Instruction Format

Memory-Reference Instructions
12 11

15 14

Opcode

0
Address

Register-Reference Instructions
15
0

12 11
Register operation
1

Input-Output Instructions
15
1 1

(OP-code = 000 ~ 110)

12 11
1

(OP-code = 111, I = 0)
0

(OP-code =111, I = 1)
0

I/O operation

Computer Instructions

Each format has 16 bits. The operation code

(opcode) part of the instruction contains three
bits and the remaining 13 bits depends on the
operation code encountered.
A memory-reference instruction uses 12 bits to
specify an address and one bit to specify the
addressing mode I. I is equal to 0 for direct
address and to 1 for indirect address.
The register-reference instructions are
recognized by the operation code 111 with a 0
in the leftmost bit (bit 15) of the instruction.

Computer Instructions

A register reference instruction specifies an

operation on or a test of the AC register. An
operand from memory is not needed; therefore,
the other 12 bits are used to specify the
operation or test to be executed.
Similarly, an input-output instruction does not
need a reference to memory and is recognized
by the operation code 111 with a 1 in the left
most bit of the instruction. The remaining 12
bits are used to specify the type of input-output
operation or test performed.

Computer Instructions

The type of instruction is recognized by the

computer control from the four bits in positions 12
through 15 of the instruction. If the three opcode
bits in positions 12 though 14 are not equal to 111,
the instruction is a memory-reference type and the
bit in position 15 is taken as the addressing mode
I. if the 3 bit opcode is equal to 111, control then
inspects the bit in position 15. if this bit is 0, the
instruction is register-reference type. If the bit is 1,
the instruction is an input-output type.It may
seem that the computer is restricted to a
maximum of eight distinct operations.

Computer Instructions

The total number of instructions chosen for the

basic computer is equal to 25
The instructions for the computer are listed in
table. The symbol designation is a three letter
word and represents an abbreviation intended
for programmers and users.
The hexadecimal code is equal to the
equivalent hexadecimal number of the binary
code used for the instruction.

BASIC COMPUTER INSTRUCTIONS

Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ

Hex
I=0
0xxx
1xxx
2xxx
3xxx
4xxx
5xxx
6xxx

Code
I=1
8xxx
9xxx
Axxx
Bxxx
Cxxx
Dxxx
Exxx

Description
AND memory word to AC
Add memory word to AC
Load AC from memory
Store content of AC into memory
Branch unconditionally
Branch and save return address
Increment and skip if zero

CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT

7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001

Clear AC
Clear E
Complement AC
Complement E
Circulate right AC and E
Circulate left AC and E
Increment AC
Skip next instr. if AC is positive
Skip next instr. if AC is negative
Skip next instr. if AC is zero
Skip next instr. if E is zero
Halt computer

INP
OUT
SKI
SKO
ION
IOF

F800
F400
F200
F100
F080
F040

Input character to AC
Output character from AC
Skip on input flag
Skip on output flag
Interrupt on
Interrupt of

Instruction set
completeness

1.
2.

3.

4.

The of instructions are said to be complete if

the computer includes a sufficient number of
instructions in each of the following categories
Arithmetic, Logical and shift instructions
Instructions for moving information to and from
memory and processor registers
Program control instructions together with
instructions that check status conditions
Input and output instructions

Arithmetic Micro
operations
A micro operation is an elementary operation
performed with the data stored in registers.
Classified into four categories
1. Register transfer micro operations transfer
binary information from one register to another.
2. Arithmetic micro operations perform arithmetic
operations on numeric data stored in registers.
3. Logic micro operations perform bit manipulation
operations on non-numeric data stored in
registers
4. Shift micro operations perform shift operations
on data stored in registers.

Arithmetic Micro
operations

The arithmetic micro operation is defined by the

statement R3 R1+R2 specifies an add micro
operation .
It states that the contents of register R1 are added
to the contents of register R2 and the sum
transferred to the register R3.
subtraction is most often implemented through
complementation and addition.
Instead of using the minus operator, we can specify
the subtraction by the following statement.
R3 R1+ R2+ 1

Arithmetic Micro
operations

R2 is the symbol for the 1s complement of R2.

Adding 1 to the 1s complement produces the
2s complement. Adding the contents of R1 to
the 2s complement of R2 is equivalent to R1R2.
The increment and decrement micro operations
are symbolized by plus-one and minus-one
operations respectively.

Arithmetic Micro
operations
Symbolic
Designation

Description

R3 R1 + R2

Contents of R1 plus R2 transferred to R3

R3 R1 R2

Contents of R1 minus R2 transferred to R3

R2 R2

R2 R2 + 1

Complement the contents of R2 (1s

complement)
2s Complement the contents of R2 (negate)

R3 R1 + R2 + R1 plus the 2s complement of R2 (subtract)

1
R1 R1 + 1

R1 R1 1

Increment the contents of R1 by one

Decrement the contents of R1 by one

Stack organization

A useful feature that is included in the CPU of most

computers is a stack or Last-In, First-Out(LIFO) list.
A storage device that stores information in such a
manner that the item stored last is the first item
retrieved.
Stack in digital computer is essentially a memory
unit with an address register(SP) that can count
only after an initial value is loaded into the stack.
The register that holds the address for the stack is
called a Stack Pointer(SP), because its value always
points at the top in the stack.

Stack organization

The two operations of a stack are the insertion

and deletion of items. The operation of insertion
is called PUSH (or push-down) because it can be
thought as the result of pushing a new item on
top.
The operation of deletion is called POP(or popup) because it can be thought of as the result of
removing one item so that the stack pops up.
These operations are simulated by
incrementing or decrementing the stack pointer
register.

Stack organization
Register Stack: A stack can be organized
as a collection of a finite number words or
registers.
Fig: Block diagram of a 64-word stack

Stack Organization
Note: FULL 1 ,when the stack is full, FULL 0 , when the stack is not
full
EMTY 1, when the stack is empty of items
EMTY 0, when the stack is not empty

The Stack pointer register SP contains a binary number

whose value is equal to the address of the word that is
currently on top of the stack.
Three items are placed in the stack: A, B and C, in that
order. Item C is on top of the stack so that the content of
SP is now 3.
To remove the top item, the stack is popped by reading the
memory word at address 3 and decrementing the content
of SP. Item B is now on the top of stack, since SP holds the
address 2.

Stack Organization

To insert a new item, the stack is pushed by

incrementing SP and writing a word in the nexthigher location in the stack.
Note: Item C has been readout but not physically
removed. This does not matter because when the
stack is pushed, a new item is written in its place.
In a 64-word stack, stack pointer contains 6 bit because 2^6
= 64. since SP has only six bits, it cannot exceed a number
grater than 63(111111 in binary). When 63 is incremented
by 1, the result is 0 since 111 111 + 1= 1000000 in binary
but SP can accommodate only the six least significant bits.
Similarly, when 000 000 is decremented by 1, the result is
111111.

Stack Organization

The 1-bit register FULL is set to 1 when the

stack is full, and the 1-bit register EMTY is set to
1 when the stack is empty of items.
DR is the data register that holds the binary
data to be written into or read out of the stack.
Initially, SP is cleared to 0, EMTY is set to 1, and
FULL is cleared to 0, so that SP points to the
word at address 0 and the stack is marked
empty and not full.
If the stack is not full (if FULL= 0), a new item is
inserted with a push operation.

Stack Organization

The PUSH operation is implemented with the

following sequence of micro operations.
SP SP+1
M[SP] DR
the stack
If (SP=0) then (FULL1)
EMTY 0

Increment stack pointer

Write item on top of
Check if stack is full
Mark the stack not empty.

The stack pointer is incremented so that it points

to the address of the next-higher word.
A memory write operation inserts the words from
DR into the top of the stack.

Stack Organization

The first item stored in the stack is at address

1. The last item is stored at address 0.
If SP reaches 0, the stack is full of items, so
FULL is set to 1. This condition is reached if the
top item prior to the last push was in location
63 and after incrementing SP, the last item is
stored in location 0.
Once the item is stored at location 0, there are
no more empty registers in the stack. If an item
is written in the stack, obviously the stack
cannot be empty, so EMTY is cleared to 0.

Stack Organization

A new item is deleted from the stack if the stack is

not empty(if EMTY=0) . The POP operation consists
of the following sequence of micro operations.
DR M[SP] Read item from the top of stack
SP SP -1
Decrement stack pointer
If (SP=0 ) then
Check is stack is empty
(EMTY1)
FULL 0
Mark the stack not full.

The top Item is read from the stack into DR. The
stack pointer is then decremented. If its value
reaches 0, the stack is empty, so EMTY is set to 1.

Stack Organization

This condition is reached if the item read was in

location 1. once this item is readout, SP is
decremented and reaches the value 0, which is the
initial value of SP.
Note: A POP operation reads the item from location
0 and then SP is decremented. SP changes to 111111,
which is equivalent to decimal 63.
in this configuration, the word in address 0 receives
the last item in the stack.
Stack is PUSHED when FULL = 0 or
POPED when EMTY = 0

Stack Organization

Reverse Polish Notation

A stack organization is very effective for
evaluating arithmetic expressions. The common
arithmetic expressions are written in infix
notation with each operator written between
the operands
Example: A * B + C * D
The star (denoting multiplication) is placed
between two operands A and B or C and D. the
plus is between the two products.

Stack Organization
prefix notation, places the operator before the
operands.
The postfix notation, referred to as Reverse
Polish Notation(RPN) places the operators after
the operands.
Example: A + B infix notation
+ AB
Postfix notation
AB + Postfix or Reverse Polish Notation
The Reverse Polish Notation is a form suitable for
stack manipulation.

Stack Organization
The expression A * B + C * D is written as AB *CD*
Evaluated as follows
1. Scan the expression from left to right.
2. When an operator is reached, perform the operation
with the two operands found on the left side of the
operator.
3. Replace the two operands and the operator by the
result obtained from the operation.
n Example:
infix 3*4+5*6=42
postfix 34*56*+
1256*+
1230+
42

Stack Organization
Reverse Polish notation evaluation with a stack.
Stack is the most efficient way for evaluating
arithmetic expressions.
(Example) using stacks to do this.
3 * 4 + 5 * 6 = 42
=> 3 4 * 5 6 * +

Instruction Codes

A process is controlled by a program

A program is a set of instructions that specify
the operations, data, and the control sequence
An instruction is stored in binary code that
specifies a sequence of microoperations
Instruction codes together with data are stored in
memory (Stored Program Concept)
A computer instruction is a binary code that
specifies a sequence of microoperations for the
computer.
Instruction codes together with data are stored in
memory.

Instruction Codes

Instruction code is a group of bits that instruct the

computer t perform a specific operation. It is usually
divided into parts, each having its own particular
interpretation(Explanation or Understanding).
The most basic part of an instruction code is its
operation part. The operation code of an instruction is a
group of bits that define such operations as add,
subtract, multiply, shift and complement.

The operation part of an instruction code

specifies the operation to be performed. This
operation must be performed on some data
stored in processor registers or in memory.

Instruction Codes
An instruction code must therefore specify not
only the operation but also the registers or the
memory words where the operands are to be
found, as well as registers or memory words
where the results is to be stored.
Stored program Organization
The simplest way to organize a computer is to
have one processor register and instruction
code format with two parts. The first part
specifies the operation to be performed and the
second part specifies an address.

Instruction Codes

The memory address tells the control where to find an

operand in memory. This operand is read from memory and
used as the data to be operated on together with the data
stored in the processor register.
For a memory unit with 4096 words we need 12 bits to
specify an address since 2^12=4096. If we store each
instruction code in one 16-bit memory word, we have
available four bits for the operation code to specify one out
of 16 possible operations, and 12 bits to specify the address
of an operand.
The control reads a 16-bit instruction from the program
portion of the memory. It uses the 12-bit address part of the
instruction to read an operand from the data portion of
memory. It then executes the operation specified by the
operation code.

Instruction Codes
Computer instruction

Field specifying the

operation to be executed

Field specifying the data

To be operated on

Instruction Codes

Fig: Stored program Organization.

15

12 11

Opcode

Address

Instruction Format
1
5

Binary Operand

Instruction Codes
Fig: Stored Program Organization
Memory
4096 * 16
Instructions
(Program)

Operands
(data)

Processor Register
(accumulator or AC )

Instruction Codes

Computers that have a single-processor register

usually assign to it the name accumulator and
label it AC. The operation is performed with the
memory operand and the content of AC.
If an operation in an instruction code does not
need an operand from memory, the rest of the bits
in the instruction can be used for other purposes.
For example, operations such as clear AC,
complement AC, and increment AC operate on
data stored in the AC register. They do not need an
operand from memory.

Instruction Codes

Instruction code format

Instruction code format with two parts :
Op. Code + Address
Op. Code : specify 16 possible operations(4 bits)
Address : specify the address of an operand(12 bits)
If an operation in an instruction code does not need
an operand from memory, the rest of the bits in the
instruction (address field) can be used for other
12 purpose
11
0
15
12 11
0

15

Op. Code

Address

instruction

data

Not an instruction

Instruction codes

Direct and Indirect Address

It is sometimes convenient to use the address bits
of an instruction code not as an address but as
the actual operand. When the second part of an
instruction code specifies an operand, the
instruction is said to have an immediate operand.
when the second part specifies the address of an
operand, the instruction is said to have a direct address.
This is contrast to a third possibility called indirect
address, where the bits in the second part of the
instruction designate an address of a memory word in
which the address of the operand is found.

Instruction Code

It consists of a 3-bit operation code, 12-bit

address, and an indirect address mode bit
designated by I.
The mode bit is 0 for direct address and 1 for
indirect address.
The memory word that holds the address of the
operand in an indirect address instruction is
0
used
15 as
14 a pointer
12to
11 an array of data.
I

Op code

Address

Fig: Instruction Format

Instruction Code
Fig: Demonstration of direct and indirect

address
Indirect addressing

Direct addressing
22

457

ADD

35

300
457

ADD

300

1350

Operand
1350

+
AC

Operand

+
AC

Instruction Cycle

1.
2.
3.
4.

The program is executed in the computer by going

through a cycle for each instruction.
In the basic computer each instruction cycle
consists of the following phases
Fetch an instruction from memory
Decode the instruction
Read the efective address from memory if
the instruction has an indirect address
Execute the instruction
upon the completion of step 4, the control goes back to
step1 to fetch, decode, and execute the next instruction.
This process continues unless a HALT instruction is
encountered.

Instruction Cycle

Fetch and Decode

Initially, the program counter PC is loaded with the

address of the first instruction in the program.
The sequence counter SC is cleared to 0, providing
a decoded timing signal T0. After each clock
pulse, SC is incremented by one, so that the
timing signals go through a sequence T0, T1, T2,
and so on. The micro operations for the fetch and
decode phases can be represented by the
following register transfer statements.

Instruction Cycle

T0: AR PC
T1: IR M[AR], PC PC+1

T2: D0,.,D7 Decode IR(12-14), ARIR(011),IIR(15).on

Since only AR is connected to the address inputs of memory,
it is necessary to transfer the address from PC to AR during
the clock transition associated with timing signal T0.
The instruction read from the memory is then placed in the
instruction register IR with the clock transition associated
with the timing signal T1. At the same time, PC is
incremented by one to prepare it for the address of the
next instruction in the program.

Instruction Cycle

At time T2, the operation code in IR is decoded, the

indirect bit is transferred to flip-flop I, and the address
part of the instruction is transferred to AR.
The figure shows how the first two register transfer
statements are implemented in the bus system. To
provide the data path for the transfer of PC to AR we
must apply a timing signal T0 to achieve the following
connection.
1. Place the content of PC onto the bus by making the
bus
selection inputs S2S1S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the
LD input of AR

Instruction Cycle

FETCH and DECODE

T0: AR PC (S0S1S2=010, T0=1)

T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(1
T1

S2

T0

S1 Bus
S0

Memory
unit

7
Address

Read

AR

LD

PC

INR

IR
LD
Common bus

5
Clock

Instruction Cycle

1.
2.

3.

4.

The next clock transition initiates the transfer

from PC to AR since T0=1. In order to
implement the second statement
T1: IR M[AR], PC PC+1 it is necessary to use
timing signal T1 to provide the following
connections in the bus system.
Enable the read input of memory
Place the content of memory on to the bus by making
S2S1S0= 111.
Transfer the content of the bus to IR by enabling the LD
input of IR.
Increment PC by enabling the INR input of PC

Instruction Cycle
Determine the Type of Instruction
The timing signal that is active after the decoding is
T3. During time T3, the control unit determines the
type of instruction that was just read from memory.
Decoder output D7 is equal to 1 if the operation code
is equal to binary 111 we determine that if D7=1,
the instruction must be register or input-output
instruction type. If D7=0, the operation code must
be one of the other seven values 000 through 110,
specifying a memory-reference instruction.

Fig: Flowchart for instruction cycle (initial

configuration)

Instruction Cycle..

Control then inspects the value of the first bit of the

instruction, which is now available in flip-flop I.
If D7=0 and I=1, we have a memory-reference
instruction with an indirect address. It is then
necessary to read the effective address from memory.
The micro operations for the indirect address
condition can be symbolized by the register transfer
statement AR M[AR].Initially, AR holds the address
part of the instruction. This address is used during the
memory read operation. The word at the address
given by AR is read from memory and placed on the
common bus.

Register Reference
Instruction

Register reference instruction are recognized by

the control when D7=1 and I =0. These
instructions use bits 0 through 11 of the
instruction code to specify one of 12
instructions. These 12 bits are available in IR(011). They were also transferred to AR during
time T2

Register Reference Instruction

Register Reference Instruction

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
CLA
CLE
CMA

r:
rB11:
rB10:
rB9:

SC 0
AC 0
E0
AC AC

CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT

rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:

E E
Complement E
AC shr AC, AC(15) E, E AC(0) Circulate right
AC shl AC, AC(0) E, E AC(15) Circulate left
AC AC + 1
Increment AC
if (AC(15) = 0) then (PC PC+1)
Skip if positive
if (AC(15) = 1) then (PC PC+1)
Skip if negative
if (AC = 0) then (PC PC+1)
Skip if AC zero
if (E = 0) then (PC PC+1)
Skip if E zero
S 0 (S is a start-stop flip-flop)
Halt computer

Clear SC
Clear AC
Clear E
Complement AC

Memory Reference
Instructions

The decoded output Di for i = 0, 1, 2, 3, 4, 5, and

6 from the operation decoder that belongs to
each instruction is included in the table. The
effective address of the instruction is in the
address register AR and was placed there during
timing signal T2 when I = 0, or during timing
signal T3 when I = 1.
The execution of the memory-reference
instructions starts with timing signal T4 the
symbolic description of each instruction is
specified in the table in terms of register transfer
notation.

Memory Reference
Instructions

The actual execution of the instruction in the

bus system will require a sequence of micro
operations. This is because data stored in
memory cannot be processed directly. The data
must be read from memory to a register where
they can be operated on with logic circuits.
We now explain the operation of each
instruction and list the control functions and
micro operations needed for their execution

Memory Reference
Instructions
Table: Memory Reference Instruction
Symbol

Operation
Decoder

Symbolic description

AND

D0

AC AC M[AR]

ADD

D1

AC AC + M[AR], E Cout

LDA

D2

AC M[AR]

STA

D3

M[AR] AC

BUN

D4

PC AR

BSA

D5

M[AR]PC, PCAR+1

ISZ

D6

M[AR]M[AR]+1,
If M[AR]+1 =0 then PC PC +1

Memory Reference
Instructions
AND to AC
This is an instruction that performs the AND logic
operation on pairs of bits in AC and the memory word
specified by the effective address. The result of the
operation is transferred to AC. The micro operations that
execute this instruction are:
D0T4 : DR M[AR]
D0T5: AC AC DR, SC 0.
The control function for this instruction uses the operation
decoder D0 since this output of the decoder is active
when the instruction has an AND operation whose binary
code value is 000.
Two timing signals are needed to execute the instruction.

Memory Reference
Instructions
Two timing signals are needed to execute the instruction.
The clock transition associated with timing signal T4
transfers the operand from memory into DR.
The clock transition associated with the next timing signal
T5 transfers to AC the result of the AND logic operation
between the contents of DR and AC.
The clock transition associated with timing signal T4
transfers the operand from memory into DR.
The clock transition associated with the next timing signal
T5 transfers to AC the result of the AND logic operation
between the contents of DR and AC.

Memory Reference
Instruction
ADD to AC
The instruction adds the content of the memory
word specified by the effective address to the
value of AC. The sum is transferred into AC and
the output carry Count is transferred to the E
(extended accumulator) flip-flop. The micro
operations needed to execute this instruction
are
D1T4: DR M[AR]
D1T5: AC AC + DR, E Cout, SC 0

Memory Reference
Instruction

The same two timing signals, T4 and T5, are

used again but with operation decoder D1
instead of D0, which was used for the AND
instruction.
After the instruction is fetched from memory
and decoded, only one output of the operation
decoder will be active, and that output
determines the sequence of micro operations
that the control follows during the execution of
a memory-reference instruction.

Memory Reference
Instruction

LDA : Load to AC
This instruction transfers the memory word
specified by the effective address to AC.
The microoperations needed to execute this
instruction are
D2T4: DR M[AR]
D2T5: AC DR, SC 0

Memory Reference
Instruction

STA : Store AC
This instruction stores the content of AC into
the memory word specified by the effective
address.
Since the output of AC is applied to the bus and
the data input of memory is connected to the
bus,
we can execute this instruction with one micro
operation:
D3T4: M[AR] AC, SC 0

Memory Reference
Instruction

This instruction transfers the program to the

instruction specified by the effective address.
Remember that PC holds the address of the
instruction to be read from memory in the next
instruction cycle in the program sequence.
BUN : Branch Unconditionally
The BUN instruction allows the programmer to
specify an instruction out of sequence and we say
that the program branches (or jumps)
unconditionally. The instruction is executed with one
micro operation:
D4T4: PC AR, SC 0

Memory Reference
Instruction

BSA : Branch and Save Return Address

This instruction is useful for branching to a portion
of the program called a subroutine or procedure.
When executed, the BSA instruction stores the
address of the next instruction in sequence (which
is available in PC) into a memory location specified
by the effective address.
The effective address plus one is then transferred
to PC to serve as the address of the first instruction
in the subordinate. M[AR] PC, PC AR + 1

D5T5: PC AR, SC 0

MEMORY REFERENCE INSTRUCTIONS

BSA: Branch and Save Return Address

Memory, PC, AR at time T4

20 0 BSA 135
PC = 21Next instruction

AR = 135
136

Subroutine

1 BUN 135
Memory

Memory, PC after execution

20 0 BSA 135
21 Next instruction

135
PC = 136

21
Subroutine

1 BUN 135
Memory

Timing signal T4 initiates a memory write

operation, places the content of PC onto the
bus, and enables the INR input of AR.
The memory write operation is completed and
AR is incremented by the time the next clock
transition occurs. The bus is used at T5 to
transfer the content of AR to PC.

Memory Reference
Instruction
ISZ : Increment and Skip if Zero
This instruction increments the word specified by
the effective address, and if the incremented
value is equal to 0, PC is incremented by 1.
This is done with the following sequence of
microoperations:
D T : DR M[AR]
6 4

D6T5: DR DR + 1

D6T6 : M[AR] DR, if (DR = 0) then (PC PC +

1), SC 0

FLOWCHART FOR MEMORY REFERENCE

INSTRUCTIONS
Memory-reference instruction
AND

ADD

LDA

D0 T4
D1 T4
DR M[AR]
DR M[AR]
D0 T5
D1 T5
AC AC DR AC AC + DR
SC 0
E Cout
SC 0
BUN

BSA

STA
D2 T4

DR M[AR]

D3 T4
M[AR] AC
SC 0

D2 T5
AC DR
SC 0

ISZ

D4 T4
D5 T4
D6 T4
PC AR
M[AR] PC
DR M[AR]
SC 0
AR AR + 1
D5 T5
PC AR
SC 0

D6 T5
DR DR + 1
D6 T6

M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0

Instruction Formats

Computers fall into one of three types of CPU

organizations.
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization
Single Accumulator Organization: All
operations are performed with an implied
accumulator register. The instruction format of
this type of computer uses one address field.
Ex: ADD X
AC AC + M[X]

Instruction Formats

Computers fall into one of three types of CPU

organizations.
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization
Single Accumulator Organization: All
operations are performed with an implied
accumulator register. The instruction format of
this type of computer uses one address field.
Ex: ADD X
AC AC + M[X]

Instruction Formats

Computers fall into one of three types of CPU

organizations.
1. Single Accumulator Organization
2. General Register Organization
3. Stack Organization
Single Accumulator Organization: All
operations are performed with an implied
accumulator register. The instruction format of
this type of computer uses one address field.
Ex: ADD X
AC AC + M[X]

Instruction Formats
General Register Organization: The
instruction format in this type of computer needs
three registers address fields.
ADD R1, R2, R3
R1 R2+ R3
We can reduce from three to two if the destination
register is the same as one of the source register.

ADD R1, R2
MOV R1, R2

R1 R1+R2
R1 R2 (OR R2 R1)

Thus ,a transfer type of instruction need two

address fields to specify the source and the
destination.

Instruction Formats
ADD R1, X
R1 R1 + M[X].
It has two address fields, one form register R1
and the other from the Memory address X.
Computers with Stack organization would
have PUSH and POP instructions which
require an address field.
Thus the instruction
PUSH X Will push the word at X to the top
of stack. Operation type instruction do not
need an address field in stack organized
computers.

Instruction Formats

To illustrate the influence of the number of

addresses on computer programs, we will
evaluate the arithmetic statement X = (A + B) *
(C + D) using zero, one, two, or three address
instructions.
We will use the symbols ADD, SUB, MUL and
DIV for the four arithmetic operations.
We assume that the operands are in memory at
address A, B, C and D; and the result must be
stored in memory at address X.

Instruction Formats

Three- Address Instructions: Computer with

three addresses instruction format can use each
address field to specify either processor register
are memory operand.
X = (A + B) * (C + A)
ADD
R1, A, B
R1 M [A] + M
[B]
ADD
R2, C, D
R2 M [C] + M
[D]
MUL X, R1, R2
M [X] R1 * R2

Instruction Formats
The advantage of the three address formats is
that it results in short program when evaluating
arithmetic expression.
The disadvantage is that the binary-coded
instructions require too many bits to specify
three addresses.
Two Address Instruction:
Most common in commercial computers. Each
address field can specify either a processes
register on a memory word.
X = (A + B) * ( C + D)

Instruction Formats

MOV

R1, A

R1M [A]

ADD

R1, B

R1 R1 + M [B]

MOV

R2, C

R2 M [C]

ADD

R2, D

R2 R2 + M [D]

MUL

R1, R2

R1 R1 * R2

MOV

X, R1 M [X] R1

One Address instruction

It used an implied accumulator (AC) register for
all data manipulation. For multiplication/division,
there is a need for a second register.

Instruction Formats

LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X

AC M [A]
AC AC + M [B]
M [T] AC
AC M (C)
AC AC + M (D)
AC AC * M (T)
M [] AC

Instruction Formats
All operations are done between the AC register
and a memory operand. Its the address of a
temporary memory location required for storing
the intermediate result.
Zero Address Instruction
A stack organized computer does not use an
address field for the instruction ADD and MUL.
The PUSH & POP instruction, however, need an
address field to specify the operand that
communicates with the stack (TOS top of the
stack)

Instruction Formats

PUSH

TOS A

PUSH

TOS B

ADD

PUSH

TOS C

PUSH

TOS D

ADD

TOS (C + D)

MUL
POP

TOS (C + D) * (A + B)
M [X] TOS

TOS (A + B)

Addressing Modes

Addressing is a method to provide access to the

data stored in memory.
Different ways in which the address of an operand
is specified in an instruction is referred to as
addressing mode. The operation field of an
instruction specifies the operation to be
performed. This operation must be executed on
some data stored in computer register as memory
words.
The way the operands are chosen during program
execution is dependent on the addressing mode of
the instruction.

Addressing Modes

The addressing mode specifies a rule for

interpreting or modifying the address field of
the instruction between the operand is activity
referenced. Computer use addressing mode
technique for the purpose of accommodating
one or both of the following provisions.

1. To give programming versatility to the uses by

providing such facilities as pointer to memory, counters
for top control, indexing of data, and program
relocation.
2. To reduce the number of bits in the addressing fields of
the instruction.

Addressing Modes

1.
2.
3.

The basic operation cycle of the computer

Fetch the instruction from memory
Decode the instruction
Execute the instruction

The decoding done in phase 2 determines the

operation to be performed, the addressing
mode of the instruction, and the location of the
operands. The computer then executes the
instruction and return to step 1 to fetch the
next instruction.

Addressing Modes

Instructions may be defined with a variety of

addressing modes and sometimes, two or more
addressing modes are combined in one instruction.
There may or may not be an address field in the
instruction. If there is an address field, it may
designate a memory address or a processor register.
Addressing modes modify the address field of the
instruction, there are two modes that need no
address field at all. These re implied and immediate
modes.
Various addressing modes are

Addressing Modes

(1) Implied mode

(2) Immediate mode
(3) Register mode
(4) Register mode
(5) Register indirect mode
(6) Auto increment/ Auto decrement mode
(7) Direct Address mode
(8) Indirect Address mode
(9) Relative Address mode
(10) Indexed Addressing mode
(11) Base Register Addressing mode

Addressing Modes

Implied Mode:
In this mode the operands are specified
implicitly in the definition of the instruction.
For example: The instruction complement
accumulator is an implied mode instruction
because the operand in the accumulator register
is implied in the definition of the instruction.
In fact, all register reference instructions that
use an accumulator are implied mode
instructions

Addressing Modes
Zero-address instructions in a stack organization
computer are implied-mode instructions since the
operands are implied to be on top of the stack.
Examples
RAL : Rotate the contents of the accumulator left
RLC: Rotate the contents of the accumulator left
through carry
CMA : Take the complement of the contents of the
accumulator

Addressing Modes
Immediate Mode: In this mode the operand is
specified in the instruction itself. In other words, an
immediate mode instruction has an operand field
rather than address field.
Example:
MVI A, 06 : Move 06 to the accumulator
ADI 05 : Add 05 to the content of the accumulator
Register Mode: In this mode the operands are in
registers that reside within the CPU. In other words
the contents of a register is the operand.

Addressing Modes

Example:
MOV A ,B : Transfer the contents of the register B to register A.
ADD B : Add the contents of the register B to the contents of the
accumulator.

No memory access
Very fast execution
Very limited address space

Register Indirect Mode: In this mode the

instruction specifies a register in the CPU whose
contents gives the address of the operand in
memory. In other words, the selected register
contains the address of the operand rather than the
operand itself.

Register Indirect Addressing Diagram

Instruction
Opcode

Register Address R

Memory

Registers

Pointer to Operand

Operand

Addressing Modes
Direct Addressing: In this mode the effective
address is equal to the address part of the
instruction. The operand resides in memory and
its address is given directly by the address field
of the instruction.
Advantages:
Single memory reference to access data
No additional calculations to work out effective
address
Limited address space

Direct Addressing Diagram

Instruction
Op code

Address A
Memory

Operand

Addressing Modes

Indirect Addressing: In this mode the address

field of the instruction gives the address where
the effective address is stored in memory.
Control fetches the instruction from memory
and uses its address part to access memory
again to the read the EA.
e.g. ADD (A) : Add contents of cell pointed to by
contents of A to accumulator
Multiple memory accesses to find operand
Hence slower

Indirect Addressing
Diagram
Instruction
Opcode

Address A
Memory
Pointer to operand

Operand

Addressing Modes

Auto Increment or Auto Decrement Mode

This is similar to the register indirect mode
except that the register is incremented or
decremented after(or before) its value is used
to access memory.
When the address stored in the register refers
to a table of data in memory, it is necessary to
increment or decrement the register after every
access to the table.

Addressing Modes

Relative Addressing Mode: In this mode the

content of PC is added to the address part of the
instruction in order to obtain the effective address.
Example: Assume that the PC contains an address
825 and the address part of the instruction contains
the number 24. The instruction at location 825 is
read from the memory during the fetch phase and
the PC is then incremented by one to 826. The EA
computation for the relative address mode is
826+24=850
Relative addressing is often used with branch-type
instructions.

Addressing Modes
Direct Relative Addressing Mode:
Address of operand = EA
= Content of PC +
Displacement
Indirect Addressing Mode: Address of operand
is calculated by adding the content of register
indicated by the base register and displacement
Address of Operand = EA
= Displacement + Base
address

Addressing Modes

Example:

Main Memory

If PC
ADD

R1

24

800

800
24

100

Here 800+24 =824; the address of the

memory Location.
Now, 100 will be added to the content of
register R1

Addressing Modes
Indexed Addressing Mode:
In this mode the content of an index register is
added to the address part of the instruction to
obtain EA. The index register is a special CPU
register that contains an index value

Example:
index
ADD

R1

500

24

Here the index register contains

the index value
EA= 500 +24 =524. Now 1001 will
be added to the content of R1

50
0
52
4

Main
Memory

1001