SERIAL

PERIPHERAL
INTERFACE
(SPI)

M Serial Peripheral Interface Module MTT48 8-1

 Module Objective

Understand SPI format and data transfersgure the control registers

Transmit and receive data

Module exercise:

Configure the SPI to transmit and receive characters to/from another

device in Master mode at a 1 MHz rate

M Serial Peripheral Interface Module MTT48 8-2

SERIAL PERIPHERAL INTERFACE MODULE
System LVI IRQ Direct
Clock 68HC08 Timer
Generation Integration Interface Memory
RESET CPU Access
Module Module Module
(CGM) (SIM) (TIM) Module
COP BREAK (DMA)

Internal Bus (IBUS)

Serial Random Electronically Monitor

Serial
Peripheral Access Programmable ROM
Communications
Interface Memory ROM
Interface
(SPI) (RAM)
(SCI)

• Features of the SPI module include the following:

• Full-Duplex Operation
• Master and Slave Modes
• Separate Transmit and Receive Registers
• Four Master Mode Frequencies (Maximum = Bus Frequency •2)
• Maximum Slave Mode Frequency = Bus Frequency
• Separate Clock Ground for Reduced Radio Frequency (RF) Interference
• Serial Clock with Programmable Polarity and Phase
• Bus Contention Error Flag
• Overrun Error Flag
• Two Separately Enabled Interrupts with DMA or CPU Service:
SPRF (SPI Receiver Full)
SPTE (SPI Transmitter Empty)
• Programmable Wired-OR Mode
• I2C (Inter-Integrated Circuit) Compatibility

M Serial Peripheral Interface Module MTT48 8-3

 SPI I/O Registers

Three registers control and monitor SPI operations:

• SPI Control Register (SPCR)
• SPI Status and Control Register (SPSCR)
• SPI Data Register (SPDR)

M Serial Peripheral Interface Module MTT48 8-4

 SPI Modes

Master mode
• Only a master SPI initiates a transmission
• Data is shifted out via Master Out Slave In (MOSI) line
• Data is shifted in via Master In Slave Out (MISO) line
• Transmission ends after 8 cycles of serial clock (SPSCK)

Slave Mode
• Transfer synchronized to serial clock (SPSCK) from Master
• Data is shifted in via the Master Out Slave In (MOSI) line
• Data is shifted out via the Master In Slave Out (MISO) line

M Serial Peripheral Interface Module MTT48 8-5

 Slave Select Pin
MASTER SLAVE
MOSI

Shift Register MISO Shift Register

SPSCK
Baud Rate Gen. SS +5v

SS
Slave Select (SS)
• Master mode
– SS held high during transmission
– Acts as error detection input
– Can be general purpose output
• Slave mode
– SS must remain low until transmission completes
0 = Enables slave
1 = Disables slave

M Serial Peripheral Interface Module MTT48 8-6

 SPI Control Register
READ:
SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Control Register (SPCR)

• SPI Master (SPMSTR) • SPI Enable (SPE)
– Selects master mode or slave mode operation 1 = SPI module enabled
1 = Master mode 0 = SPI module disabled
0 = Slave mode
Recommend disabling SPI before initializing or
changing clock phase, clock polarity, or baud
• SPI Master and Slave need identical clock polarity and rate

phase settings
• Clock Polarity (CPOL)
– Determines clock state when idle
• Clock Phase (CPHA)
1 = Begin capturing data on second clock cycle edge
0 = Begin capturing data on first clock cycle edge*
– When CPHA = 0, the SS must be deasserted and reasserted
between each transmitted byte
M Serial Peripheral Interface Module MTT48 8-7
 Clock Polarity and Phase

SPI Control Register (SPCR)

• SPI modules need identical Clock polarity and phase

SS
CPHA CPOL

0 0 SPSCK

1 0 SPSCK

0 1 SPSCK

1 1 SPSCK

MOSI/MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

Capture Strobe

M Serial Peripheral Interface Module MTT48 8-8

 SPI Baud Rate

READ: SPRF 0 OVRF MODF SPTE 0

SPSCR SPR1 SPR0
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Status and Control Register (SPSCR)

• SPI rate select bits (SPR1, SPR0)
– Sets the Master SPSCK clock frequency
– No effect in the Slave devices
– Baud Rate = CGMOUT / Baud Rate Divisor

System Clock Baud Rate

SPR1:SPR0
Divided By (System Clock Freq. = 8 MHz)
00 2 4 MHz
01 8 1 MHz
10 32 250 KHz
11 128 62.5 KHz

M Serial Peripheral Interface Module MTT48 8-9

 SPI Data Register

READ:
SPDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WRITE:

RESET: UNAFFECTED BY RESET

SPI Data Register (SPDR)

• Read/Write buffer for SPI data
• Write operation
– Writes data to transmit data register
• Read operation
– Reads data in receive data register

M Serial Peripheral Interface Module MTT48 8-10

 SPI Status Flags

READ: SPRF 0 OVRF MODF SPTE 0

SPSCR SPR1 SPR0
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Status and Control Register (SPSCR)

• SPI Receiver Receiver Full (SPRF)
– Set when a byte is shifted from shift register to the receive data register
– Cleared by reading SPSCR then reading SPDR

1 = Receive data register full

0 = Receive data register not full
• SPI Transmitter Empty (SPTE)
– Set when a byte is transferred from SPDR to the shift register
– Cleared by reading SPDR register

1 = Transmit data register empty

0 = Transmit data register not empty

M Serial Peripheral Interface Module MTT48 8-11

 SPI Interrupts
READ:
SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Control Register (SPCR)

• SPI Receiver Interrupt Enable Bit (SPRIE)
– Interrupt generated when SPRF flag set

• SPI Transmit Interrupt Enable (SPTIE))

– Interrupt generated when SPTE flag set
1 = Interrupt enabled
0 = Interrupt disabled

• Direct Memory Access Select (DMAS)

– Selects either DMA or CPU interrupt request
– SPRIE/SPTIE bits still enable or disable interrupts

M Serial Peripheral Interface Module MTT48 8-12

 Initialization

SPI Initialization sequence

1) Initialize SPI clock frequency ( SPR1 and SPR0 in SPSCR )

2) Set clock configuration ( CPOL and CPHA bits in SPSCR )

3) Select Master/Slave operation ( SPMSTR in SPCR )

4) Enable interrupts if desired ( SPTIE, SPRIE in SPCR )

5) Enable the SPI system ( SPE in SPCR )

• Should enable Master before Slaves

M Serial Peripheral Interface Module MTT48 8-13

 Master to Slave Transfer

Simple Polled operation

1) Initialize the SPI

2) Select SS to Slave device (hardware dependent

3) Write byte to SPDR

4) Wait for SPI Transmitter Empty Flag (SPTE)

5) Read the SPDR

6) Release SS to Slave (hardware dependent)

M Serial Peripheral Interface Module MTT48 8-14

 SPI Exercise

Part 1:
Initialize a SPI to the following:
Master mode
1 MHz baud rate ( 8 MHz system clock )
Clock phase = 1 and clock polarity = 0
Polled operation

Part 2:
Write a procedure to transmit the character in the
Accumulator to the Slave device. Then wait for the
received character and place it into the Accumulator.
(The Master SS is tied to VDD and the Slave SS is tied to
ground)

M Serial Peripheral Interface Module MTT48 8-15

 Serial Peripheral Interface Module MTT48 8-16

SPI Config & Transmit Exercise

Write a routine that configures the SPI as a master, non-interrupt driven and then transmits the
value $55. The SPI is connected to a serial-in/parallel out 8-bit shift register. The shift register
is chip-selected with the PB3 line at low voltage level. Between transfers, the PB3 line must be
high. It requires the clock to idle low and takes data on rising clock edges. The serial clock
cannot exceed 300 KHz. Assume System Clock Frequency = 8 MHz.
Write your program here: Suggested program steps:
PTB EQU $01 Addresses for: Port B Data register
PTF EQU $09 Port F Data register
DDRB EQU $05 Port B Data Direction register
DDRF EQU $0D Port F Data Direction register
SPCR EQU $10 SPI Control register
SPSCR EQU $11 SPI Status and Control register
SPDR EQU $12 SPI Data (Read=rcv, Write=xmt)
CONFIGURATION:
Select Port F inputs/outputs & levels :
1. Make PB3 output value high.
2. Make PB3 an output.
3. Load accumulator with
" MOSI & SPSCK = outputs" value.
" MISO & SS* = inputs" value.
4. Store accumulator to DDRF register.
Select master mode, clock operation, & enable SPI:
5. Load ACC. with value that selects freq Š 300 KHz.
6. Store accumulator to SPSCR register.
7. Load accumulator with value that selects master
mode, clock phase = rising edge, polarity = idle
low, active pullup outputs, interrupts disabled,
SPI enabled.
8. Store accumulator to SPCR register.
Send $55 to shift register:
9. Make PB3 output low (chip-select shift register).
10. Load accumulator with $55.
11. Store accumulator to SPDR register.

M
12. Stay here until transmission is complete.
13. Make PB3 output high (deselect shift register).
14. Done, stay here.
HC08-SPIExer
 Additional Information
Wired-Or Mode

READ:
SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Control Register (SPCR)

• SPI Wired OR Mode (SPWOM)
– Configures MISO, MOSI, and SPSCK outputs to be open-drain drivers
– Allows multiple-master systems
– Provides some protection against CMOS latchup

M Serial Peripheral Interface Module MTT48 8-17

 Additional Information
Overflow and Mode Fault Status Flags

READ: SPRF 0 OVRF MODF SPTE 0

SPSCR SPR1 SPR0
WRITE:

RESET: 0 0 0 0 1 0 0 0

SPI Status and Control Register (SPSCR)

• Overflow flag (OVRF)
– Failure to read data register before it is over written
– Incoming data bytes are lost
• Data register contents unaffected
– Cleared by reading the data register
• Mode Fault flag (MODF)
– Master mode only
– Indicates another master tried to access this device
– Set when another device pulls SS pin low
– Cleared by a write to the SPSCR

M Serial Peripheral Interface Module MTT48 8-18

 Additional Information
Low Power Modes

Low Power Modes

• WAIT
– SPI mode remains active
– SPI registers are not accessible
• Except by DMA
– Enabled SPI interrupts will exit wait mode
• STOP
– SPI module becomes inactive
– No affect on register conditions
– Operation continues after an external interrupt

M Serial Peripheral Interface Module MTT48 8-19

 Register Summary

READ:
SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE
WRITE:

READ: SPRF 0 OVRF MODF SPTE 0

SPSCR SPR1 SPR0
WRITE:

READ:
SPDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WRITE:

M Serial Peripheral Interface Module MTT48 8-20

 Serial Peripheral Interface Module MTT48 8-21

SPI Config & Transmit Solution

Write a routine that configures the SPI as a master, non-interrupt driven and then transmits the
value $55. The SPI is connected to a serial-in/parallel out 8-bit shift register. The shift register
is chip-selected with the PB3 line at low voltage level. Between transfers, the PB3 line must be
high. It requires the clock to idle low and takes data on rising clock edges. The serial clock
cannot exceed 300 KHz. Assume System Clock Frequency = 8 MHz.
Write your program here: Suggested program steps:
PTB EQU $01 Addresses for: Port B Data register
PTF EQU $09 Port F Data register
DDRB EQU $05 Port B Data Direction register
DDRF EQU $0D Port F Data Direction register
SPCR EQU $10 SPI Control register
SPSCR EQU $11 SPI Status and Control register
SPDR EQU $12 SPI Data (Read=rcv, Write=xmt)
CONFIGURATION:
Select Port F inputs/outputs & levels :
BSET #3,PTB 1. Make PB3 output value high.
BSET #3,DDRB 2. Make PB3 an output.
LDA #$06 3. Load accumulator with
" MOSI & SPSCK = outputs" value.
" MISO & SS* = inputs" value.
STA DDRF 4. Store accumulator to DDRF register.
Select master mode, clock operation, & enable SPI:
LDA #$02 5. Load ACC. with value that selects freq Š 300 KHz.
STA SPSCR 6. Store accumulator to SPSCR register.
LDA #$22 7. Load accumulator with value that selects master
mode, clock phase = rising edge, polarity = idle
low, active pullup outputs, interrupts disabled,
SPI enabled.
STA SPCR 8. Store accumulator to SPCR register.
Send $55 to shift register:
BCLR #3,PORTB 9. Make PB3 output low (chip-select shift register).
LDA #$55 10. Load accumulator with $55.
STA SPDR 11. Store accumulator to SPDR register.

M
WAIT BRCLR #7,SPSCR,WAIT 12. Stay here until transmission is complete.
BSET #3,PORTB 13. Make PB3 output high (deselect shift register).
DONE BRA DONE 14. Done, stay here.
HC08-SPISol