Logic Design – EEE205

CH 7
Latches & Flip-Flops

BY

Dr. Hassan
SHARABATY
Ankara – November 2017 1

Latches
A latch is a temporary storage device that has two stable states (bistable).
It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type.
 Using NOR gates, the latch responds to active-HIGH inputs;
 Using NAND gates, it responds to active-LOW inputs.

0 S
0 0R Q 0 1 0 Q
Latch

Q 1 0 1 Q
0 0 0 S R
Active-HIGH input Latch (NOR) Active-LOW input Latch (NAND)
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 Latches
The active-HIGH S-R latch will be in a stable condition (latched)
when both inputs are LOW.
Assume the latch is initially RESET (Q = 0)
0 R
10 Q
and the inputs are at their inactive level
Latch
(0). initially
To SET the latch (Q = 1), a brief HIGH
signal is applied to the S input while the R 10 RESET
Q
0 S
remains LOW.
To RESET the latch (Q = 0), a brief 0 R
10
Q
HIGH signal is applied to the R input
Latch
while the S remains LOW. initially
10 SET
Q
0 S

Latches
 The active-LOW S-R latch is in a stable (latched) condition

when both inputs are HIGH.

Assume the latch is initially RESET (Q = 0)

1 S 0
and the inputs are at their inactive level 1 Q
Latch
(1). initially
 To SET the latch (Q = 1), a brief LOW
RESET
01
signal is applied to the S input while the R
1 R
remains HIGH. Q

To RESET the latch a brief LOW is 1 S 01

Q

applied to the R input while S is HIGH. Latch

initially
SET
Never apply an active set and
1 10 Q
reset at the same time (invalid). R

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Latches

Active-High inputs S-R latch

Latches

Active-LOW inputs S-R latch

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 Latches

Determine the waveform that will be observed on the Q output.

Assume that Q is initially LOW.

Solution

The following waveforms are applied to an active-LOW input S-R

latch.
- Draw the output waveform Q.
- Assume that Q starts LOW.

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The following waveforms are applied to an
active-HIGH input S-R latch.
- Draw the output waveform Q.
- Assume that Q starts LOW.

The following waveforms are applied to an

active-LOW input S-R latch.
- Draw the output waveform Q.
- Assume that Q starts LOW.

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 Gated Latches

The gated latch has an additional

input, called enable (EN) that

must be HIGH in order to the latch
respond to the S and R inputs.

 EN is Active  output is controlled

by the state of the S and R inputs.

EN is inactive  output will latch the

previous state (no change in the output)

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Gated Latches

Show the Q output with relation to the

input signals. Assume Q starts LOW.

Keep in mind that S and R are only active when EN is HIGH.

S
R
EN

When S is HIGH and R is LOW, a HIGH on the EN input sets the latch.
When S is LOW and R is HIGH, a HIGH on the EN input resets the latch.
When both S and R are LOW, the Q output does not change from its present state.

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The following waveforms are applied to a
gated S-R latch. Determine the outputs
Q & Q, assuming that Q start in LOW.

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The following waveforms are applied to a

gated S-R latch. Determine the outputs Q &
Q, assuming that Q start in LOW.

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The following waveforms are applied to a
gated S-R latch. Determine the outputs Q &
Q, assuming that Q start in LOW.

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The D Latch

If we combine the S and R inputs into a single input D as shown,

we get another type of gated latch called the D latch :

SD
Q D
Q Q
EN
EN EN
Q
Q
R Q

A simple rule for the D latch

is:
Q follows D when the
Enable is active.
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The D Latch

The truth table for the D latch summarizes its operation. Note:

If EN is LOW, then previous output will not change (i.e latched).

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The D Latch
D Q

EN
Determine the output Q for the given
Q
the inputs shown.

Notice that “Enable input” is not active during these intervals ,

so the output is latched.

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 D Q

Show the output waveform in case of the EN

following input waveforms. The latch is initially
Q
RESET.

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Flip-flops

A flip-flop is an edge-triggered device, which means that the output is

sensitive to its inputs only upon an active transition (edge) on the

triggering input called the clock (CLK).
The active edge can be positive (rising edge)
or negative (falling edge).

Dynamic input
indicator

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 Flip-flops

 Upon active edge  The output will respond to flip-flop inputs.

 Without an active edge  No change in the output (Previous output).

Sensitive to inputs Sensitive to inputs

upon (rising edge) upon (falling edge)

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Edge-Triggered S-R Flip-Flop

positive edge-triggered S-R flip-flop

negative edge-triggered S-R flip-flop

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Determine the Q waveforms. Assume that the
flip-flop is initially RESET.

Any change in R or S after the triggering edge of the clock has no effect
on the output
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Draw the Q output of each flip-flop, if they are initially RESET.

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The Edge-Triggered D Flip-Flop

Q follows D on the active edge, otherwise no change.

(a) Positive-edge triggered

(b) Negative-edge triggered

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The Edge-Triggered D Flip-Flop

Q follows D on the active or triggering clock edge.

(a) Positive-edge triggered (b) Negative-edge triggered

Determine Q waveform if the flip-flop starts out RESET.

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Draw the Q output relative to the clock for a D flip-flop.
Assume positive edge-triggering and Q initially
LOW.

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Draw the Q output relative to the clock for a D flip-flop.

Assume positive edge-triggering and Q initially
LOW.

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 The Edge-Triggered J-K Flip-Flop

 J-K flip-flop is similar to S-R flip-flop, however

don’t have invalid state.

 J = K = 1,

output state
will be
inversed upon
the active
clock edge .
 The truth table for a negative edge-triggered J-K
flip-flop is the same, except that the triggering
edge is the falling edge of the clock pulse.
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Determine the Q output, starting in the RESET state.

A change in J or K after the triggering edge of the clock has no

effect on the output
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 Determine the Q output, assuming
that the flip-flop is initially RESET.
Notice that the outputs change on
the falling edge of the clock.

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Determine the Q output for the J-K flip-flop, Q

J
assuming that the flip-flop is initially SET.
CLK
Notice that the outputs change
on the rising edge of the clock. K Q

Set Toggle Set Latch

CLK

Q 32
 J Q

Determine the Q output relative to the CLK

clock. Assume that Q starts LOW. K Q

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Develop the Q output waveform

relative to the clock. Assume that Q is
initially LOW.

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 Asynchronous Preset and Clear Inputs

Flip-flops inputs ( D, J-K …) are called “synchronous inputs” because

data on these inputs are transferred to output only on active edge of the
clock pulse.

 Most flip-flops have other inputs that affect the output regardless of
the clock (not synchronized). PRE

An active preset “PRE” input makes the Q

output HIGH (SET). J Q

An active clear “CLR” input makes the Q CLK

output LOW (RESET).

K Q

These inputs are usually active LOW (PRE and CLR ).

CLR

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PRE
Asynchronous Preset and Clear Inputs
Most flip-flops have other inputs that affect the J Q

output regardless of the clock (not synchronized). CLK

These inputs are usually active LOW (PRE and CLR ). K Q

Assum that the flip-flop is initially SET

CLR
Set Toggle Set Reset Latch
CLK Toggle

Set
PRE
K Reset
CLR

Q
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 determine the output Q if it is initially LOW.

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Determine the Q waveform. Assume

that Q is initially LOW.

Toggle Latch Toggle Latch

Latch Toggle

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 Ideal pulse
Flip-flop Characteristics
CLK

Propagation delay time is the required time interval to

change the output (after applying the input signal).

CLK

Propagation delays, clock to output.

The typical propagation delay time for the 74AHC family (CMOS) is 4 ns.

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Flip-flop Characteristics
 Another propagation delay time specification is the time required

for an asynchronous input to cause a change in the output.

Propagation delays, preset input to output

and clear input to output.

The 74AHC family has specified delay times

under 5 ns.
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 Flip-flop Characteristics

Set-up time and hold time are times required before and after
the clock transition that data must be present to be reliably clocked
into the flip-flop.
D
Setup time t s is the minimum
time for the data to be CLK
present
before the clock Set-up time, ts
transition.
Hold time tH is the minimum D

time for the data to remain

after the clock transition. CLK

Hold time, tH
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Flip-flop Characteristics

 Other specifications include

Maximum clock frequency fmax : the highest rate of triggering

input that the flip-flop can respond quickly enough.

 Minimum pulse widths tW for various inputs PRE , CLR ,

D…

 Power dissipation P which is the product of the supply voltage

and the average current required.

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 Flip-flop Applications

Some of flip-flops applications are:

- Data storage.
- Frequency division.
- Counters.

Parallel Data Storage:

A group of flip-flops are connected to
parallel data lines and clocked together.

Data is stored until the next clock pulse.

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Flip-flop Applications
HIGH HIGH
Frequency division
To divide the frequency, we use a J QA J QB
fout
series of flip-flops (connected in CLK CLK
fin
toggle mode), so that each flip-flop
K K
divide the input frequency by two.

fin
One flip-flop will divide fin
QA
by 2, two flip-flops will

divide fin by 4 (and so on). fout

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 Flip-flop Applications
Example
Determine the fout waveform,
if an fin = 8 kHz square wave
is applied to the clock input
of flip-flop A.
Solution: 8 kHz
4 kHz
2 kHz

1 kHz

How many flip-flops are required to divide a frequency by thirty-two? 5 Flip-flops

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Flip-flop Applications

Counters
Both flip-flops should be
initially RESET.
Flip-flop A will be toggled on
the negative-going transition of
each clock pulse.
The Q output of flip-flop A
clocks flip-flop B, so each time
QA makes a HIGH-to-LOW
transition, flip-flop B toggles.

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 Flip-flop Applications
Example
Determine the output
waveforms for QA, QB, and
QC and show the binary
sequence represented by
these waveforms.

Solution:
The outputs go through the
binary sequence 000, 001,
010, 011, 100, 101, 110,
and 111 as indicated.

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Selected Key Terms

Latch A bistable digital circuit used for storing a bit.

Bistable Having two stable states. Latches and flip-flops are

bistable multivibrators.

Clock A triggering input of a flip-flop.

D flip-flop A type of bistable multivibrator in which the output
assumes the state of the D input on the triggering edge
of a clock pulse.

J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-
change, and toggle modes.

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 Selected Key Terms

Propagation The interval of time required after an input signal has

delay been applied for the resulting output signal to change.
time
Set-up time The time interval required for the input levels to be on a
digital circuit.

Hold time The time interval required for the input levels to remain
steady to a flip-flop after the triggering edge in order to
reliably activate the device.

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1. The output of a D latch will not change if

a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above

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2. The D flip-flop shown will
a. set the output on the next clock pulse
b. reset the output on the next clock pulse
c. latch previous output on the next clock pulse
d. toggle the output on the next clock pulse

D Q

CLK CLK

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3. Assume the output is initially HIGH on a rising edge triggered

J-K flip flop.

For the inputs shown, on which clock pulse, will the output go from
HIGH to LOW?

a. 1 CLK

b. 2
K
1 2 3 4
c. 3

d. 4
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4. The application illustrated is a
a. Timer. HIGH HIGH

b. data storage device f out

J QA J QB
c. frequency multiplier
fin CLK CLK
d. frequency divider
K K

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Output
5. The application illustrated is a lines
D Q0
a. Timer. C

b. data storage device

R

D Q1
c. frequency multiplier C

d. frequency divider D Q2
C
Parallel data
input lines R

D Q3
Clock C

R
Clear

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6. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q

c. 3 CLK

d. 4 K Q

CLR

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7. The time interval illustrated is called

a.tPHL 50% point on triggering edge

b. tPLH CLK

c. set-up time
Q 50% point on LOW-to-
HIGH transition of Q
d. hold time ?

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8. The time interval illustrated is called
a. tPHL
b. tPLH D

c. set-up time CLK

d. hold time ?

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Answers:
1. 6. b
b
2. 7. b
d
3. c 8. d
4. d
5.
b

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