Intel 8085 Microprocessor Architecture
Intel 8085 Microprocessor Architecture
Architecture
Introduction
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Functional Description of
8085
• It is a 40 pin IC package and uses +5V for power.
• It can run at a (maximum) frequency of 3MHz.
• The modified versions of the 8085 processor have
these minimum common feature and functional
similarities.
• 8-bit processor - data length is 8-bit - has a data
bus of 8-bits wide
• Addressing capability of 16-bit
• That means it can address 2^16= 64K Bytes of
memory (1Kbyte =1024 byte).
Functional Units of 8085
processor
• The processor consists of five functional units:-
• Arithmetic and logic Unit
• General purpose registers
• Special Purpose Registers
• Instruction register and decoder and
• Timing and control unit.
Arithmetic Logic Unit
(ALU)
• ALU is the circuitry which performs the actual
arithmetic and logical operations.
• Addition (ADD), subtraction (SUB), increment (INR),
decrement (DCR) etc. are the arithmetic operations
available with 8085 microprocessor.
• The possible logical operations in 8085 are AND
(ANA), OR (ORA), EXLUCIVE OR (XRA),
COMPARE(CMP), COMPLEMENT (CMA) etc.
Arithmetic Logic Unit
(ALU) Contd..
• The data is fetched from the memory, the
operation executed with the content of the
accumulator - results stored in the Accumulator
• ALU of 8085 is called accumulator oriented ALU -
one of the data for arithmetic and logical
operations - is stored in accumulator.
• If the operation needs only one data, then that
data usually be stored in accumulator.
The general-purpose
registers
• A register - collection of 8 flip-flops with parallel in
and parallel out operation.
• A flip-flop can only store one bit so to handle 8 bits
at a time, 8 flip-flops and named as an 8-bit
register.
• Registers - storage areas inside the microprocessor
- they differ by the purpose of storage.
The general-purpose
registers Contd..
• The five flag bits are Zero (Z), Carry (CY), Sign (S),
Parity (P), and Auxiliary Carry (AC) flags.
• The remaining three bits (D1, D3 and D5) of the flag
register remain unassigned and they are marked
with an X to show that they are not used and are
don’t cares.
• It provides the status of µP after every instruction.
Flag Register Bit Position
The flag register Contd..
• D7 D6 D5 D4 D3 D2 D1 D0
Parity flag(P)
• The parity flag is set if the content of the
accumulator after an arithmetic operation has an
even number of 1’s.
• Otherwise the parity flag is reset. It is set for
operation in the even parity mode.
• Parity is number of 1’s
• If parity is even, parity flag is set (1).
• If parity is odd, parity flag is reset (0).
Program counter (PC)
• PC is a 16-bit register, which always points to the
address of next instruction to be executed.
• In other words this register is used to sequence
the execution of the instructions.
• At the end of execution of any instruction, the
content of the memory location indicated by PC is
moved to instruction register and the PC is loaded
with the new address to indicate the next address.
• As it keeps track of program by always counting
the memory address from which the next byte is
to be fetched, a self-explanatory name is given.
Stack Pointer (SP)
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Data Bus
• IO/M~ (output)
a) It is a signal that distinguishes between a
memory operation and an IO operation.
b) An active low on this signal shows it is a
memory operation (IO/M~=0) and a high on this
line indicates an IO operation (IO/M~=1).
Control Signals – 8085
S1 and S0 (output)
• They are status signals, used to specify the kind of operation
being performed. (Also Indicate- Data Bus Status)
• The status signals combined with I/O signals to govern the
different operations as listed in Table
• If both S0 and S1 are low, the operation of the processor
tends to halt.
• If S1 low and S0 is high, the processor reads the data. While
the processor writes data on to a memory or I/O, S1 is high
and S0 is low.
• If both S0 and S1 are high, the instruction fetch operation is
performed.
Status signals-operations
Interrupts
• INTR: (Input)
It is a general purpose interrupt request signal. It
is an active high signal
• INTA~: (output)
It is used to acknowledge an interrupt. It is an
active low signal.
Interrupt Signals
• INTR (Input)
a) INTERRUPT REQUEST is used as a general purpose
interrupt.
b) If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA ~ will be
issued.
c) During this cycle a RESTART (RST) or CALL instruction
can be inserted to jump to the interrupt service
routine (ISR).
They are used to make the processor execute a
subroutine at a predefined address called ISR
Interrupt contd…
• RST (Restart Interrupts): (Input)
• These are interrupts that transfer the program control to
specific memory locations. These are all maskable.
• They have higher priority than INTR interrupts. The
priority order is RST 7.5, RST 6.5 and RST 5.5
• TRAP: (Input)
• It is a non-maskable interrupt and has the highest
priority.
It is unaffected by any mask or Interrupt Enable.
It is the highest priority interrupt.
continued…