Generation of Processor
Generation of Processor
8085
8086
80186
80286
80386
80486
80586
PENTIUM 2
P3
P4
DUAL CORE, CORE TO DUO, QUAD CORE,
C I3 , C I5,C I7
BASIC COMPUTING SYSTEM
BASIC COMPUTING SYSTEM
HLL - HIGH LEVEL LANGUAGE.
a=b+c HLL
Micro-
memory ASM - ASSEMBLY LANGUAGE.
processor
ADD B,C ASM
I/O
COMPILER AND ASSEMBLER.
FETCH ,DECODE,EXECUTE.(Inst
Basics of Microprocessor
• Bit : Binary digit 0 or 1
• Nibble : Group of 4 bits eg: 1100
• Byte : Group of 8 bits. Eg: 1010 1111
• Word : Group of 16 bits.
• Binary And hexadecimal
DECIMAL HEXADECIMAL BINARY 8421 method
0 0 0000 why hexa
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
Microprocessor : It is a semiconductor device made up of using LSI
technique which includes ALU , Control unit and register array.
REGISTERS: 16 BITS
STACK POINTER
PROGRAM COUNTER
FFFF
PC addr
4001
Inst 1 4001
IR data Inst 2 4002
ID
0000
• Accumulator (Reg A): It is an 8 bit register, it is the focus of all operations i.e in
an arithmetic or logical operation one data is always present in accumulator,
after the operation result is stored in to the accumulator.
• General purpose registers (Reg B,C,D,E,H,L): These are called general purpose
registers. They can be used individually as 8 bit data registers , they can also
be used in pair to form 16 bit memory register. B-C, D-E and H-L are only
allowed pairs.
• Register W and Z (Temp reg) : These are temporary registers internally used by
microprocessor to store temporary data during the execution of instructions.
• Temporary register : It is just an 8 bit temporary storage used to hold second
operand.
• Flag register : It is an 8 bit register out of which only 5 bits are used to show
status of current result and 3 bits are not used. It is also called as status
register. There are five flags. Carry flag, Parity flag, Auxiliary carry flag, Zero
flag and Sign flag.
Flag Format :
D7 D6 D5 D4 D3 D2 D1 D0
SF ZF X AC X PF X CY
1111 111
A= 1111 1111
B= 0000 0001
1 0000 0000
CY PF
Sign flag:
1000 0011
unsigned signed
Q) Flag register contains data 45, interpret
it’s meaning.
SF ZF XX AC XX PF XX CY
0 1 0 0 0 1 0 1
SF ZF XX AC XX PF XX CY
1 1 0 1 0 1 0 1
SF ZF XX AC XX PF XX CY
1 0 1 0 1 0 1 0
SP
4003 04
4004 03 Stack
4005 02
4006 01
CPU MEMORY
MEMR
IOR IOW
I/O
Operation IO/M RD WR S0 S1
MEMR 0 0 1 0 1
MEMW 0 1 0 1 0
IOR 1 0 1 0 1
IOW 1 1 0 1 0
OPCODE 0 0 1 1 1
FETCH
• Interrupt
IS
R 1
2
3 Interru
Interru pt
4
pt Servic
5
Service Int e
Int 6
routine routin
7
8 e
9
1
0
• AD0 TO AD7 : It is multiplexed address/data bus. It is used for dual
purpose that is to carry lower byte address as well as data. This bus is
bi-directional.
• A8 to A15 : It is unidirectional bus used to carry higher byte address.
• X1 and X2: These pins provide the clock inputs to the microprocessor.
The clock is provided from an external crystal oscillator. Crystal
frequency of 8085 is 6 MHz (6.44 MHz)
• ClkOut: 8085 provides clock inputs to all the peripheral devices through
this pin. This takes care of synchronizing the different components
connected to 8085. It receives the signal from X1 and X2. Clock
frequency of 8085 is 3 MHz (3.22 actual value)
• WR :It is an active low signal that indicates a write operation.
• RD : It is an active low signal that indicates a read operation.
• IO / M This signal is used to distinguish between an IO and a Memory
operation. When the signal is high, it is an IO operation, otherwise it is a
Memory operation.
• READY: This signal is used to synchronize 8085 with slower peripherals.
The microprocessor checks this signal at the beginning of every machine
cycle. If the signal is low, it means that the peripheral is not ready and the
microprocessor will have to remain in a wait state until the signal
becomes high again.
• HOLD and HLDA: These signals are used for Direct Memory Access (DMA).
The DMAC issues a HOLD request to 8085. In response, the
microprocessor relinquishes the control of the buses and acknowledges
the request through the HLDA pin. The DMA transfer ends when the
HOLD request is released.
SOD and SID: The Serial Output Data (SOD) and the Serial Input Data (SID) pins
are responsible for transferring data serially (one bit at a time) to and from the
microprocessor.
Vcc and Vss: 8085 has two power supply signals. Vcc indicates a +5V power
supply while Vss indicates a ground signal.
S1 and S0: These are the control pins which indicate the status of the operation
that the microprocessor performs. They instruct the microprocessor to either
read, write or fetch data.
S1 S0 Status
0 0 Idle
0 1 Write
1 0 Read
1 1 Opcode
fetch
ALE: The Address Latch Enable pin is used for identifying the contents of the
multiplexed bus (AD0-AD7). If the multiplexed bus contains an address, ALE is
high and if the multiplexed bus contains data, ALE is low.
ALE=1, AD0 TO AD7 carries address.
ALE=0, AD0 TO AD7 carries data.
• RESETIN : It is an active low signal that is activated when a manual reset is
applied to 8085. This signal resets 8085. On reset, the PC contains the address
of 0000H.
• Reset Out: This signal is connected to all other peripheral devices. It is used to
reset the entire system once the microprocessor is reset (For example, when
we reboot a PC, we initiate the RESETIN signal. Once the processor receives
this, it sends Reset Out – an output signal to all the components of the PC).
8085 Interrupts:
• Interrupts are external real time events that need an appropriate response. The 8085
microprocessor services the interrupts by executing a set of instructions called as the Interrupt
Service Routine (ISR). When an interrupt occurs, the microprocessor first finishes the current
instruction. It then Pushes the address of the next instruction to the stack and then transfers the
control to the address of the ISR and executes it. We can prevent an interrupt from occurring by
either Masking individual interrupt using SIM instruction or by disabling all the interrupts using
the DI instruction.
• 8085 Microprocessor has two types of interrupts:
• Hardware Interrupts
• Software interrupts
• Hardware Interrupts of 8085: Interrupts that are initiated through hardware pins are known as
hardware interrupts. They are further classified in to maskable and non maskable interrupts.
Maskable interrupts can be ignored or delayed by microprocessor if it is performing some critical
task whereas microprocessor has to respond non maskable interrupts immediately. 8085 has 5
hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
• TRAP: It has the highest priority. It is edge as well as a level triggered. It can neither be masked
nor disabled (non-maskable). It has a fixed address for its ISR. We can say that it points to that
fixed address. Hence, it is known as a vectored interrupt. Its vector address is 0024H.
• RST 7.5: It has the priority lower than TRAP. It is edge triggered. It can be masked as
well as disabled (maskable). It is a vectored interrupt whose address is 003CH.
• RST 6.5: It has the priority lower than RST 7.5. It is level triggered. It can be masked
as well as disabled (maskable). It is a vectored interrupt whose address is 0034H.
• RST 5.5: It has the priority lower than RST 6.5. It is level triggered. It can be masked
as well as disabled (maskable). It is a vectored interrupt whose address is 002CH.
• INTR: It has the lowest priority of all hardware interrupts. It is level triggered. It can
only be disabled, but not masked. It is a non-vectored interrupt.
• The hardware interrupts of 8085 can be summarized in the following table:
INTERRUPT PRIORITY TIRGGER MASKABLE DISABLED VECTORED VECTOR
ADDRESS
TRAP 1 Edge / Level No No Yes 0024H
RST 7.5 2 Edge Yes Yes Yes 003CH
RST 6.5 3 Level Yes Yes Yes 0034H
RST 5.5 4 Level Yes Yes Yes 002CH
INTR 5 Level No Yes No Variable
Software Interrupts of 8085: Interrupts that are initiated through software
(programs) are known as software interrupts. 8085 has 8 software interrupts:
RST 0 to RST 7. The service routines of these interrupts are stored at addresses
which can be found by multiplying the interrupt number by 8 (ISR for RST 1 is
0008H). The list of all the software interrupts and their ISR addresses are as
below: INTERRUPT ISR ADDRESS
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
Q) Explain Instruction cycle , machine cycle and T states
Instruction Cycle: It is the time required by the microprocessor to fetch and execute one complete instruction. The
instruction cycle is in two parts: fetch cycle and execute cycle. Fetch cycle is the time required by the microprocessor to
fetch the instruction (Larger instructions will have longer fetch cycles) and execute cycle is the time required by the
microprocessor to execute the fetched instruction.
Machine Cycle: It is the time required by the microprocessor doing one operation and accessing one byte from the external
memory or I/O module.
T-State: A T-state is one clock cycle of the microprocessor. Can also be called as a sub division of an operation.