WK 3

Chapter 9

8086/8088 Hardware Specifications

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 Objectives
• Describe the functions of all 8086/8088 pins
• Understand DC characteristics and fan out
• Using the clock generator 8284A chip
• Connect buffers and latches to the buses
• Interpret timing diagrams
• Describe wait states and design their circuits
• Explain difference between minimum and
maximum modes of using the 8086/8088
• Introduce the 8087 floating point processor
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 The 8086/8088
• Fairly old microprocessors, but still considered
a good way to introduce the Intel family
• Both microprocessors use 16-bit registers and
20-bit address bus (supporting 1 MB memory),
but:
- The 8086 (1978): 16-bit external data bus
- The 8088 (1979): 8-bit external data bus
• Still used in embedded systems (cost is less
than $1)

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 Maximum mode Minimum mode
 2 Modes: Operation with a
8/9 pins have Math Coprocessor
Different
Basic
Functions
Operation
Depending
On the mode

n budget:
086, Min mode:
I/P Selects
Min/Max Mode
0 Address
1 Data
0 Control & Status
3 Power

9 Total
40 pins available

Use multiplexing

8086 8088
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 DC Pin Characteristics: Voltages
Standard TTL Output and Input Voltage Levels

Vcc 5.0 V
11Logic
Logic
Level
Level

“1”-Level
Noise Margin
Guaranteed Forbidden Accepted
Output Levels Forbidden
Region Input Levels

“0”-Level
00 Logic
Logic Level
Level Noise Margin

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 DC Pin Characteristics: Currents
Fan out for a standard TTL output
How many inputs can an output support?
For the 0 logic Level: (output “sinks” current)

Standard OFF O/P can sink up to

16 mA max
TTL Gate
I/P
0
ON An I/P sources
up to 1.6 mA

0-level Fanout = Maximum number of inputs that the output can support
= 16 mA/1.6 mA = 10
For the 1 logic Level: (output “sources” current)

O/P can source up to If different,

ON 400 A max take the smallest
1 of the two numbers
OFF I/P sinks
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 8088/86 Pin Characteristics: DC
Guaranteed Accepted
Output levels
Output pins Input pins Input levels

-
# * *
#
* = 16 mA for standard 74 TTL * = 1.6 mA for standard 74 TTL
# = 0.40 V for standard 74 TTL # = 40 A for standard 74 TTL
0 level noise margin = 0.8 – 0.45 = 0.35 V (P)
8086/88 p does not strictly comply P but = 0.8 – 0.40 = 0.40 V
with the DC characteristics Standard ’74 TTL (for standard 74 TTL O/P)
Gate
of the TTL family
0 level fan-out to TTL gate = 2  1.6  1 (8086/88 P)
but = 16  1.6 = 10
A processor output can drive: (for standard 74 TTL O/P)
• One Standard 74XX input, or
• One 74SXX input, or
• Five 74LSXX inputs, or +: Current into pin (sink)
Two problems:
• Ten 74ALSXX inputs, or - : Current out of pin (source) - Lower fanout
• Ten 74HCXX inputs - Lower noise margin
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 8088/86 Pin Characteristics: DC
• Input pins are TTL compatible and source(0)/sink(1) only ±10μA
of current (actually better than TTL!)
• Output pins are TTL fully compatible at logic “1”, but have
problems at logic 0:
- A higher maximum logic 0 voltage of 0.45 V (instead of the
TTL standard of 0.4 V)
This reduces logic 0 noise margin from 400 mV to 350 mV…
 be careful with long wiring from output pins
- A lower logic 0 sink current of 2.0 mA (instead of the 16 mA
for the standard 74 TTL)
This reduces fan out capability for standard TTL loads…
 better use 74LS, AL, or HC circuits for interfacing, or
 use buffers

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 The Buses: Address & Data
• Address, A (for memory & I/O)  Data, D
 Control lines  Status, S
Some functions are multiplexed on the same pins to reduce chip pin count
Address Data
AD15-0 Write Cycle
Pins - 86
Latch address
ALE: Latch to a buffer
address o/ps to a buffer 86 88
• For both Ps: Address bus signals
are A0-A19 (20 lines) for 1M byte of
addressing space
• Data bus signals are
- D0-D7 for the 8088
- D0-D15 for the 8086
• The address & data pins
are multiplexed as:
- AD0-AD7 (8088)
- or AD0-AD15 (8086)
• Address/Status pins are MUXed
- A/S for A16-19 (both Ps)
• The ALE O/P signal is used to demultiplex the address/data (AD) bus and
the address/status (A/S) bus.
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 The Status (S) Bus 86: #S0-S2, S3-S7
88: #S0-S2, S3-S6, #SS0
• 86: Address bits A16-A19 & #BHE: muxed with the status bits S3-S7.
Status bits

Indicates status of processor and bus cycle

ALE: Latch address, #BHE o/ps to a buffer

• S3 & S4 indicate which segment

register is used with the current
instruction:

• S5 = the IF (Interrupt flag) bit

in FLAGS
Spare #S0,1,2 are not MUXed. They encode bus status (current bus cycle)
• S6: 0 Available only in the MAX mode for use by a bus controller chip
•Brey: S7:
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 Main Control Signals
1. Signals that are common to both MIN and MAX modes:

• The read output (#RD)

(i.e. RD): indicates a
read operation
Note: The write (#WR)
output: indicates a write
(a MIN/MAX
output)
• The READY input: when
low (= not ready), forces
the processor to enter
a wait state. Facilitates
interfacing the processor # or = Active low signal
to slow memory chips
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 Main Control Signals, Contd.
Two hardware interrupt inputs:
• INTR input: Hardware interrupt
request. Honored only if the IF flag
is set. The p enters an interrupt
ACK cycle by lowering the #INTA
output

The IF flag bit is set (to enable

interrupts) by the STI instruction,
and cleared by CLI

• NMI input: Hardware non-

maskable interrupt request.
Honored regardless of the status
of the IF flag. Uses interrupt vector
2
Test for low
• #TEST input: Example: interfacing
the P with the 8087 math 8087
coprocessor. Checked by the 8086
WAIT instruction that precedes Math
processor #TEST Busy
each floating point instruction. If O/P
Coprocessor
high, the instruction waits till input Synchronizes
signal goes low and then gives FP processor execution to external events
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 Main Control Signals, Contd.
• CLK input: Basic timing clock for the
processor. 1:3 duty cycle
(Get from clock generator chip)
• MN/#MX input: Selects either
Minimum (+ 5V directly) or Maximum
mode (GND)
• #BHE/S7 output (MUXed):
#BHE: (Bus High Enable) Enables
writing to the high byte of the 16-bit
data bus on the 8086
Not on 8088 (it has an 8-bit data bus-
no high byte!)
• RESET input: resets the
microprocessor (to reboot the
computer). Causes the processor to
start executing at address FFFF0H
(Start of last 16 bytes of ROM at the
top of the 1MB memory) after
disabling the INTR input interrupts
(CLR IF flag). Input must be kept
high for at least 50 s. Sampled by
the processor at the + ive clock edge
(Get from clock generator chip)
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 2. The 8/9 Signals that depend on mode: Their Min Mode States
For the processor to operate in the minimum mode, connect MN/#MX
input directly to +5V. Their min mode states:
• M/#IO or IO/#M output: indicates
whether the address on the
address bus is a memory
address (IO/#M = 0) or an I/O
address (IO/#M = 1)
• #WR output: indicates a write
operation.
• #INTA output: interrupt
acknowledgement. Goes low in
response to a hardware interrupt
request applied to the INTR input.
Interrupting device uses it to put
the interrupt vector number on
the data bus. The p reads the
number and identifies the ISR*
• Note: Address on the bus can be either for
ALE (address latch enable)
output: Indicates that the muxed memory or I/O devices. M/#IO signal indicates
AD bus now carries address which one is intended by the current instruction
(memory or I/O). Use to latch
that address to an external circuit *ISR = Interrupt Service Routine
before the processor removes it!.
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 Minimum Mode Signals, Contd.
For the processor to operate in the minimum mode, connect MN/#MX
input directly to +5V.
• DT/#R output: indicates if the data bus
is transmitting (outputing) data (=1) or
receiving (inputting) data (=0). Use to
control external bidirectional buffers
connected to the data bus.
• #DEN output: (data bus enable). Active
when AD bus carries data not address
Use to activate external data buffers.
• HOLD input: Requests a direct memory
access (DMA) from the P. In response,
the P stops execution and places the
data, address, and control buses at
High Z state (floats them).
• HLDA output: Acknowledges that the
processor has entered a hold state in
response to HOLD.
• #SS0 output (8088) : Equivalent P
Bidirectional
to the S0 status output of the Data Buffer
maximum mode. Use with IO/#M
and DT/#R to decode the current Enable Direction
bus cycle (Table 9-5) #DEN DT/#R

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 Multiprocessor System

Clock
Generator

Sync
Xtal

Clock
Generator

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 2. The 8/9 Signals that depend on mode: Their Max Mode States
For the processor to operate in the minimum mode, connect MN/#MX
input to ground.
• #S0,#S1,#S2 outputs: Status bits that
encode the type of the current bus cycle,
Used by the 8288 bus controller and the
8087 coprocessor (Table 9-6)
• #RQ/GT0, #RQ/GT1: Bidirectional lines
for requesting and granting access to a
shared bus (Request/Get). For use in
multiprocessor systems. The RG/GT0
line has higher priority
• #LOCK output: Activated for the duration
of P instructions having the LOCK
prefix. Can be used to prevent other
microprocessors from using the system
buses and accessing shared memory or
I/O for the duration of such instructions,
e.g.
LOCK:MOV AL,[SI] Table 9-6
• QS0, QS1 (Queue Status) outputs:
indicate the status of the internal
instruction queue (Table 9-7). For use by
the 8087 coprocessor
to keep in step with
the P.
Table
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 Clock Generator (8284A)
Provides the following functions:
• Generates Clock signals:
- Generates a CLK signal for the 8086/8088
- Provides a CLK sync signal (OSC) for use
by slave processors on a multiprocessor
8086/8088 systems
- Provides a TTL-level peripheral clock signal
(PCLK)
• Provides synchronization for external
input signals to the processor:
– The RESET input
– The READY input for wait state generation

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 Clock Generator (8284A): Signals
Clocks & Clock Synchronization Signals
• X1 and X2: Crystal Oscillator pins. Connect a crystal
of the correct frequency between these two terminals
to generate the clock signal.
• EFI: External frequency input. Signal can be used as
the clocking source to the 8284A instead of the
crystal oscillator.
• F/#C input: Selects external EFI input (1) or the Crystal
crystal oscillator (0) as the clocking source for the
8284A
• CLK output: The clock signal produced for
connecting to the CLK input on the 8086/8088.
At 1/3 rd of the crystal or EFI input frequency with
1:3 duty cycle: fclock = fxtal/3 = fEFI/3
• OSC: Oscillator output. Same frequency as crystal or
EFI. Connect to EFIs on other 8284As in
multiprocessor systems (synchronized clocks)
fosc = fxtal= fEFI
• PCLK output: peripheral clock signal at 1/6 th of the OSC:
EFI To other Ps
crystal or EFI input frequency (1/2 clock freq) with 1:2
duty cycle. Use to drive peripheral equipment in the XTAL PCLK
system fpclk = fxtal/6 = fEFI/6 3 2 to Per
or EFI
• CSYNC input: Clock synchronization input. Should CLK
be used if EFI is used, otherwise must be grounded. to P
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 Clock Generator (8284A): Signals
RESET Signals
• #RES Reset input: Active low. Usually
connected to an RC circuit to provide
automatic reset at power on.
• RESET output: Synchronized to Clk. Connect
to the 8086/8088 RESET input.

READY Signals
• #AEN1 and #AEN2 address enable inputs:
Used with RDY1 and RDY2 inputs to generate
the READY output. The READY output is
connected to the READY input on the
8086/8088 P to control memory wait states.
To P
• #ASYNC input: for READY output
synchronization. Selects 1 or 2 stages of
synchronization for the RDY1 and RDY2
inputs.

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 Clock Generator (8284A): Block Diagram
• Starts 4 clock pulses max after power up
• Must be kept High for at least 50 s
Hysteresis to avoid
RESET

Schmitt trigger
jitter due to slowly
Switch/RC circuit varying inputs

Active High,
Synchronize to P
Crystal with – ive clock edge Inverting buffer
CLOCK & Sync

Select clocking source Use as EFI in

Multiprocessor
systems
Select Crystal Osc
or EFI 3 2
Peripheral
External Frequency I/P Clock. f = 1/6th
of crystal or EFI
Frequency,
Synchronize clock if EFI is used with multiprocessor systems 1:2 duty cycle
READY

To processor
CLK input.
f = 1/3rd of
crystal or EFI
Frequency,
1:3 duty cycle

0 = 2 stages, 1 = 1 stage of synchronization

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 Typical Application of the 8284A for clock and Reset signal generation

frequency, f f/3

2.5 MHz
PCLK
Grounded when f/6
Xtal Osc is used
OSC 15 MHz
f
RESET
R

Synced
To CLK

C
RC circuit for
Manual automatic Reset on power up 50 s Effective
Reset RC time constant large enough Minimum Digital
push button for 50 s min Reset pulse #RES Input
Switch at worst trigger conditions (1.05
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 Bus Demultiplexing and Buffering
• Demultiplexing:
The address/data and address/status buses are
multiplexed to reduce the device pin count. These
buses must be demultiplexed (separated) to obtain
the signals required for interfacing other circuits to
the P
– Use the ALE output from the microprocessor to latch the
address/status information that appear briefly on the
multiplexed bus
– This makes the latched address information available for
long enough time for correct interfacing, e.g. to memory
• Buffering:
Fan out is limited, so output signals should be
buffered in large systems
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 Demultiplexing the 8088 Processor

Using the ALE signal to Demultiplex:

-The Address lines A0-7
from the AD0-7 muxed bus
-The A16-19 lines from the
A16/S3-A19/S6 muxed bus
20-bit

Not
Muxed
Data
Latch (Transparent)
Delay
Demuxed
Latch Octal D-type
A0-A7
I/P Transparent Latch
Output
Enable (not edge triggered
Memory write cycle for the 8088
(non-muxed line are not shown)
Data and address lines must remain
valid and stable for the duration of the cycle
74373 is an Octal D-type transparent
Latch with 3-state outputs
Use as data bus, with #DEN active
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Demultiplexing the
8086 Processor
Address/Data bus

20-bit

16-bit

with
#DEN active

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 D  O/P
Transparency

Last O/P
Maintained
(latched)
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 Buffering
Since the microprocessor output pins provide minimum drive
current at the 0 logic level, buffering is often needed if more
TTL loads are connected to any bus signal: Consider 3 types
of signals
• For demuxed signals: Latches used for demuxing, e.g. ‘373,
can also provide the buffering for the demuxed lines:So, Fan out = ?
– 0-level output can sink up to 32 mA (20 x 1.6 mA loads) Which case
– 1-Level output can source up to 5.2 mA (1 load = 40 A) sets the limit?
• For non-demuxed unidirectional (always output) address and
control signals (e.g. A8-15 on the 8088), buffering is required-
often using the 74ALS244 (unidirectional) buffer.
• For non-demuxed bidirectional data signals (pin used for both
in and out), buffering is often accomplished with the 74ALS245
bidirectional bus buffer
Caution: Buffering introduces a small delay in the buffered
signals. This is acceptable unless memory or I/O devices
operate close to the maximum bus speed
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 Fully DeMuxed
and buffered 8088
Non-DeMuxed
Address Lines
(unidirectional-
Always O/Ps)
 244 Buffer
74244 is an Octal Buffer
with 3-state outputs
Feature Not utilized!
DeMuxed
Address Lines
(unidirectional-
Always O/Ps) A B isolation
Latch provides with G = 1
the buffering
Non-Demuxed
Bidirectional
Data Lines
74245 is an Octal Bus  245 Buffer
Transceiver with 3-state outputs
Enable external buffers DIR Direction
Feature utilized! 1: AB
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ABReserved.
 Fully DeMuxed and buffered 8086

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 (Not
Transceivers)

Use to determine
Fanout

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Reserved.
 Bus Timing
Timing in General
• A data transfer operation to/from
Clock
the P occupies at least one Cycle
bus cycle
• Each bus cycle consists of
4 clock cycles, T1, T2, T3, T4,
each of period T
• With 5 MHz processor clock:

- T = 1/5 MHz = 0.2 s

- Bus cycle = 4 T = 0.8 s
- Max rate for memory and I/O
transactions = 1/0.8 = 1.25 M
operations per sec (Fetch speed).
- Processor executes
2.5 Million Instructions per sec
(MIPS) (Execute speed)  Fetch is slower than execute. Effect on pipelining?
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 Bus Timing in General, Contd.
• T1: Note: #RD,#WR,#INTA
- Address is emitted from the Processor are all inactive high during T1
- Control signals such as ALE, DT/#R, IO/#M, etc. are also initiated
• T2
- Used primarily for changing Clock Cycle
the direction of the AD bus
TW T3 T4
during read operations ( then )
- Read or write controls are setup,
Read Data Read Data
e.g. #DEN, #RD (#INTA) or #WR Check READY
(Normal) (with Wait)
* If a Write operation, Data to be written is put on the bus for the external device to take
* If a Read operation, AD bus is floated, so external device can put the read data on it
• T3 & T4:
Actual Data transfers occur during T3 & T4.
- In Read operations, “Data In” on the data bus is normally strobed into the processor at
the start of T4
- In Write operations, “Data out” on the bus is strobed into the external device at the
trailing edge of the #WR signal
• Wait States: If addressed device is too slow to allow normal data transfer, it sets
READY input low (NOT READY)
* The processor samples the READY input at the end of T2. If found low, T3 is
considered a “Wait'' state (TW). Ready is checked again at the middle of that wait state.
If high, it is followed by proper T3 and T4. If low (not ready), the next clock cycle is
considered
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Timing in General: Read & Write with waits
WK 5 Read Cycle with 1 TW Write Cycle with 1 TW
X X
TW TW

Latch Sample the READY I/P Latch

Address Address
Muxed
Lines

P strobes data in
HiZ

, #INTA

Data
IN
Buffer OUT
Direction

Enable Address O/P Data Address O/P Data

Data
Buffers
WR
Note: #RD,#WR,#INTA Device strobes data in

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 Bus Timing, Contd.
Basic Data Read Timing
Timing for a basic Read cycle

• Can be for either memory or I/O

On the 8088:
- For memory, IO/#M = 0 P strobes
- For I/O: IO/#M = 1 Also DT/#R = 0
data in

To Device

Bus Or I/O Device

P floats bus (HiZ)

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Detailed Memory READ Timing for the 8088 Standard Bus Cycle = 4T, No Wait States

t=0 Start of
T4

Valid Address
A15-A8 Not Muxed

A19-A16
Muxed

2. Latch/Buffer
Delay Time
Latch
1. Valid Address READY Timing
MUXed
Delay Time Address Lines Assume
3T for the processor No Waits Required
To get data from memory
3. Setup P strobes
Maximum allowed memory Max Memory Time data in Hold Time
access time Access Time
A7-A0 Muxed

Read

Data Bus Direction: In

Enable Data bus

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 READ Timing Budget: 8088, 5MHz Clock
• It takes the processor about 3 clock cycles (3T = 3 x 200 = 600
ns with a 5 MHz clock) to take-in the memory data
• Not all this time is available for the memory device to retrieve
the data and put it on the bus, there is: (See Fig. 9-12)
Incurred 1. Address Valid Delay, TCLAV = 110 ns max
Delays 2. Delay in address latch/buffer and decoders  40
ns
Required
3. Data-in Setup time (required), TDVCL = 30 ns
• Maximum allowed memory access time to operate without waits
= 3 x 200 – (110+40+30) = 420 ns
• If memory has a larger access time, it needs to request wait
states from the processor using the READY input
• #RD signal should be wide enough, TRLRH = 325 ns,
as there may be hold time requirements for the Data-In.
#RD signal is extended with the insertion of wait states
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 INTA Read Timing, 8088
Similar to a memory or I/O read cycle, with #INTA replacing #RD

3. Interrupting device sees this 4. Processor latches in

and puts a byte-long pointer to vector pointer from the
1. Interrupting device Interrupt Vector data bus
Raises INTR on the data bus

2. Processor floats the AD7-AD0 Pointer to Interrupt

bus and Acknowledges the Vector. Supplied by
Interrupt by lowering #INTA
the interrupting device

Controls
for a READ
operation

Upon accepting a hardware interrupt request from a device (on INTR), the processor
acknowledges this to the device and initiates an #INTA read cycle for the 1-byte interrupt
number which the processor reads and uses as a pointer to the interrupt service routine
to be executed
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 Bus Timing
Basic Data Write Timing
Timing for a basic write cycle

• Can be for either memory or I/O

On the 8088:
- For memory, IO/#M = 0
- For I/O: IO/#M = 1
Also DT/#R = 1

Device
strobes data in

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 Detailed Write Timing for the 8088

Also DT/#R = 1

3 parts
of the address

Data should
1. Address established remain
2. Processor puts data on data bus valid for 88 ns
after #WR rise

Enable Data bus

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 READY and Wait States: 5 MHz Clock
• If the memory or I/O device is too slow to use the standard
4T read cycle (access time > 420 ns) , wait states must be
inserted into the cycle by using the READY input to the
processor
• Wait states are additional clock cycles that increase the
length of access time allowed for memory or I/O devices
• Wait states are inserted between the standard T2 and T3
cycles
• Wait time is inserted as whole clock cycles: i.e. if access
time = 430 ns  insert 1 complete wait state of 200 ns!
• Inserting n wait states increase the maximum allowed
access time from the normal typical value of 420 ns (with no
waits) to 420 + n 200 ns
• The READY signal is sampled by the microprocessor at the
start of T3 and again at the middle of each wait state.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Detailed Ready Timing
‘Ready’
(Tw)
Sampling

Sample Then
at end Sample
of T2 at middle
35 ns of each TW

RDY
Input to 8284A
0 ns
8 ns
Inactive
(Not Ready)
READY
Output from 8284A
30 ns
(Input to 8086)
Active
(Ready)
118 ns
Internal Sync circuits
In the 8284A ensure that
READY output to processor meets the above timing requirements

0: 2 stages, 1: 1 stage of sync

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 #RD gated by the
Generation of 0-7 wait states RD
(Gated) for the memory device
Using one of the two RDY
Requiring wait states
inputs to the 8284A
1st bus cycle state
Jumper
Selects
# of Wait
States
RDY1
Serial I/P
0W 1 Synchronous
QA
Shift rights
1W 1
QB 8-bit Shift Register

QC
2W OR
1
…
CLR Shift Register
RD During T1
(Gated)

CLR shift Register:

Processor
No Shifting
Effectively,
RDY1 = (Selected Q + RD)
(when the slow memory
device is accessed)
Note: #RD is extended with Note: #RD,#WR,#INTA
the addition of wait states are all inactive high during T1
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Minimum and Maximum Modes
• MN/#MX input on 8088/8086 selects min (0V) or max (+V)
mode
• Minimum mode is the least expensive way to configure a 8086/8088 system:
– Bus control signals are generated directly by processor
– Good backward compatibility with earlier 8085A 8 bit processor
- Same control signals
- Support same peripherals
• Maximum mode provides greater versatility at higher cost.
– New control signals introduced to support 8087 coprocessor (e.g. QS0 &QS1)
and multiprocessor operation (e.g. #RQ/GT0 & RQ/GT1)
– Control signals omitted must be externally generated using an external
bus controller, e.g. 8288. The controller decodes those control signals
from the now compressed form of 3 control bits (#S0,#S1,#S2)
– Can be used with the 8087 math coprocessor
– Can be used with multiprocessor systems
• Maximum mode no longer supported since 80286

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Use of 8086 in the Minimum Mode
Microprocessor-based System

Basic control signals are directly available from processor

Address
Demultiplexing

Address
Decoding
Direction
Bidirectional
AD Bus Data Buffering
Prevents
Transceiver from
driving the AD bus
when interrupt
controller
Is using it
RAM ROM I/O
Interrupt
Here the Interrupt controller Handling Several Interrupt
accesses the AD bus before Requests
demultiplexing
Brey: - careful!
The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 8086 Maximum Mode
8288 Bus Controller chip: Necessary in this mode.
Generates essential control signals not provided directly by P
form the S0-S2 O/Ps

Control signals are more specific, e.g. separate lines for

M and I/O operations

8086 Chipset
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 8288 Bus Controller

bus
20-Pin Chip

Familiar 8088/8086
Outputs
More specific Outputs,
Selects Replace #RD, #WR,
Mode: M/#IO
1. I/O Bus
2. System Bus
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 8288 Bus Controller: Pin Functions
• S0, S1, S2 inputs: Status bus bits • #IORC output: Input/Output read
from processor. Decoded by the 8288 control signal.
to produce the normal control signals • #IOWC output: Input/Output write
• CLK input: From the 8284A clock control signal.
generator • #AIOWC output: Advanced
• ALE output: Address latch enable Input/Output control signal.
output for demuxing address/data • #MRDC output: Memory read control
• DEN output: Data bus enable output signal.
to enable data bus buffer. Note • #MWTC output: Memory write control
opposite polarity to #DEN output in signal.
minimum mode.
• #AMWT output: Advanced Memory
• DT/#R output: Data transmit/Receive write control signal.
output to control direction of the
bi directional data bus. • MCE/#PDEN output: Master
• cascade/Peripheral data output.
#INTA output: Acknowledge a Selects cascade operation if IOB=0 or
hardware interrupt applied to the enables I/O bus transceivers if
INTR input of the processor. IOB=5V
• IOB input: I/O bus mode input.
Selects operation in either I/O bus
mode or system bus mode.
• #AEN input: Address Enable input.
Used by the 8288 to enable memory Effective only in the system bus mode
control signals. Supplied by a bus
arbiter in a multiprocessor system
• CEN input: Control Enable input.
Enables the generation of command
outputs from the 8288.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 The Math Coprocessor: Chapter 14
(Numeric Data Processor (NDP))
• The 8086 performs integer math operations
• Floating point operations are needed, e.g. for Sqrt (X),
sin (x), etc.
• These are complex math operations that require large
registers, complex circuits, and large areas on the chip
• A general data processor avoids this much burden
and delegates such operations to a processor
designed specifically for this purpose -
e.g. math coprocessor (8087) for the 8086
• The 8086 and the 8087 coprocessors operate in
parallel and share the busses and memory resources
• The 8086 marks floating point operations as ESC
instructions, will ignore them and 8087 will pick them
up and execute them
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 The 8087 Coprocessor: Organization
• CU and NEU units
• Eight 80-bit FP Registers
• Supports 68 FP (ESC)
instructions
• Speeds up 8086
performance on FP
operations by a factor
of 50-100 time Top of
the data
• 8087 Tracks activities Stack

of the 8086 by monitrng: 8086 ST(0)

- Bus status (S0-S2 bits)

- Queue status (QS0,1)
#Test Busy
- Instruction being
A stack of 8 x 80-bit
fetched (to check if its an
ESC instruction) FP Registers
ST(7)
• Synchronize with WAIT
using the BUSY-#TEST
signals
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 8086 Maximum mode outputs for NDP Connection
• Bus Status Outputs S0-S2: Table 9-7
Status bits that encode the type
of the current bus cycle
• Bus Request/Grant Outputs RQ0/GT0:
Allow 8087 to request use of the bus,
e.g. for DMA memory access
• Queue Status Outputs QS1,QS0:
- For use by coprocessors that receive their instructions via ESC prefix.
- Allow the coprocessor to track the progress of an instruction through the
8086 queue and help it determine when to access the bus for the escape
op-code and operand.
- Indicate the status of the internal instruction queue as given in the table:
QS1 QS0
0 0 Queue is idle
0 1 First byte of opcode from queue
1 0 Queue is empty
1 1 Subsequent byte of opcode from queue
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Inputs common AD Before
with the 8086 Demuxing

Can interrupt
the 8086

The 8086 with an 8087 Coprocessor

80867e is operating in the MAX
Brey: The Intel Microprocessors, mode
© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Synchronization between 8086 & the 8087 Coprocessor

The assembler marks

all FP instructions as
ESC instructions having a
special range of opcodes.
The Coprocessor monitors
the 8086 bus activities and
Intercepts such instructions,
captures them for execution

WAIT instructions
can be used to halt the
8086 to ensure that the
8087 has finished a crucial
step,
e.g. storing a result in
memory.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Programming the 8087
Sequence of FP operations:
1. Operand data is loaded from memory into 8087
registers
2. Do the FP operation in the 8087
3. Store FP results from the 8087 to memory
• FP Instructions use the top of the 80-bit register data stack as the
default operand (needs not be mentioned), e.g.
FLDPI ; loads PI (= ) into the top of the stack
; i.e. into register ST(0)
• When something is put on top of the stack, a stack PUSH occurs
automatically
• When something is removed from the top of the stack, an
automatic stack POP occurs
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Programming the
Define
80387: Example
Double Two 5 x 4-byte array
Word
RAD
(radii)

AREA
;ECX, also used as loop counter
Instructions
Starting with . ST = Stack top which is also ST(0)
F are FP
Instructions
For the 80387

Results in stack
80386 Program after Instruction Execution

Note: 8087 automatically converts Push

Data from integer to FP when
moving it from memory to its data
stack
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