Drain and Transfer characteristics of JFET

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Drain and Transfer characteristics of JFET

September 01, 2020

Drain and transfer Characteristics of JFET:

1) With no external bias:

Circuit diagram for no bias for drain characteristics

Initially external voltage is not applied between gate and the source. It acts as the
short circuit. The current is formed when majority charge carriers move from to
source to drain. So when no external voltage is applied, there is no potential to
attract the majority carries at the drain and thus initially current is zero when input
voltage is zero.
Very small gate source voltage VGS is applied and the JFET acts as a simple resistor.
The drain current ID increases gradually and reaches the knee point. Then it enters
into pinch off region where the drain current ID is almost constant for the increase
in the drain source voltage VDS.

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6/28/23, 10:52 PM Drain and Transfer characteristics of JFET

Output characteristics of JFET with shorted gate

Knee point: Till this knee point the variation of drain current to the drain source
voltage is linear. After this point it looks like a curve.

Pinch off point: Above this point the drain current does not increase even though
the drain source voltage is increased.

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Channel Ohmic region: The region left to the knee point is called channel Ohmic
region. Because in this region JFET acts like an ordinary resistor.
Pinch off or saturation region: In this region the drain current is totally constant
for the increase in the drain source voltage and it enters the saturation region.

Breakdown region: when the drain and source voltage is increased further the
device enters into the breakdown voltage.

2) With external bias:

JFET with external bias to determine drain characteristics

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6/28/23, 10:52 PM Drain and Transfer characteristics of JFET

When the gate source voltage VGS is applied, it is reversely biased. The pinch off
voltage is reached earlier when external bias is applied than when no external bias
is applied.

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Drain characteristics of JFET with external bias DIGITAL ELECTRONICS

The input gate source voltage VGS is increased and kept at constant and the output DIODES
drain source voltage VDS is gradually increased and the output current ID is
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observed. Initially the current increases linearly and after it reaches knee voltage it
enters the saturation region where the current is almost constant. When the EXPLORATORY DATA ANALYSIS(EDA)
applied voltage is increased further breakdown occurs and it enters into the
breakdown region. In Ohmic region it acts as a resistor. FEATURE ENGINEERING

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Transfer Characteristics of JFET:

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Transfer characteristics of JFET

The transfer characteristics can be determined by keeping the drain source voltage
VDS constant, drain current ID is observed by changing the gate source voltage.
So it is observed that when the gate source voltage VGS is increased in the negative
region the drain current ID decreases.

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