8051 MICROCONTROLLER

Introduction
• Microcontrollers are processor chips that generally have memory,
input ports, and output ports within the chip itself.
• Therefore, they can also be called single-chip computers,
computer-on-a-chip, or system-on-a-chip.
• Microcontrollers are used in machine control applications, where
there is no need to change the program.
• Equipments that use microcontrollers include computer printers,
plotters, fax machines, Xerox machines, telephones, automotive
engine control mechanisms, and electronic instruments such as
oscilloscopes, multimeters, planimeters, IC testers, etc.
 Introduction
• The major difference between microprocessors and
microcontrollers is that microcontrollers are comparatively faster
because of reduced external memory accessing.

• Intel’s 8031, 8051, and 8096 and Motorola’s 68HC11 are examples
of microcontrollers.
 DSP processor - Introduction
• DSP processors are processing chips that have flexibility in
hardware and software, to implement signal-processing
algorithms.

• These processors have an extended arithmetic and logic unit for

operation on floating or fixed point number formats.

• Like microcontrollers, DSP processors also have on-chip memory,

I/O ports, A/D converters, and serial ports. They are used in mobile
phones, digital cameras, PBX systems, and smart card readers
 Intel’s MCS 51 series
microcontrollers
• Intel Corporation has many micro-controllers in both 8 bit and 16
bit configuration.

• The 8 bit micro-controllers -in many part numbers -MCS – 51 as the

family name.

• The various MCS – 51 series micro-controllers. For example,

8XC51RD comes with the internal ROM of 64KB while 8XC51FC
comes with only 32KB ROM.
Intel’s 8 bit Micro-controllers

Device Number Data bus width RAM capacity ROM capacity

8031 8 128 bytes Nil

8051 8 128 bytes 4Kbytes

8751H 8 128 bytes 4Kbytes EPROM

8052AH 8 256 bytes 8Kbytes

8752BH 8 256 bytes 8Kbytes EPROM

 Intel’s 8 bit Micro-controllers
• Intel Corporation has many microcontrollers in both 8-bit and 16-
bit configurations.

• The 8-bit microcontrollers are available in many part numbers,

with MCS-51 as the family name.

• For example, 8XC51RD comes with an internal ROM of 64 KB, while

8XC51FC comes with only a 32 KB ROM.

• All the microcontroller chips listed above have the same basic
architecture.
 Intel 8051 Architecture
• The main features -8051chips are
o 8 bit CPU,
o 4Kbytes of on chip Program memory,
o 128 bytes of on chip data RAM,
o 4 ports of 8bit each,
o Two 16 bit timers,
o Full duplex serial port and
o On-chip clock oscillator.
• In addition to the above features, the 8051 provide Boolean
processing; six interrupt capabilities and full-fledged CPU for
control applications.
8051 Architecture
8051 Block Diagram
 8051 Microcontroller - Introduction
• 8051 is an 8 bit micro-controller i.e. data bus within and outside
the chip is 8 bits wide.
• The address bus of the 8051 is 16 bits wide, so it can address
64Kbytes of memory.
• The lower order address bus is multiplexed with the data bus as in
-8085 processors.
• The port0 and port 2 pins of 8051 forms the multiplexed address
and data bus.
8051 Pin details of 8051 DIP IC
 8051 – Pin details
• The 8051 is a 40-pin chip.

• The power supply +VCC and VSS takes two pins and the built-in
clock oscillator requires two pins (–XTAL1 and XTAL2) for
connecting the crystal.

• The four control signals pins of 8051 are PSEN {Program Store
Enable}, ALE, EA(External Access) and RST (Reset).

• RST is an active high reset signal to restart the controller chip

 Pin detail - 8051
• 8051 responds to a RST high input only if the RST is held high for
at least two machine cycles.
• A machine cycle is the period taken by any processor to fetch
and execute one instruction.
• In 8051, the maximum number of clock cycles taken for a
machine cycle is 12.
• So, the RST pin must be high for at least 24 clock periods.
• PSEN, ALE, EA are the signals used in conjunction with the
external memory access of the 8051
 MEMORY ORGANISATION
• In the 8051, the memory is organized logically into program
memory and data memory separately.
• The program memory is read-only type; the data memory is
organized as read–write memory.
• Again, both program and data memories can be within the chip or
outside.
• The Intel 8051 has 128 bytes of RAM and 4 KB of ROM within the
chip.
• The address bus of the 8051 is 16 bits wide. So it can access 64 KB
of memory.
Memory organization of 8051
 MEMORY ORGANISATION
• As the memory is organized separately as program memory and
data memory, the 8051 microcontroller can access 64 KB of
program memory and 64 KB of data memory.
• The user can configure the entire program memory outside the
chip or use 4 KB inside and 60 KB outside the chip.
• The internal data memory is accessed with 8-bit addresses and the
external data memory with 16-bit addresses.
• So the maximum data memory that can be connected to the 8051
system is 64 KB.
 INTERNAL RAM STRUCTURE
• The 8051 has 128 bytes of internal data RAM, which is accessible
as bytes or sometimes as bits.
• The address of the internal RAM starts at 00H and occupies space
up to 7FH. The RAM space is divided into three blocks—the
register banks, the bit-addressable memory, and the scratch pad
memory.
• The 8051 has four register banks of eight registers each, with
addresses from 00H to 1FH. In assembly language, they are
addressed by the names R0–R7.
 INTERNAL RAM STRUCTURE:
1F R7 7F
1E R6
1D R5
1C R4
BANK 3
1B R3
1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
14 R4
BANK2
13 R3
12 R2
11 R1
10 R0
0F R7 2F 7F 78
0E R6 2E 77 70
0D R5 2D 6F 68
0C R4 2C 67 60
BANK1
0B R3 2B 5F 58
0A R2 2A 57 50
09 R1 29 4F 48
08 R0 28 47 40
07 R7 27 3F 38
06 R6 26 37 30
05 R5 25 2F 28
04 R4 24 27 20
BANK 0
03 R3 23 1F 18
02 R2 22 17 10
01 R1 21 0F 08
00 R0 20 07 00 30

register banks bit-addressable memory scratch pad memory.

 Internal RAM Structure

• The register banks are identified with 2 bits in the processor status word.

• The PSW has two bits for identifying the register bank, i.e., 00 represents bank
0, 01 represents bank 1, 10 represents bank 2, and 11 represents bank 3.

• In the 8051, bitwise operations are also possible with special instructions using
the bit addresses. The bit-addressable memory is both bit-addressable (from
00H to 7FH) and byte-addressable (from 20H to 2FH). Bit operations are helpful
in many control algorithms.

• Using general-purpose scratch pad memory, programmers can read and write
data at any time for any purpose. This memory ranges from the byte address
30H to the address 7FH.
 SPECIAL FUNCTION REGISTERS
(SFRs)
• SFR, which occupies upper 128 bytes of internal memory are the
registers, that control the entire processor
• They can e accessed by DIRECT addressing.
• The registers available in the 8051 are as follows :
 LIST OF REGISTERS
• Accumulators - A and B
• Process Status Word - PSW
• I/O port registers - P0, P1, P2, P3
• Data pointers - DPH and DPL
• Serial data buffer register - SBUF
• Stack pointer - SP
• Timer registers - TH0, TH1 and TL0, TL1
• Timer Control Registers - TCON, TMOD
• Power and Port control - PCON, SCON
• Interrupt Control Registers - IP, IE.
 Special Function Registers
• Programmers should not use the addresses in the range 80H to
FFH (other than SFR) as it is used by INTEL CORPORATION for
expansion functions of 8051.

• The 8051 has two accumulators -A register and B register.

• The register B forms the accumulator for multiplication and

division instructions and for other instructions it can be accessed
as a general purpose register.
 Special Function Registers
• The stack in the 8051 is organized within the internal RAM area.
• The stack pointer is eight bits wide and has to be initialized with an
address in the RAM area.
• When the 8051 is reset, the stack pointer is by default set to 07H.
• The stack pointer is incremented before storing a data in the stack.
• Similarly, while reading data from the stack, the data is read first
and then the stack pointer is decremented.
Special Function Registers of 8051
Direct Addressed Memory Address
Special Function Register
(SFR)
80 P0
81 SP
82 DPL
83 DPH
87 TCON
88 TMOD
89 TL0
8A TL1
8B TH0
8C TH1
90 P1
98 SCON
99 SBUF
A0 P2
A8 IE
B0 P3
B8 IP
D0 PSW
E0 ACC
F0 B
 Processor Status Word
• The PSW contains all the flags of the 8051 and is eight bits wide.
• The PSW is accessible fully as an 8-bit register, with the address
D0H.
• The bit pattern of this flag register is
• Parity bit (P)
– It is set to 1 if the accumulator contains an odd number of 1s, after an
arithmetic or logical operation.
• Overflow flag (OV)
– This flag is set during ALU operations, to indicate overflow in the result.
It is set to 1 if there is a carry out of either the D7 bit or the D6 bit of
the accumulator. Overflow flag is set when arithmetic operations such
as add and subtract result in sign conflict.
• The conditions under which the OV flag is set are as follows:
– Positive + Positive = Negative
– Negative + Negative = Positive
– Positive – Negative = Negative
– Negative – Positive = Positive
Register bank Select Bits (RS0 & RS1)

• These bits are user-programmable.

• They can be set by the programmer to point to the correct register
banks.
• The register bank selection in the programs can be changed using
these two bits.
• General-purpose flag (F0)
– This is a user-programmable flag; the user can program and
store any bit of his/her choice in this flag, using the bit address.
Register bank selection using
Processor status word

RS1 RS0 Selected Bank Address Range

0 0 Bank 0 00h to 07h
0 1 Bank 1 08h to 0Fh
1 0 Bank 2 10h to 17h
1 1 Bank 3 18h to 1Fh
 Flag Description
• Auxiliary carry flag (AC)
– It is used in association with BCD arithmetic. This flag is set when there is a
carry out of the D3 bit of the accumulator.
• Carry flag (CY)
– This flag is used to indicate the carry generated after arithmetic operations.
It can also be used as an accumulator, to store one of the data bits for bit-
related Boolean instructions.
• The 8051 supports bit manipulation instructions.
• This means that in addition to the byte operations, bit operations
can also be done using bit data.
• For this purpose, the contents of the PSW are bit-addressable.
 Bit addressable registers
• 8051 supports bit manipulation instructions. -bit operations can
also be done using bit data.

• Similarly, the accumulator and B register contents -bit addressable.

• The bit addresses of all the bits of the accumulator and B registers
are given as
Bit addresses of Accumulator & B
register bits
Accumul ACC. ACC. ACC. ACC. ACC. ACC. ACC. ACC.
ator bits 7 6 5 4 3 2 1 0
Bit
Address
E7 E6 E5 E4 E3 E2 E1 E0
Upon 0 0 0 0 0 0 0 0
Reset

B register B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

bits

Bit
Address
F7 F6 F5 F4 F3 F2 F1 F0
Upon 0 0 0 0 0 0 0 0
Reset
 POWER CONTROL IN 8051
• The 8051 has various power control modes, which are used to
control the power consumed by the microcontroller chip.

• Some of these modes let the microcontroller go into a ‘sleep’

mode, which makes it consume lesser power than during normal
operation.

• The power control modes are selected through the Special

Function Register PCON.
Bit Pattern for PCON register
Bit Name Explanation of Function

7 SMOD Serial port Baud rate set bit

6 - Reserved

5 - Reserved

4 - Reserved

3 GF1 General Purpose Flag 1

2 GF0 General Purpose Flag 0

1 PD Power Down mode set bit

0 IPL Idle Mode Set bit

 IDLE MODE
• The micro-controller enters the idle mode whenever the PCON.0
bit is set to 1.
• In the idle mode, the clock pulses applied to the CPU are masked
while all other units like interrupt controller etc., will be kept
active.
• The contents of the CPU are not affected in this idle mode.
• The processor can be revoked -idle mode -hardware interrupt or by
giving a hardware reset signal.
• These two actions - reset PCON.0 and the processor execution -
resumed to the instruction following the instruction that set idle
mode.
 POWER DOWN MODE
• The Power down mode is initiated by making PCON.1 bit to 1.

• In this mode, the clock generator -switched off and only the
internal memory is active.

• the supply voltage Vcc can be reduced to 2V and the power

consumption –reduced.

• Only way to revoke the processor from power down mode -reset
the system.
 THE STACK OPERATION
• In the 8051, the stack is configured as a series of memory locations
following the Last-In First-Out (LIFO) pattern.

• In general, the stack is initialized in the internal RAM area. Any 8-

bit data can be stored and retrieved from the stack using PUSH and
POP instructions, with the help of the stack pointer.

• The stack pointer (SP) is an 8-bit register within the SFR area, with
the address 81H.
 THE STACK OPERATION
• This register can hold one 8-bit address at a time, which is actually
the memory location at top of the stack.
• A push operation in the 8051 is used to store an 8-bit data in the
stack.
• The PUSH instruction first increments the value of SP and then
stores the data mentioned in the instruction in the memory
location pointed to by SP.
• Similarly, the POP instruction stores the value from the top of the
stack in the register mentioned in the instruction and then
decrements the value of SP.
 THE STACK OPERATION
• The stack pointer is initialized to the value 07H when the 8051
microcontroller is reset.

• The other instructions of the 8051 that affect the stack and the
stack pointer are ACALL, LCALL, RET, and RETI.

• The stack pointer can be initialized to any internal RAM address by

the programmer, by writing the required address in the SP SFR
address 81H.
 Immediate Addressing Mode
• The data to be manipulated is directly given in the instruction
itself.
• The data is preceded by a # symbol.
• E.g. ADD A, #80h.
• This instruction adds the data 80h to the contents of the
accumulator and the result is stored in the accumulator itself.
• This addressing mode will be used when the data for the
arithmetic and logical operation is needed only once and is a
constant.
 Register Direct Addressing
• The register, that contains the data to be manipulated, is specified
in the instruction.
E.g. ADD A, R0.
• This instruction will add the contents stored in register R0 with the
accumulator contents and store the result in accumulator.
• The registers A, DPTR and R0 to R7 are used in Register direct
addressing.
• This addressing mode uses temporary registers which hold the data
for the operation.
 Memory Direct Addressing
• The memory address that contains the data to be operated is specified here in
the instruction.
• E.g. ADD A, 74h.
• This instruction adds the data in accumulator with that stored in memory
address 74h.
• All internal RAM addresses including that of special function registers can be
used in memory direct addressing instructions.
• This addressing mode is used when the data stored in memory is to be used in
arithmetic and logical instructions.
• The data in memory used in the direct addressing can be changed at any other
point in the program.
 Memory Indirect Addressing
• The register, which contains the actual memory address
of the data, is specified in the instruction.

• The register specified is preceded by @ symbol in

assembly language format. E.g. ADD A, @R0.

• The value stored in the register R0 is now the address of

the memory location of the data to be fetched.
 Memory Indirect Addressing
• From this memory location, the data is fetched and the instruction
is executed.

• The data pointer register (DPTR) is used to access the data in the
external memory with 16-bit addresses.

• The indirect addressing mode is very much useful for accessing

data which are continuously stored in memory and accessed
consecutively in program.
 Indexed Addressing
• In this type of addressing, the instruction consists of two parts - a
base address and an offset.
• This type of addressing is useful in relative memory accessing and
relative jumping.
• The base address is stored in data pointer (DPTR) or any other
register.
• The offset value is stored in Accumulator e.g. MOVC A, @A+DPTR.
 Indexed Addressing
• This instruction adds the contents of the accumulator with the
contents of the data pointer and the result forms the actual
address of the data from where it is fetched. This data is moved on
to the accumulator.

• The indexed addressing mode is useful in accessing data structures

similar to lookup tables. The base address will hold the address of
the starting point of the table and the offset will point the
particular entry in the table.
 INSTRUCTION SET OF 8051
• Instruction supported by 8051 can be classified into
different types depending upon their operational
functions.

• The instruction set classification is as followed.

 Data Transfer Instructions
• As the name indicates, instructions in this set are used to transfer
data.
• The data can be transferred from or to external RAM or within the
internal memory itself.
• The instruction MOV is used to transfer the data between internal
registers/memory.
• The general format is
– MOV Reg destination, Reg source.
• The source and destination registers within the 8051 chip can be
addressed by any one of the addressing modes except indexed
addressing mode discussed earlier.
 Data Transfer Instructions
Addressing Modes

Mnemonic Operation
Direct Indirect Register Immediate

MOV A,
A = <src> √ √ √ √
<src>
MOV <dest>,
<dest> = A √ √ √
A
MOV <dest>,
<dest> = <src> √ √ √ √
<src>

MOV DPTR, DPTR = 16-bit

√
# data 16 immediate data

INC SP:
PUSH <src> √
MOV “@SP”, <scr>

MOV <dest>, “@SP”:

POP <dest> √
DEC SP
 Data Transfer Instructions
XCH A, ACC and <byte> Exchange
√ √ √
<byte> Data

XCHD A, ACC and @ Ri exchange

√
@Ri low nibbles

Copy 8 bit data from the

MOVX A, external RAM location
Only Indirect Addressing mode
@Ri pointed to by Ri to register
A

Copy 8-bit data from

MOVX @ Ri,
register A to the external Only Indirect Addressing mode
A
RAM location pointed to
by Ri
 Data Transfer Instructions
Copy 8-bit data from the
MOVX A, @
external RAM location Only Indirect Addressing mode
DPTR
pointed to by the 16-bit
DPTR to register A

Copy 8-bit data from

MOVX @
register A to the external Only Indirect Addressing mode
DPTR, A
RAM location pointed to by
the 16-bit DPTR

MOVC A, Read Program Memory at Only Indirect Addressing mode

@A + DPTR (A + DPTR)

MOVC A, Read Program Memory at Only Indirect Addressing mode

@A + PC (A + PC)
 Data Transfer Instructions
• The instructions with the mnemonic MOVX is used to access data
from external memory locations using indirect addressing only. –
• MOVX instruction must use Accumulator (A) register as -
destination or source and the other is indirectly accessed external
memory.
• MOVX can be used -8 bit external memory address and 16 bit
external memory address. It can be noted that the external
memory -interfaced with 8051 with either 8 bit address or 16 bit
address.
 Data Transfer Instructions
• If the 8 bit address is used-internal register (any location in Internal
RAM) -hold the address of the memory. If 16 bit address is used-
Data Pointer (DPTR) is used to hold the address.

• The instructions MOVC A,@A+DPTR and MOVC A,@A+PC are the

two instructions meaning MOVE CODE MEMORY and are used to
transfer data from program memory using indexed addressing
 Data Transfer Instructions
• The program memory addressing using MOVC instruction needs 16
bit address. So, the Data Pointer register (DPTR) and Program
Counter (PC) -base registers -instructions.

• Data can only be read from the program memory and not written
into because the program memory is generally ROM.

• PUSH instruction is used to copy data in any internal RAM location

to the stack
 Data Transfer Instructions
• The POP instruction is used to copy data from the top of the stack
to the RAM location specified in the instruction.

• XCHD is used to transfer only the lower-order nibble between the

accumulator and the indirectly addressed internal RAM.

• XCH is used to exchange the contents of the accumulator and a

register or the internal memory of the 8051.
 Arithmetic Instructions
• These instructions are used to do arithmetic operations.

• The common arithmetic operations like addition, subtraction,

multiplication and division are possible with 8051.

• All the data used in arithmetic instructions must be available inside

the controller i.e. in the internal RAM area only.
 Arithmetic Instructions
• ADD instruction is used to add any 8 bit data with Accumulator and
the result is stored in Accumulator (A) register. The carry generated
if any is stored in Carry flag of the processor status word.

• The ADDC instruction is also used to add any 8 bit data with
Accumulator along with Carry bit.
 Arithmetic Instructions
• The SUBB instruction -subtract contents of a register from the
Accumulator content and during this subtraction, the Carry bit is
also subtracted from the accumulator.

• For ADD and SUB instructions, one of the data must be in

Accumulator and the other data - in any direct addressed or
indirect addressed internal memory location or can be an
immediate data.
 Arithmetic Instructions
• In addition to - ADD, ADDC and SUBB instructions in 8085, -have
instructions MUL and DIV.

• The register B is exclusively used for these two instructions. The

operands should be stored in the registers A and B for the MUL and
DIV instructions.
 Arithmetic Instructions
• The MUL instruction multiplies the contents of A and B registers
and stores the 16 bit result in the combined A and B registers.

• The lower order byte -result is stored in A register and the higher
order byte - stored in B register.

• The DIV instruction upon execution will divide the contents of A

register by the contents of B register.
 Arithmetic Instructions
• The quotient of the result - stored in A register and the remainder
is stored in B register.

• A division by 0 i.e. 0 in the B register before executing DIV AB will

result in the overflow flag (OV) set to 1.

• DA A instruction -to convert binary sum obtained after adding two

BCD numbers into BCD number.
 Arithmetic Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate
ADD A, A=A+
√ √ √ √
<byte> <byte>
ADDC A=A+
√ √ √ √
A,<byte> <byte>+C
SUBB A, A=A–
√ √ √ √
<byte> <byte>–C
INC A A=A+1 Accumulator Only
DEC A A=A-1 Accumulator Only
<byte> =
DEC <byte> √ √ √ √
<byte>– 1
MUL AB B:A= B  A Accumulator Only
A = Int
[A/B]
DIV AB Accumulator Only
B = Mod
[A/B]
Decimal
DA A Adjust Accumulator Only
Accumulator
 Logical Instructions
• In addition to logical AND, OR and XRL operation, 8051 has
additional instructions - CLR, CPL. All the data for the logical
instructions -available in the internal RAM only.

• The instruction CLR A -to clear the contents of A register, CPL is

used to complement or logically invert the contents of the A
register and SWAP - to swap the nibbles of A register.

• 8051 supports four rotate operations with the options –rotating

left or right and rotating through carry or not.
 Logical Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate
ANL A, A = A AND
√ √ √ √
<byte> <byte>
<byte> =
ANL <byte>,
<byte> AND √
A
A
<byte> =
ANL <byte>,
<byte> AND √
# data
# data
ORL A, A = A OR
√ √ √ √
<byte> <byte>

ORL <byte>, <byte> =

√
A <byte> OR A

<byte> =
ORL <byte>,
<byte> OR # √
# data
data
 Logical Instructions
XRL A, A = A XOR
√ √ √ √
<byte> <byte>
<byte> =
XRL
<byte> XOR √
<byte>, A
A
XRL <byte> =
<byte>, # <byte> XOR √
data # data
CLR A A = 00H Accumulator only
CLP A A = NOT A Accumulator only
Rotate ACC
RL A Accumulator only
Left 1 bit
Rotate Left
RLC A through Accumulator only
Carry
Rotate ACC
RR A Accumulator only
Right 1 bit
Rotate Right
RRC A through Accumulator only
Carry
 Branching Instructions
• 8051 supports unconditional jumping and subroutine calling in
three different ways.

• They are Absolute jump AJMP, ACALL, long jump LJMP, LCALL, and
short jump SJMP.
Un Conditional Branching Instructions
Conditional Branching Instructions
Addressing Modes
Mnemoni
Operation Immediat
c Direct Indirect Register
e
CJNE Jump if A
A,<byte> ≠= √ √
,rel <byte>
CJNE Jump if
<byte>,# <byte> = √ √
data,rel #data
Jump if A
JZ rel Accumulator only
=0
Jump if A
JNZ rel Accumulator only
≠0
 Branching Instructions
• The syntax for short jump instruction- SJMP 8-bit address.
• This 8 bit address is a relative address- to the program counter.
• The branching address -by adding the address given in the
instruction with the program counter content.
• The 8-bit address is a 2's complement number i.e., the most
significant bit -sign + or -. The remaining 7 bits - specify the
address. using SJMP -branch to anywhere between 127 bytes after
the program counter content and 128 bytes before it.(From (PC-
128 bytes) to (PC+127 bytes))
 Branching Instructions
• For example,
8800: SJMP 06h
• This instruction shift the execution to the location 8808h. The
program counter content after fetching the 2 byte - SJMP
instruction is 8802h. So, 06h added to 8802H results in 8808h.
• The syntax for LJMP -“LJMP 16-bit address”.
• After the execution of this instruction the Program counter -loaded
with the 16 bit address and the execution shifts to that location.
• The syntax for AJMP instruction is “AJMP 11 bit jump address”.
 Branching Instructions
• The destination branching address -absolute jumping is calculated -
keeping MSB 5 bits of the Program counter as it is and changing the
LSB 11 bits to that as given -instruction.
• For example,
8800: AJMP 7F0h
• This instruction branch the execution address 8FF0h. After fetching-
program counter content will be 8802h. Keeping the MSB 5 bits of
the PC (10001) as it is, and changing the LSB 11 bits to that given in
the instruction (111 1111 0000) , the branching address becomes
8FF0h.
 Branching Instructions
• The micro controller 8051 -single instruction for counter operation
to decrement -result (DJNZ). -very useful in looping using a counter
similar to “for loop” in high level languages.

• Similarly, jumping after checking the result of a comparison -done

by a single instruction (CJNE) -very useful for looping of instruction
execution based on a condition.

• Used in programming constructs similar to “do while” in high level

languages.
 Bit Manipulation Instructions
• The special feature of the 8051 micro controller is that it can
handle bit data also like that of byte data.

• The internal data memory map of 8051 has a bit- addressable area
also.

• The special function registers that have the address with 0 or 8 as

last digit in their hex address, are also bit addressable.

• The bit manipulation instructions include logical instructions and

conditional branching.
Bit Manipulation Instructions
Mnemonic Operation
ANL C,bit C = C AND bit
ANL C,/bit C = C AND (NOT bit)
ORL C,bit C = C OR bit
ORL C,/bit C = C OR (NOT bit)
MOV C,bit C = bit
MOV bit,C bit = C
CLR C C=0
CLR bit bit = 0
SETB C C=1
SETB bit bit = 1
CPL C C = NOT C
CPL bit bit = NOT bit
JC rel Jump if C = 1
JNC rel Jump if C = 0
JB bit,rel Jump if bit = 1
JNB bit,rel Jump if bit = 0
JBC bit,rel Jump if bit = 1 ; CLR bit
 Bit Manipulation Instructions
• The logical instructions - ANL and ORL. Conditional branching - JC,
JNC, JB, JNB, JBC.

• The other instructions available -CLR, SETB, CPL, and MOV.

• There are no instructions for halting the machine execution.

• Figure 10.6 shows the flag bits affected by the various instructions.

• Increment and decrement instructions do not affect the flag

register.
Instructions that affect Flag bits
Flags Affected
Instruction
C OV AC
ADD √ √ √
ADDC √ √ √
SUBB √ √ √
MUL 0 √
DIV 0 √
DA √
RRC √
RLC √
SETB C 1
CLR C 0
CPL C √
ANL C,bit √

ANL C,/bit √

ORL C,bit √

ORL C,/bit √

MOV C,bit √
CJNE √
Hardware Features of 8051
 Introduction
• The major benefit of microcontrollers lies in their built-in
parallel ports. The parallel ports can be used to interface all
data converters (ADCs, DACs, etc.) and display devices (LEDs,
LCDs, etc.).
• Any microcontroller-based system needs to transfer data
between the external peripherals and the microcontroller.
The microcontroller needs to read data fed by the user from
the external interface, process it, and give the output to the
peripherals or to the user again. To communicate data with
the external world, the microcontroller needs ports. The ports
may support either parallel or serial data transfer.
 Parallel Ports of 8051
• 8051 has 4 I/O ports namely Port0, Port1, Port2 and Port3.
The major constraint -the number of pin count. to reduce -
number of pins of the microcontroller ICs, the pins allotted for
the parallel ports -alternate functions also.
• Out of the available four parallel ports of 8051, Port 1 is used
exclusively for input and output functions alone.
 Parallel Ports of 8051
• The other port pins have -distinct function in addition to -
used for input and output functions. So, all the 24 pins of Port
0, port 2, port 3 -two different functions based on the
commands or programs running.

• All the four ports are bi-directional -programmed to have

input or output operation. All the 8 port pins -connected
through 8 D type port latches. One D type latch connects the
data in it to a port pin when the port is used as output port.
 Parallel Ports of 8051
• The user can access all the four ports using -addresses
mapped in the special function register area.

• Note that it is possible to address individual bits of all the

four ports by - bit addresses. Using this bit address, individual
bits can be read in or changed.
Parallel Ports and Port Pins of 8051
 Structure of Port 1
• Port 1 -only port in 8051 -used exclusively for input and output operation.

• The output of the port latch is connected to the port pin through a transistor
driver with internal pull up resistor. The port can be operated as an input after
writing 1 to all the bits of port 1 latch.

• 8051 ports are organized such that most instructions read the data from the
pin for read operation and some instructions read the data from the latch.

• So, the input buffer consists of the select logic and the related control signals
– ‘Read Latch’, ‘Read Pin’ for discriminating this.
Internal structure of PORT 1
Structures of Port 0 and Port 2
• Pins of ports 0 and 2 can be used as input port pins if a 1 is
written to the corresponding port latches by the programmer.

• For using Pins of ports 0 and 2 as output pins, a pull up resistor

may have to be connected to the corresponding port pins.

• Ports 0 and 2 have an alternate function in addition to being

used as input and output ports.
 Structures of Port 0 and Port 2
• The Ports 0and 2 are used as address/ data bus when external
memory or I/O devices are accessed. Port 0 -low order
address bus and the port 2 -higher order address bus.

• The drivers of Port0 and Port2 have an internal multiplexer to

serve this purpose as shown in figures.
Internal Structure of Port 0
Internal Structure of Port 2
 Structure of Port 3
• Port 3 is different from the other ports in the aspect that
individual port pins can be programmed for input and output
operation.
• Each pin of port 3 can be programmed - for input, output
operation or alternate functions.
• All the Port3 pins -serve an alternate function according to the
hardware signals and interfacing.
• the alternate functions can be activated only if the port3 bits are
written with 1s in their position.
Internal Structure of Port 3
 Alternate functions of Port 3
• Regarding the port access-two possibilities for read operation. The
read instruction for a port can either read the port latch or the port
pins.
• This difference is made in the internal hardware of 8051 in order to
avoid misinterpretation of the voltage level at the pins.
• The instructions, which have the operations – Read, Modify and
write to the port – read the Port latches and not the pins.
 Alternate Functions of Port 3
• All other instructions accessing the ports read the data from the
– CPL
port pins only. The example P3.0; that read the port latch are
instructions
– ANL P1,A; – DJNZ P3,LABEL
– ORL P2,A; – CLR P3.1;
– XRL P3,A; – SETB P1.2;
– INC P0; – MOV P2.2,C;
– DEC P1;
– JBC P1.1,DELAY;
• Note that these instructions read the port, modify the contents and
then write the data back to the port. So, the port latches are read
and not the pins.
 External Memory Interfacing in 8051
• External memory interfaced to 8051 can be of two types -
external program memory and external data memory.
• The external memory accesses are accomplished with the
Ports 0 and 2 of 8051 as they serve as the multiplexed
address/ data buses. The external memory in 8051 is always
accessed with 16 bit addresses.
• The 8051 outputs the signal ALE (Address Latch enable) in
order to de-multiplex the lower order address and data bus.
• In addition, the micro-controller sends the control signals on
the Port3 lines.
 Program memory interfacing

• The program memory can be placed outside the chip in

addition to the internal program memory. The complete
program memory can be placed outside the chip neglecting
the internal program memory.
• Applying proper the voltage level on the input line EA of 8051
can do the selection of any of the above two methods.
• Connecting EA to Ground will disable the internal program
memory and all program memory accesses are done to
external memory. The Read strobe signal given by the micro-
controller is PSEN.
• This active low signal is connected to the Read selection line
of the memory chips.
Connecting External Program
Memory to 8051
Connecting External Program Memory
to 8051
• Connecting EA pin of 8051 to the logic 1 or +5V will program
the microcontroller to use the internal program memory for
the addresses starting from 0000. After the available internal
memory, the external memory is accessed.
• If = 0; The internal program memory is not accessed.
• If = 1; Then internal program memory is accessed for address
0000-0FFF (or the available range) and external program
memory is accessed for addresses greater than 0FFF.
Connecting EPROM IC 27128 to 8051
 Accessing External Data Memory
• The data memory in the system - be Random Access memory
as it should facilitate both read and write operation of data.
The external data memory is interfaced in the same way as
the program memory is interfaced.

• The major difference is that the read and writes operations

can be done in Read /Write Random Access Memory.
Accessing External Data Memory
• The control signals for reading and writing to data
memory are available from the port3 pins. P3.6 pin
gives data memory write enable signal and P3.7 pin
gives out the RAM read enable signal.

• A decoder logic circuit is necessary to select the RAM

chip based on the higher order address lines.
Connection External Data Memory to
8051
Connecting RAM Chip 6264 to 8051
 8051 Timers
• The 8051 comes -with two 16 bit timers, both of which may
be controlled, set, read, and configured individually. The 8051
timers have three general functions:
• Programming predefined length of time, and then issuing an
interrupt request.
• Counting the transitions on an external pin,
• Generating baud rates for the serial port.
 8051 Timers
• Basically the timers are the digital counters which are
incremented at the pulses given to it. The timers can be
controlled to -function through four SFRs namely, TMOD,
TCON, TH0/TL0 and TH1/TL1.
• The timers will have overflow when it counts to full value and
resets to 0 upon next count.
• The overflow in the timers will set the two bits in the TCON
SFR. This overflow can be programmed to interrupt the
microcontroller execution and execute a predefined
subroutine.
 8051 Timers
• If the timer registers are incremented by the internal clock
pulses from the microcontroller, then the operation is termed
as ‘Timing’ operation.
• Meanwhile if the timer registers get their clock pulses from
an external device through the port 3 pins of 8051, then the
operation is termed as ‘Counting’.
• Timer 0 external input pin P3.4 (T0) is used give clock input to
timer 0 to act as counter.
• Timer 1 external input pin P3.5 (T1) is used give clock input to
timer 1.
 Timer SFRS
• The 8051 has two timers and each of them will have similar
operations and functions. The timer in 8051 is basically a 16-
bit register which can be incremented depending upon the
clock pulses applied to it.

• These timer registers are configured as the Special Function

Registers.
 Timer SFRS
• These SFRs at any time has the timer/counter register content.
So, the timers can be stopped at any time and the contents can
be read from these registers .Since there are only two bytes
devoted to the value of each timer it is apparent that the
maximum value a timer may have is 65,535.
• If a timer contains the value 65,535 and is subsequently
incremented, it will reset to 0 with an indication of overflow.
• One timer is TIMER0 and the other is TIMER1. Each timer also
has two 8 bit SFRs namely TH0 and TL0 forming the higher and
lower order bytes of Timer0 and TH1 and TL1 forming the
higher and lower bytes of Timer1.
 Timer SFRS
• These SFRs at any time has the timer/counter register content.
So, the timers can be stopped at any time and the contents can
be read from these registers .Since there are only two bytes
devoted to the value of each timer it is apparent that the
maximum value a timer may have is 65,535.
• If a timer contains the value 65,535 and is subsequently
incremented, it will reset to 0 with an indication of overflow.
• One timer is TIMER0 and the other is TIMER1. Each timer also
has two 8 bit SFRs namely TH0 and TL0 forming the higher and
lower order bytes of Timer0 and TH1 and TL1 forming the
higher and lower bytes of Timer1.
 TMOD SFR
• The TMOD SFR -used to control the mode of operation of both
timers. Each bit of the SFR gives the micro controller specific
information -how to run a timer. The higher order four bits
(bits 4 through 7) relate to Timer 1 whereas the low four bits
(bits 0 through 3) perform the same functions for timer 0.
BIT Patterns for TMOD (89h) SFR
 TCON SFR
• SFR that controls the two timers and provides
valuable information about them is TCON.
BIT Patterns for TCON (88h) SFR
Bit Name Bit Address Explanation of Function Timer

7 TF1 8Fh Timer 1 Overflow. The micro 1

controller sets this bit when Timer
1 overflows.
6 TR1 8Eh Timer 1 Run. When this bit is set 1
Timer 1 is turned on. When this bit
is cleared Timer 1 is off.
5 TF0 8Dh Timer 0 Overflow. The micro 0
controller sets this bit when Timer
0 overflows.
4 TR0 8Ch Timer 0 Run. When this bit is set 0
Timer 0 is turned on. When this bit
is cleared Timer 0 is off.
 TCON SFR
• Only 4 of the 8 bits of the TCON SFR is defined. the other 4 bits
of the SFR don’t have anything to do with timers. They are
related with Interrupts and they will be discussed in the
chapter that addresses interrupts.

• Note that the individual bits of TCON register can be addressed

separately by their bit addresses. This allows the programmer
to run the timers using bit addressable instructions and check
the overflow independently.
 Timer Operating Modes

• The two 16 bit timers of 8051 can be operated in any

one of the four modes. The mode selection can be
done by the setting the proper bits in the TMOD SFR.
Operating Modes of 8051
 Mode 0 - 13-bit Timer Mode
• Timer mode "0" is a 13-bit timer. Out of 16 bits of Timers, only 13bits
are used. The 5 bits of lower order byte is used and 8 bits of the
higher order byte of the timers are used in Mode0. Lower order byte
TL0/1 will count from 0 to 31.
• When TL0/1 is incremented from 31, it will "reset" to 0 and
increment TH0/1. So, the timer can only contain 8192 values from 0
to 8192.
• The timer can be operated as timer with internal clock pulses or as a
counter with external clock pulses.
• This selection is done by D2 bits of TMOD for Timer 0 and D6 bit of
TMOD for Timer1
 TCON SFR
• The clock pulses selected by D2 and D6 bits of TMOD is then
controlled by programmer setting and connected to the Timer
registers. The control is by three different means.

• First is the Timer Run control bits D4 and D6 of TCON register.

The timer will run only when Timer run control bits are set to 1.
 TCON SFR
• The other controls for the timers are through the GATE control
bits D4 and D7 of TMOD and the External inputs for timer.
Setting GATE to 1 allows the timer to count only if the external
control input INT0 or INT1 is set to 1. Setting Gate to 0 will
disable the corresponding external timer control inputs INT0
and INT1.

• Setting Timer to mode 0 will overflow back to zero after 8192

counts. This will set the TF1 and TF0 bits for timer 1 and timer
0 respectively.
Mode 0 Operation of Timer 1 of
8051
 Mode 1 – 16-bit Timer Mode
• In timer Mode 1 of 8051, each timer is operated as a 16-bit
timer. It functions just like mode 0 except that all 16 bits are
used.
• TL0/1 bits are incremented from 0 to 255. When TL0/1 is
incremented from 255, it resets to 0 and causes TH0/1 to be
incremented by 1. Since this is a full 16-bit timer, the timer
may contain -65536 distinct values.
• The control of gating and running the timer in mode 1 is similar
to that of mode 0
Mode 1 Operation of Timer 1 of
8051
Mode 2 – 8-bit Timer Auto Reload
Mode
• Only 4 of the 8 bits of the TCON SFR is defined. the other 4 bits
of the SFR don’t have anything to do with timers. They are
related with Interrupts and they will be discussed in the
chapter that addresses interrupts.

• Note that the individual bits of TCON register can be addressed

separately by their bit addresses. This allows the programmer
to run the timers using bit addressable instructions and check
the overflow independently.
Mode 2 – 8-bit Timer Auto Reload
Mode
• For example, let’s say TH0 holds the value FDh and TL0 holds
the value FEh. Then at the next counting pulse, TL0 will be
incremented to FFh. Then for the next pulse, the TL0 will
overflow and should have become 00.

• But, as it is reload mode, the TL0 will be loaded with TH0 i.e.,
FDh. The value of TH0 will never be changed. TH0/1 is set to a
known value and TL0/1 is the SFR that is constantly
incremented.
 Mode 2 – 8-bit Timer Auto
Reload Mode
• The auto-reload mode is very commonly used for
establishing a baud rate for Serial Communications.

• The control of gating and running the timer in mode 2

is similar to that of mode 0
Mode 2 Operating of Timer 1 of
8051
 Mode 3 – Split Timer Mode
• Mode "3" of 8051 timer is a split-timer mode and is applicable
only for Timer 0. When Timer 0 is placed in mode 3, it
essentially becomes two separate 8-bit timers. That is, Timer 0
is TL0 and Timer 1 is TH0.

• Both timers count from 0 to 255 and overflow back to 0.

• In mode 3, all the bits that are related to Real Timer 1 will
simply hold its count and will not run and the situation is
similar to keeping TR1=0.
 Mode 3 – Split Timer Mode
• In Split Timer mode of Timer 0, the real Timer 1 (i.e. TH1
and TL1) can not be started or stopped since the bits that
do that are now linked to TH0. The real timer 1, in this
case, will be incremented every machine cycle no matter
what.

• When two separate timers in addition to a baud rate

generator is required in an application, then real Timer 1
can be used as a baud rate generator and TH0/TL0 can be
used as two separate timers in mode 3.
Mode 3 Operation of Timer 0 of
8051
 Timer Control and Operation
• For timer operation (C/T = 0 in TMOD), the timer register
counts the divided-down clock. The timer register is
incremented once every (FOSC / 12) in standard mode. If the
clock frequency is 11,059,000KHz, then the counter will be
incremented at the rate of (11,059,000KHz/12) = 921,583 KHz.

• This means the counter will be incremented 921,583 times in a

second. Thus to have delay of say 0.1 seconds, then the
counter must be initialized to the count value of (0.1*921,583)
= 92158.
 Timer Control and Operation
Following steps are the program steps to initialize and use a
timer in 8051
•Decide what mode the timer to be in.
•Initialize the TMOD SFR.
•Write the timer value to Timer register
•Start the timer running by setting the TR0/1 bit in TCON
register
•Check for TF0/1 bit or program to handle timer overflow as
interrupt and execute interrupt subroutine.
Steps in Timer Control
Write TMOD

Write TCON

Write timer register

Start timer

Program Required Operation

Continue
 Timer Control and Operation

• To set the bit TR1 of TCON (D6 bit), any one of the following
two commands can be used -MOV TCON, #40h OR SETB TR1

• As, TR1 is a bit addressable location, SETB instruction is used

and this has the benefit of setting the TR1 bit of TCON without
changing the value of any of the other bits of the SFR.
 Reading Value of 16-bit Timer
• There are two common ways of reading the value of a 16-bit
timer;
1. Read the actual value of the timer as a 16-bit number from
TH0/TL0 or TH1/TL1.
2. Detect when the timer has overflowed from the TF0/1 bits of
TCON. If TF0 is set, it means that timer 0 has overflowed; if
TF1 is set, it means that timer 1 has overflowed. This overflow
can act as an interrupt and can directly run an Interrupt
service routine, if enabled properly.
 Using Timers and Counters

• Timers in 8051 can be programmed to count pulses from

external devices. For example, a sensor placed along a
conveyor belt can give one pulse for every object moving on
the conveyor.

• This pulse can be counted by the 8051 timer in counter mode.

The pulses from the sensor can be given as an external input to
a timer and programmed to count.
 Using Timers and Counters
• The timer can be programmed to give an interrupt after a
predefined count value. For example, after counting 12 objects
in the conveyor or after counting 12 pulses in the timer, an
interrupt may be given to the 8051 system to give signal to
some other action like packing the 12 items
• It is important to note that the 8051 checks the P3.4 line each
instruction cycle (12 clock cycles). This means that if P3.4 is
low, goes high, and goes back low in 6 clock cycles it will not be
detected by the 8051.
• This also means the 8051 event counter is only capable of
counting events that occur at a maximum of 1/24th the rate of
the crystal frequency.
 Using Timers and Counters
• That is to say, if the crystal frequency is 12 MHz, it can count a
maximum of 500,000 events per second (12.000 MHz * 1/24 =
500,000).

• If the event being counted occurs more than 500,000 times per
second, it will not be able accurately counted by the 8051.
 Interrupt Sources and Interrupt
Vector Addresses
• 8051 basically has following five interrupt sources so
that any of the following events will make 8051 to
execute an interrupt service routine.
• Timer 0 Overflow.
• Timer 1 Overflow.
• Reception/Transmission of Serial Character.
• External hardware interrupt 0.
• External hardware interrupt 1.
 Interrupt Sources and Interrupt
Vector Addresses
• Different interrupt sources have to be distinguished
and 8051 must execute different subroutines
depending –interrupt triggered. This is accomplished
by jumping or calling to a fixed address when
interrupt occurs.
• These addresses are called interrupt vector addresses
or interrupt handler addresses.
Interrupt Sources and Interrupt
Vector Addresses
Interrupt Flag Interrupt Vector Address

External 0 IE0 0003h

Timer 0 TF0 000Bh

External 1 IE1 0013h

Timer 1 TF1 001Bh

Serial RI/TI 0023h

 Interrupt Sources and Interrupt
Vector Addresses
• Whenever Timer 0 overflows (i.e., the TF0 bit is set), the main
program will be temporarily suspended and control will jump
to 000BH.

• It is assumed that service routine at address 0003H handles the

situation of Timer 0 overflowing.
 Enabling and Disabling Interrupts
• By default at power up, all interrupts are disabled. This means
that even if, for example, the TF0 bit is set, the 8051 will not
execute the interrupt. Programming must be done specifically
to enable interrupts.

• Interrupt Enable Special Function Register IE SFR at the address

A8h is used to enable and disable interrupts by modifying its
bits.

• The interrupts enabling can be handled individually by - bit

addresses for the individual bits of IE register.
 Bit Patterns for the IE SFR (A8H)
Bit D7 D6 D5 D4 D3 D2 D1 D0
position

Bit AF AC AB AA A9 A8
Address

Name EA - - ES ET1 EX1 ET0 EX0

Explana
tion
Global
Enable Enable Enable Enable Enable
Interrupt Undefi Undefin
Serial Timer 1 External 1 Timer 0 External 0
Enable/ ned ed
Interrupt Interrupt Interrupt Interrupt Interrupt
Disable
 Bit Patterns for the IE SFR (A8H)
• Each of the 8051’s interrupts has its own bit in the IE SFR. A
particular interrupt can be enabled by -corresponding bit. For
example, to enable Timer 1 Interrupt, the one of the following
instructions can be executed.

• MOV IE, #08h OR SETB ET1

 Bit Patterns for the IE SFR (A8H)
• However, before Timer 1 Interrupt (or any other interrupt) is
truly enabled, bit 7 of IE SFR must also be set. Bit 7, the Global
Interrupt Enable/Disable, enables or disables all interrupts
simultaneously.

• That is, if bit 7 is cleared then no interrupts will occur, even if

all the other bits of IE are set. Setting bit 7 will enable all the
interrupts -selected by setting other bits in IE.
 Interrupt Priorities and Polling
Sequence
• The 8051 automatically evaluates whether an interrupt occurs
after every instruction. When checking for interrupt conditions,
it checks them in the following order:
• External 0 Interrupt
• Timer 0 Interrupt
• External 1 Interrupt
• Timer 1 Interrupt
• Serial Interrupt
 Interrupt Priorities and Polling
Sequence
• The above list -gives the interrupt priority.
• So, whenever the External 0 interrupt and Timer 1 interrupt
occurs at the same instant, then 8051 microcontroller executes
the interrupt service routine corresponding to External 0
interrupt first.
• Then 8051 microcontroller will return to the main program,
execute one instruction and then execute the interrupt service
routine corresponding to Timer 1 Interrupt.
 Interrupt Priorities and Polling
Sequence
• If a Serial Interrupt occurs at the exact same instant that an External 0
Interrupt occurs, the External 0 Interrupt will be executed first and the
Serial Interrupt will be executed once the External 0 Interrupt has
completed.
• The 8051 offers two levels of interrupt priority: high and low. By using
interrupt priorities, the above interrupts can be divided into two
separate interrupt priorities. So, the five interrupts can be again
prioritized.
• Interrupt priorities are controlled by the IP SFR (B8h). For example, if
the Serial Interrupt is much more important than the Timer 0 interrupt,
then the Interrupt Priority register IP SFR at the address B8h can be
properly programmed to set the priority.
 Interrupt Priorities and Polling
Sequence
• This is done by assigning a high priority to the Serial Interrupt
and a low priority to the Timer 0 Interrupt. By setting the D4 bit
to 1, the serial interrupt will be set to higher priority and
making D1 bit to 0, the Timer 0 interrupt will be set to lower
priority.
• Note that the priority can be set individually by using the bit
addresses of the IP register. For example, the timer 0 interrupt
priority can be made high by setting the D1 bit of IP SFR. So,
the following instructions can be used for the same.
• SETB PT0 (or) SETB B9H (or) MOV IP, #82H
 Bit Patterns for the IP SFR

Bit position D7 D6 D5 D4 D3 D2 D1 D0

Bit Address BC BB BA B9 B8
Name EA - - PS PT1 PX1 PT0 PX0
Explanation
Enable
Interrupts
Serial Timer 1 External 1 Timer 0 External 0
- Undef Undefin
Interrupt Interrupt Interrupt Interrupt Interrupt
Made 0 to ined ed
Priority Priority Priority Priority Priority
disable all
interrupts
 Interrupt Priorities and Polling
Sequence
When considering interrupt priorities, the following rules apply:
•Nothing can interrupt a high-priority interrupt--not even another
high priority interrupt.
•A high-priority interrupt may interrupt a low-priority interrupt.
•A low-priority interrupt may only occur if no other interrupt is
already executing.
•If two interrupts occur at the same time, the interrupt with
higher priority will execute first. If both interrupts are of the same
priority the interrupt which is serviced first by polling sequence
will be executed first.
 Interrupt Priorities and Polling
Sequence
• The complete structure of the 8051 interrupts can be well
understood -figure 11.16. The five interrupt sources are passed
first - IE register, which decides the enabling and disabling of
interrupts. The global interrupt enable -shown -figure.

• The IP register - set two priority levels among the available

interrupts. This is shown in the figure as high priority and low
priority blocks. The bits IT0 and IT1 can be set by TCON special
function register and this is used to select whether the
hardware interrupt is level triggered or edge triggered.
Structure of 8051 Interrupts
IE IP High
register register priority
1 interrupt
INT0 IT0 IE0
0 Low
priority
interrupt
TF0

1
INT1
IT1 IE1
Interrupt
0 polling
sequence
TF1

RI

TI

Interrupt
enables

Global
Enable Interrupt
enabled
 Timing of Interrupts
• 8051 micro-controller samples the hardware signal level on its pins once in
every machine cycle. A machine cycle is the time taken by the controller to
access one memory location or I/O device.
• As 8051 takes 12 clock cycles to complete one machine cycle, the interrupt
signal applied at the pins of 8051 must be available for at least 12 clock
periods.
• External interrupts are applied at the pins INT0 and INT1. The sensing of
voltage level applied to this pin can also programmed in 8051. The interrupts
can be either level triggered or edge triggered as set by the IT0 and IT1 bits of
the SFR TCON
• A ‘0’ on these bit positions will make both the hardware interrupts to be level
triggered. Level triggered means a low level voltage on the interrupt pins will
activate the interrupts.
 Bit Patterns for the TCON SFR
Bit position D7 D6 D5 D4 D3 D2 D1 D0

Bit Address 8F 8E 8D 8C 8B 8A 89 88
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Interrupt 0
Interrupt 1 type
Timer 0
Timer 1 Extern type control. control. Set
run
run al Set to 1 by External to 1 by
Timer control
Timer 1 control Interru software for Interrupt software
0 bit. Set
Explanation Overflow bit. Set to pt 1 edge 0 edge for edge
Overflo to 1 by
flag 1 by edge triggering detect triggering
w flag softwar
software detect and cleared bit and
e to
to run. bit for level cleared for
run.
triggering level
triggering
Bit Address 8F 8E 8D 8C 8B 8A 89 88
 Interrupt Priorities and Polling
Sequence
• A ‘1’ on the IT0 and IT1 bits of the SFR TCON will program the
hardware interrupts as edge triggered. Edge triggering means
the change of voltage from high state to low state will activate
the interrupt.
• When an interrupt is triggered, the micro controller takes the
following actions automatically:
• The current Program Counter is saved on the stack, low-byte
first.
• Interrupts of the same and lower priority are blocked.
• In the case of Timer and External interrupts, the corresponding
interrupt flag is cleared.
 Interrupt Priorities and Polling
Sequence
• Program execution transfers to the corresponding interrupt
handler vector address.
• The Interrupt Handler Routine executes.
• An interrupt ends when your program executes the RETI
(Return from Interrupt) instruction. When the RETI instruction
is executed the micro controller takes the following actions:
• Two bytes are popped off the stack into the Program Counter
to restore normal program execution.
• Interrupt status is restored to its pre-interrupt status.
Interrupt Priorities and Polling Sequence
• The internal architecture of 8051 is such that the external
hardware interrupts will be cleared automatically when the
interrupt service routine is executed only if is programmed to be
edge or transition triggered.

• If the interrupts are level triggered, then the programmer will

have to reset the interrupt enable corresponding to this interrupt
using IP SFR.

• If the interrupt being handled is a Timer or External interrupt, the

micro controller automatically clears the interrupt flag before
passing control to interrupt handler routine. This means it is not
necessary to clear the bit in the program.
 8051 Serial Ports
• One of the 8051’s many powerful features is its integrated Universal
Asynchronous Receiver Transmitter (UART), otherwise known as a serial
port. With integrated serial port of 8051, data can be transmitted and
received easily by reading and writing the data to the serial port registers.
The features of the 8051 serial ports are
• Full duplex operation.
• Receive Buffered.
• Access using single double buffered Register SBUF.
• Four different modes of operation.
• Option to use fixed baud rate or programmable baud rate.
 8051 Serial Ports
• Full Duplex serial port means that it can transmit and receive
data simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously
received byte has been read from the SBUF register.

• However, if the first byte still hasn’t been read by the time
reception of the second byte is complete, one of the bytes will
be lost. The serial port receive and transmit registers are both
accessed at Special Function Register SBUF.
 8051 Serial Ports
• Data to be transmitted are written to the register SBUF and
the data received by the serial port are read from the register
SBUF. Physically reading and writing SBUF actually accesses
two separate registers.

• This technique of having same address for two different

registers is called double buffering.
 SERIAL PORT CONTROL SFRS
• The serial port of 8051 is controlled by two registers in SFR area of
8051 as shown in Table
• The two registers are Serial Port control registers; SCON and serial
port buffer register SBUF.

SFR Name Description SFR Address

Serial port control
SCON 98h
register
Serial port buffer
SBUF 99h
register
 SERIAL PORT CONTROL SFRS
• In addition to the above two registers, the MSB of PCON register
named as SMOD bit is used to double the baud rate of serial
transmission and reception.
• If SMOD bit is set to 1, then the baud rate is doubled.
• The individual bits of SCON have the functions as shown in Table .
As the SCON register has many individual status bits, the
individual bits of this register are bit addressable. The bit address
is also given in Table .
• The programmer can use these bit addresses to check the status
of the serial port and set the mode individually.
Bit patterns for SCON (98h) SFR

Bit Name Bit Address Explanation of Function

D7 SM0 9Fh
Serial port mode select bits
D6 SM1 9Eh
D5 SM2 9Dh Multiprocessor Communications Enable bit
Receiver Enable. This bit must be set in order to receive
D4 REN 9Ch
characters.
D3 TB8 9Bh Transmit bit 8. The 9th bit to transmit in mode 2 and 3.
D2 RB8 9Ah Receive bit 8. The 9th bit received in mode 2 and 3.
Transmit Interrupt Flag. Set when a byte has been
D1 TI 99h
completely transmitted.
Receive Interrupt Flag. Set when a byte has been completely
D0 RI 98h
received.
 Bit Pattern - Description
• D7 and D6 bits of the SCON register define the operation
modes of the serial port and the basic operating modes
are given in Table.

• The SM0 and SM1 bits can select any one of the four
operating modes described in the next section.
Definition of Bits SM0 and SM1 in
SCON SFR
 Bit Pattern - Description
• The next bit, SM2, is a flag used for enabling "Multiprocessor
communication" in modes 2 and 3. If SM2 is set to 1 in modes 2
and 3, the “Receive Interrupt” RI flag will not be activated if the
received 9th data bit is 0. If SM2 is set in Mode1, then “Receive
Interrupt” RI flag will not be activated if valid stop bit is not
received.

• This can be useful in certain advanced serial applications. It can

be now assumed that SM2 bit has to be cleared so that RI flag
will be set when any character is received.
 Bit Pattern - Description
• The next bit, REN, is "Receiver Enable." This bit is set in order to
receive the characters from the receive data line of the serial
port.

• The TB8 bit is used in modes 2 and 3. In modes 2 and 3, a total of

nine data bits are transmitted. The first 8 bits are the 8 bits of the
data to be transmitted, and the ninth bit is taken from TB8. The
RB8 also operates in modes 2 and 3 on the reception side.
 Bit Pattern - Description
• When a byte is received in modes 2 or 3, a total of nine bits
are received. In this case, the first eight bits received are the
data of the serial byte received and the value of the ninth bit
received will be placed in RB8.

• TI means "Transmit Interrupt." When a program writes a data

to the serial port buffer SBUF, then the serial port will start
shifting this data in the serial transmit line bit by bit at the
predefined clock speed or baud rate. 8051 will give TI signal to
the programmer after sending the data completely.
 Bit Pattern - Description
• Upon sensing the TI bit set to 1, the programmer can then write
the next data for transmission. When the TI bit is set, the
programmer may assume that the serial port is "free" and ready
to send the next byte.

• Finally, the RI bit means "Receive Interrupt." Whenever a data is

received on the receive data line of the serial port, this serial data
will be shifted in to a buffer and then stored in the SBUF register.

• Setting of RI bit indicates that a byte has been received. Upon

sensing the RI bit set to 1, the programmer may read the data
from the SBUF.
 OPERATING MODES
• Bits SM0 and SM1 are used to set the serial mode to a value
between 0 and 3.

• Selecting the Serial Mode selects the mode of operation (8-bit/9-

bit, UART or Shift Register) and also determines how the baud
rate will be calculated.

• In modes 0 and 2 the baud rate is fixed based on the oscillator’s

frequency. In modes 1 and 3 the baud rate is variable based on
Timer 1 overflows.
Block Diagram of the serial port of
8051
 SBUF
• SBUF is physically two registers with the same address.
• When data to be transmitted is written to the SBUF register, then
it will be shifted bit by bit into the TXD line of 8051. The port 3 pin
3.1 acts as the TXD line. The shifting is done by the transmit clock
which determines the baud rate.
• Similarly, when the data bits are received on the RXD line (Pin 3.0
of port 3), the bits are shifted serially into the shift register
according to the Receive clock.
• After the reception is complete, the data received will be placed
on SBUF from where it can be read by the programmer through
the internal bus.
 Reception / Transmission
• Mode 0: In this mode serial data is entering and exiting through RxD pin. So, in
mode 0, Full duplex is not possible – meaning that both transmission and
reception cannot take place simultaneously. TxD pin outputs the shift clock. 8
bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the
oscillator frequency. Transmission is started by writing a data byte to the SBUF
register and once the transmission is complete, TI flag is set.

• The reception is started by enabling REN in SCON register. Once the data
reception is complete, the RI flag is set.

• The baud rate in Mode 0 is fixed at one twelfth of the clock frequency. Baud
rate= (Clock frequency/12)
Signal Transmission / Reception
pattern
 Reception / Transmission

• Mode 1: In this mode, 10 bits are transmitted through TxD and

simultaneously 10 bits can be received through RxD. The 10
bits are made up of a start bit (0), 8 data bits (LSB first), and a
stop bit (1). On completion of reception, the stop bit goes into
RB8 in Special Function Register SCON. The baud rate is
variable and is set by the Timer 1 overflow rate. The baud rate
for mode 1 is fixed at the following rate.
 Reception / Transmission
• Baud rate= (Timer 1 overflow rate /16) if SMOD bit in PCON
SFR is set to 1.

• Baud rate= (Timer 1 overflow rate /32) if SMOD bit in PCON

SFR is set to 0.

• Note that PCON is a special Function Register described in

chapter 25. The MSB of PCON register can be set or reset by
the programmer. The baud rate can be doubled by setting
the MSB of PCON.
 Reception / Transmission
• In order to generate the baud rate clock from timer 1, Timer 1
can be configured to act as timer in auto reload mode with the
timer 1 interrupt disabled.

• As in mode 0, the transmission is initiated by writing a data to

SBUF register. Reception is initiated by a 1 to 0 transition that is
the start bit received and also when REN of SCON SFR is 1.
 Reception / Transmission
• Mode 2: In this mode, 11 bits are transmitted through TxD or received
through RxD. The 11 bits are made up of one start bit (always 0), 8 data bits
(LSB first), a programmable 9th data bit, and a stop bit (always 1). The 9th
data bit transmitted is same as TB8 bit in SCON special function register. It
can be assigned the value of 0 or 1 by the programmer. Or, for example, the
parity bit (P, in the PSW) could be moved into TB8.
• On reception, the 9th data bit goes into RB8 in Special Function Register
SCON, while the stop bit is ignored. The baud rate is programmable to either
1/32 or 1/64 of the oscillator clock frequency.
• Baud rate= (Clock frequency /32) if SMOD bit in PCON SFR is set to 1.
• Baud rate= (Clock frequency /64) if SMOD bit in PCON SFR is set to 0.
 Reception / Transmission
• Mode 3: In this mode, 11 bits are transmitted through TxD and
simultaneously 11 bits are received through RxD. The 11bits are
made up of a start bit (0), 8 data bits (LSB first), a programmable
9th data bit, and a stop bit (1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate. The baud rate in Mode 3
is variable.
• The baud rate for mode 3 is fixed at the following rate similar to
mode1.
• Baud rate= (Timer 1 overflow rate /16) if SMOD bit in PCON SFR is
set to 1.
• Baud rate= (Timer 1 overflow rate /32) if SMOD bit in PCON SFR is
set to 0.
 Reception / Transmission
• In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other modes
by the incoming start bit when REN = 1.
• The flow chart 11.20 shows the steps in programming
the serial port of 8051. These steps are detailed in the
following sections and also in the example programs.
Programming the Serial Port
 Initializing Serial Port
• Once the Serial Port Mode has been selected, then the programmer
must configure the serial port’s baud rate. Only serial port modes 1
and 3, the baud rates are programmable.

• The Baud Rate is determined based on the oscillator’s frequency

when in mode 0 and 2. In mode 0, the baud rate is always the
oscillator frequency divided by 12. This means if the crystal is 11.059
MHz, mode 0 baud rate will always be 921,583 baud.

• In mode 2 the baud rate is always the oscillator frequency divided by

64, so an 11.059 MHz crystal speed will yield a baud rate of 172,797.
 Initializing Serial Port
• In modes 1 and 3, the baud rate is determined by how frequently timer 1 overflows. The
most common method is to put timer 1 in 8-bit auto-reload mode (timer mode 2) and set
a reload value (TH1) that causes Timer 1 to overflow at a frequency appropriate to
generate a baud rate.
• To determine the value that must be placed in TH1 to generate a given baud rate, the
following equation is used.
• TH1 = 256 - ((Clock frequency / 384) / Baud) if SMOD in PCON SFR is 0.
• TH1 = 256 - ((Clock frequency / 192) / Baud) if SMOD in PCON SFR is 1.
• The following table gives the commonly used baud rates and the corresponding reload for
the timer in mode 2 assuming the clock frequency of 11.059 MHz and SMOD is reset.
Commonly used baud rates

Baud Rate Timer value TH1

300 A0h

1200 D0h

2400 FAh

9600 FDh
 Baud Rate
Following set of instructions will set the timer for the baud
rate of 9600.
– MOV TMOD, #00100000B ;timer/counter 1 set for mode 2, 8-
bit TIMER
– ;operation
– MOV TH1, #0FDh ; timer/counter 1 is
timed for 9600 baud
– SETB TR1 ; timer/counter 1 is
enabled for free run
•For initializing the serial port for mode 3 operation, the
following instruction can be used.
– MOV SCON, #11010000B
 Transmitting and Receiving Data
Using Serial Port
• Once the Serial Port has been properly configured as explained
above, the serial port is ready to be used to send data and
receive data.

• To write a byte to the serial port one must simply write the
value to be transmitted to the SBUF (99h) SFR. For example, to
send the letter "A" to the serial port, the following instruction
can be written.
MOV SBUF, #’A’
Transmitting and Receiving Data
Using Serial Port
• Upon execution of the above instruction the 8051 will begin
transmitting the character via the serial port. Once the transmission is
complete, the serial port transmit interrupt flag TI is set. Since the 8051
does not have a serial output buffer, a character can not be written to
SBUF before the previous written character is completely transmitted.
This can be accomplished by checking the TI flag.

• Reading data received by the serial port is equally easy. To read a byte
from the serial port one just needs to read the value stored in the SBUF
(99h) SFR after the 8051 has automatically set the RI flag in SCON.
8051 Interface Examples
 Interfacing 8255 to 8051
• When the 8051 is connected to external memory, port 0 (P0) is used for the
lower-order address and data bus and port 2 (P2) is used for the higher-
order address bus.
• Since the port 3 pins have an alternative function, the net result is that only
P1 is left for input and output operation.
• One way to expand the number of I/O ports is to connect the 8255
programmable peripheral interface with the 8051.
• The interfacing of the 8255 with the 8051 is done assuming the 8255 as a
memory location, because the 8051 supports only memory-mapped I/O.
• For accessing the external memory in the 8051, the MOVX instruction is
used.
• The lower-order address bus and the data bus are multiplexed and are
available in the port 0 pins.
• This is de-multiplexed using a latch and the ALE signal.
 Learning Outcomes

• After studying this chapter, you will be able to understand

the following:
• Interfacing of the programmable interface IC 8255 and
switches and LEDs with the 8051
• Interfacing of analog-to-digital and digital-to-analog
converters
• Interfacing of LCD interface, Matrix keyboard and motors
• 8051 application examples
Interfacing 8255 with 8051
 Interfacing 8255 to 8051
• The first step in the general interfacing method is to decide the
addresses for the port.
• The 8051 uses 16-bit addresses and the most significant address
lines are used for decoding and selecting the device.
• Here, the higher-order address bus from port 2 is given to a decoder
logic circuit.
• From the decoder, the 8255 chip select signal is generated.
• The 8255 needs four addresses for interfacing with any processor—
three for the ports A, B, and C and one for the control register.
• The lower-order address lines A0 and A1 are connected to select
one of these four registers. The read and write control signals are
available from the port 3 pins P3.7 and P3.6.
Interfacing of Push button switches & LEDs
• The simplest input and output device that can be interfaced to any
microprocessor is the push button switches and Light Emitting Diodes
(LEDs).

• The example here is considering 4 push button switches interfaced to one

port of 8051 and four LEDs connected to another port.

• The switches are connected in such a way that when it is open, it

connects a logic 0 i.e. 0Volts to the port and when it is closed, it connects
logic 1 i.e. 5Volts to the port pins.
Interfacing of switches to port pins
Interfacing of Push button switches & LEDs

• The circuit connections are shown in Figure are such that the port is not
damaged and also the port is not sourcing over current. This ensures safe
operation of the ports and switches.

• An LED gives out light illuminating when it is forward biased and has enough
current flowing through it. LED indicators are easy to interface with the
microcontrollers as output device.

• LEDs can be driven with a minimum current of about 10mA. A driver IC can be
used for illuminating LEDs.
Interfacing LED with driver to port pins
• Figure shows a method of using an inverter driver for connecting ports to LEDs.
 Description

• When logic 1 is given out on the port pin, it will be

inverted by the inverter and will connect ground
(logic 0) to the cathode of LED. This will forward
bias the LED and light will be given by LED.
 Interfacing of 4 switches and 4 LEDs
• Figure shows the interfacing of 4 Switches to port 3 pins and 4 LEDs to Port1 pins of 8051.
• The inverter driver IC 74240 is used to drive the LEDs. Even though only 4 LEDs are
shown connected in Figure 12.4, we can connect 8 LEDs as 74240 has eight inverter
drivers.
• The program to display the contents of 4 switches on to the LEDs is as followed.
 Description

– Start: MOV A, P3
– MOV P1, A

• When logic 1 is sensed on port 3 line, the

same data is given as output on port 1 lines.
When logic 0 is sensed, the same is given on
port 1lines. The LEDs will not be illuminated
now as the LEDs are not forward biased.
Interfacing of Seven Segment Displays
• Seven segment displays consist of seven LED segments. The seven segments are
arranged in the form as shown in figure and the display of various digits is also
shown in the same figure.
• Seven segment displays are available in a single dual line in package.
• There are each pin for each segment and these pins are named from a to f and
another LED is available for decimal point.
• In addition to these eight pins, the seven segment displays have one more pin
for power supply.
• Seven segment displays come in two types either in common anode or common
cathode.
Interfacing of Seven Segment Displays

• In common anode display, the anode of all segment LEDs are tied
together and taken out.
• So, to illuminate a segment, the common anode is connected to
the supply and then the segment input i.e. a to f is connected to a
low level logic 0.
• In common cathode display, the cathodes of all the LEDs are
connected together and taken out.
• So, to illuminate a segment, the corresponding segment input is
connected to the high level voltage or logic 1 and the common
cathode is connected to the ground. This will forward bias the LEDs
and illuminate them.
Seven Segment Display
 Interfacing Description
• Interfacing of Seven segment displays to 8051 microcontroller needs a driver
as shown in Figure. Here 74240 TTL inverter driver IC is used for driving the
seven segment displays.

• Also the seven segment display is assumed to be common anode type. The
common anode is connected to the supply +5V.

• The interfacing diagram for displaying the BCD code obtained from key
connected to port3 and displaying the same in seven segment display
connected to port 1
Interfacing Switches and seven segment
display to 8051
 Interfacing Description
• The segments can be illuminated
if the segments pins are
connected to the low level of
supply or to ground.
• This is done by connecting the
segment inputs of logic 0 through
74240. The 74240 IC will invert
the inputs applied to it. So, if we
want to illuminate a particular
segment, the corresponding
output for that segment has to be
logic 1.
• The data output for displaying
decimal digits 0 to 9