Input/Output Organization 1

Overview

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor

 Serial Communication
Input/Output Organization 3

Input Output Organization

– I/O Subsystem
• Provides an efficient mode of communication between the
central system and the outside environment

– Programs and data must be entered into computer memory for

processing and results obtained from computer must be
recorded and displayed to user.

– When input transferred via slow keyboard processor will be idle

most of the time waiting for information to arrive
– Magnetic tapes, disks
Input/Output Organization 4

Peripheral Devices
• Devices that are under direct control of computer are said to be
connected on-line.

• Input or output devices attached to the computer are also called

peripherals.

• There are three types of peripherals :

• Input peripherals
• Output peripherals
• Input-output peripherals

Peripheral (or I/O Device)

Monitor (Visual Output Device) : CRT, LCD
KeyBoard (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
Printer (Hard Copy Device) : Daisy wheel, dot matrix and laser printer
Storage Device : Magnetic tape, magnetic disk, optical disk
Input/Output Organization 5

Peripheral Devices
Input Devices Output Devices
• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Daisy Wheel, Dot Matrix, Laser)
- Paper Tape Reader • Plotter
- Bar code reader
- Optical Mark Reader
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
•
Input/Output Organization 6

I/O Interface
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
(1). Peripherals – Electromechanical or Electromagnetic Devices
CPU or Memory - Electronic Device
– Conversion of signal values required
(2). Data Transfer Rate
• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
– Some kinds of Synchronization mechanism may be needed

(3). Data formats or Unit of Information

• Peripherals – Byte, Block, …
• CPU or Memory – Word

(4). Operating modes of peripherals may differ

• must be controlled so that not to disturbed other peripherals connected to CPU
Input/Output Organization 7

I/O Bus and Interface

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Interface :
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory

4 types of command interface can receive : control, status, data o/p and data i/p
Input/Output Organization 8

I/O Bus and Interface

•Control command : is issued to activate peripheral and to inform what to do

•Status command : used to test various status condition in the interface and
the peripherals

•data o/p command : causes the interface to respond by transferring data from
the bus into one of its registers

•data i/p command : interface receives an item of data from the peripheral and
places it in its buffer register.
Input/Output Organization 9

I/O Bus and Memory Bus

Functions of Buses

• MEMORY BUS is for information transfers between CPU and the MM

• I/O BUS is for information transfers between CPU and I/O devices
through their I/O interface

•3 ways to bus can communicate with memory and I/O :

(1). use two separate buses, one to communicate with memory and the
other with I/O interfaces
- Computer has independent set of data, address and control bus one
for
accessing memory and another I/O.
- done in computers that have separate IOP other than CPU.

(2). Use one common bus for memory and I/O but separate control lines
for each
(3). Use one common bus for memory and I/O with common control
lines for both
Input/Output Organization 11

Isolated vs. Memory Mapped I/O

Isolated I/O
- Many computers use common bus to transfer information between
memory or I/O.
- The distinction between memory transfer and I/O transfer is made
through separate read and write line.
-In the isolated I/O configuration , the CPU has distinct input and output
instructions and each of these instruction is associated with the
address of an interface register.
- Distinct input and output instructions -each associated with address of interface
register
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations
Input/Output Organization 12

I/O Interface
Port A I/O data
Bidirectional register
Bus
data bus buffers
Port B I/O data
register

Internal bus
CPU
Chip select I/O
CS
Register select
Control Control Device
RS1 Timing
Register select register
RS0 and
I/O read Control
RD Status Status
I/O write
WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
- Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device→ Port A = Data; Port B = Command;
- CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics
Input/Output Organization 13 Lecture 36

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor
 11-3. Asynchronous Data Transfer
Synchronous Data Transfer: Clock pulses are applied to all registers
within a unit and all data transfer among internal registers occur
simultaneously during the occurrence of a clock pulse. Two units such
as CPU and I/O Interface are designed independently of each other. If
the registers in the interface share a common clock with CPU registers,
the transfer between the two is said to be synchronous.
Asynchronous Data Transfer: Internal timing in each unit (CPU and
Interface) is independent. Each unit uses its own private clock for
internal registers. Asynchronous data transfer between two
independent units requires that control signals be transmitted
between the communicating units to indicate the time at which data is
being transmitted. One way of achieving this is by means of
STROBE(Control signal to indicate the time at which data is being
transmitted) pulse and other method is HANDSHAKING(Agreement
between two independent units).
1

2
2

1
Timeout : If the return handshake signal does not respond within a given time period,
the unit assumes that an error has occurred.
– Asynchronous Serial Transfer
• Synchronous transmission :
– The two unit share a common clock frequency
– Bits are transmitted continuously at the rate dictated by the clock
pulses
• Asynchronous transmission :
– Binary information sent only when it is available and line remain
idle otherwise
– Special bits are inserted at both ends of the character code
– Each character consists of three parts :
» 1) start bit : always “0”, indicate the beginning of a character
» 2) character bits : data
» 3) stop bit : always “1”

1 1 0 0 0 1 0 1

S tart S to p
C harac ter b its
b it b it
• Asynchronous transmission rules :
–  When a character is not being sent, the line is kept in the 1-state
–  The initiation of a character transmission is detected from the
start bit, which is always “0”
–  The character bits always follow the start bit
–  After the last bit of the character is transmitted, a stop bit is
detected when the line returns to the 1-state for at least one bit
time
• Baud Rate : Data transfer rate in bits per second
– 10 character per second with 11 bit format = 110 bit per second
Input/Output Organization 21

Universal Asynchronous Receiver Transmitter

A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select
CS
Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check parity, and no.
of stop bits
•UART stands for?

a. Universal Asynchronous Sender Receiver

b. Universal Asynchronous Receiver Transmitter
c. Universal Synchronous Receiver Transmitter
d. None Of These.
1. Which of the following best describes synchronous data transfer?

A)Data transfer occurs with a clock signal controlling the timing.

B)Data transfer occurs without any timing constraints.
C)Data transfer is initiated by external events.
D)Data transfer occurs with random timing.

2. In synchronous data transfer, what is the role of the clock signal?

A)It ensures that data transfer occurs without any timing constraints.
B)It initiates data transfer upon external events.
C)It controls the timing of data transfer.
D)It provides random timing for data transfer.

3. Asynchronous data transfer is characterized by:

A)The use of a clock signal to control timing.

B)Data transfer without the need for synchronization.
C)The initiation of data transfer by external events.
D)Random timing for data transfer.

4. Which statement best describes synchronous communication?

A)Data is transferred without any timing reference.

B)Data transfer relies on a shared clock signal.
C)Data is transferred asynchronously.
D)Data transfer is initiated by external events.
5. Asynchronous communication is advantageous because:

A)It eliminates the need for synchronization.

B)It allows for faster data transfer rates.
C)It requires a shared clock signal for proper operation.
D)It ensures precise timing control.

6. What is the primary disadvantage of asynchronous data transfer?

A)It requires a clock signal for synchronization.

B)It is slower compared to synchronous data transfer.
C)It is more susceptible to timing errors.
D)It requires external events to initiate data transfer.

7. In synchronous data transfer, what is the key factor that ensures proper synchronization?

A)The absence of a clock signal.

B)External events triggering data transfer.
C)A shared clock signal controlling timing.
D)Random timing for data transfer.

8. Which type of data transfer is more commonly used in digital systems?

A)Asynchronous
B)Synchronous
C)Both are equally common
D)Neither, they are rarely used
9. Which of the following is not a function of I/O interfaces?
a)Data transfer
b)Address generation
c)Error detection
d)Control signal generation

10. What is the primary purpose of I/O interfaces in a computer system?

a)To provide communication between CPU and memory
b)To provide communication between CPU and I/O devices
c)To execute arithmetic and logical operations
d)To perform data storage operations

11. The purpose of handshaking signals in I/O interfaces is to:

a)Synchronize the data transfer between sender and receiver
b)Provide power to the connected devices
c)Regulate the clock frequency of the system
d)Identify the type of I/O device connected to the system

12. Which of the following is an essential component of an I/O interface?

a)CPU
b)Memory
c)I/O ports
d)Operating system
 Overview

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor
 Modes of Transfer

 Binary information received from external device is usually

stored in memory.
 Information transferred from central computer into an external
device originates in the memory unit.
The CPU merely execute I/O instructions and may accept data
temporarily but ultimate source or destination is the Memory Unit.
Data transfer between central computer and I/O devices may be
handled in a variety of modes. Some modes use CPU as
intermediate path and others transfer data directly to and from
memory unit.
Data Transfer to or from peripheral can be handled in one of
three possible modes :
 Programmed I/O
 Interrupt-Initiated I/O
 Direct Memory Access (DMA)
Input/output Organization 28

Modes of Transfer – Programmed I/O

 Programmed I/O
- Programmed I/O operations are the result of I/O
Instructions written in computer program. Each data item
transfer is initiated by an instruction in the program.
- Usually, transfer is to and from a CPU register to
peripheral. Other instructions are needed to transfer data
to and from CPU and Memory
- Transferring data under program control requires
constant monitoring of the peripheral by CPU.
• In programmed I/O method, CPU stays in a
program loop until the I/O unit indicated that it is
ready for data transfer. This is a time consuming
process since it keeps the processor busy
needlessly. It can be avoided by using Interrupt
facility and special commands to inform the
interface to issue an interrupt request signal
when data are available for the device.
Interrupted I/O
DMA
 Priority Interrupts

Priority
- Determines which interrupt is to be served first when two or more requests
are made simultaneously
- Also determines which interrupts are permitted to interrupt the computer while
another is being serviced
- Higher priority interrupts can make requests while servicing a lower priority
interrupt

A priority interrupt is a system that establishes priority over the

various sources to determine
- which condition is to serviced first when two or more requests
arrive simultaneously
-which conditions are permitted to interrupt the computer while
another request is being serviced
 Priority Interrupts
Priority Interrupt by Software (Polling)

Polling procedure is used to identify highest priority source by software

means

- common branch address for all the interrupts

- Priority is established by the order of polling the devices(interrupt sources)

- highest priority device is tested first and if interrupt is on , control
branches to service routine for this source otherwise next lower priority
source is tested

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow
- if there are many interrupts, time required to poll may exceed time available to
service IO device
 Priority Interrupts

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts all the interrupt requests
to determine the highest priority request

- Fast since identification of the highest priority interrupt request is identified by

the hardware

- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine

- Can be addressed using serial or parallel connection of interrupt lines.

Example of serial is Daisy chaining Priority
 Hardware Priority Interrupts – Daisy Chain

VAD 1 VAD 2 VAD 3

* Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
To next - Single common line
PI PO PI PO PI PO
device * Interrupt Acknowledge Line
- Daisy-Chain

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK

-Serial connection of all device that request an interrupt

-Device with highest priority placed in first position followed by devices with lower
priority and so on.
-Interrupt generated by any device  signals low state interrupt line
-CPU responds by enabling interrupt acknowledgement (INTACK) line.
- device receives PI=1 and passes to next only when not requesting else PI=0
-Thus device with PI=1 and PO=0 is one with highest priority requesting interrupt
 Hardware Priority Interrupts – Daisy Chain

Example: Daisy chain working

Hardware Priority Interrupts – Daisy Chain
 Parallel Priority Interrupts
Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD
generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
 Priority Encoder

Determines the highest priority interrupt when more than one

interrupts take place

Priority Encoder Truth table

Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I0' I1'
0 0 0 1 1 1 1 y = I0' I1 + I0’ I2’
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3
 Interrupt Cycle

At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle

SP  SP - 1 Decrement stack pointer

M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine
 Initial and Final Operations
7
0 JMP DISK DISK Program to service
1 JMP PTR magnetic disk
VAD=00000011 3
2 JMP RDR PTR Program to service
3 JMP KBD line printer
8
1 Main program
KBD RDR Program to service
interrupt 749 current instr.
750 character reader
4
KBD Program to service
Stack
11 keyboard
5
2 255
256 Disk
interrupt 256
750

9 6 10
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system

Initial Sequence Final Sequence

[1] Clear lower level Mask reg. bits [1] IEN <- 0
[2] IST <- 0 [2] Restore CPU registers
[3] Save contents of CPU registers [3] Clear the bit in the Interrupt Reg
[4] IEN <- 1 [4] Set lower level Mask reg. bits
[5] Go to Interrupt Service Routine [5] Restore return address, IEN <- 1
In Daisy Chaining Priority if the device does
not have any pending interrupt requests then
the value of PI and PO will be

a. PI=0, PO=0
b. PI=0, PO=1
c. PI=1, PO=0
d. PI=1, PO=1
1. GATE 2016: In Programmed I/O, who typically controls the data transfer process?
• A) CPU
• B) I/O device
• C) DMA controller
• D) Interrupt controller

2. GATE 2017: What triggers the CPU to handle an I/O operation in Interrupt-driven I/O?
• A) Polling routine
• B) DMA transfer request
• C) System call
• D) Interrupt request

3. GATE 2018: Which mode of data transfer is most suitable for devices requiring minimal CPU intervention?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O

4. GATE 2019: What is the primary function of the DMA controller in Direct Memory Access (DMA)?
• A) Initiates I/O operations
• B) Manages data transfer between I/O devices and memory
• C) Controls interrupt handling
• D) Performs arithmetic and logical operations

5. GATE 2020: In DMA, what does the CPU primarily do during data transfer?
• A) Initiates the transfer
• B) Controls the flow of data
• C) Relinquishes control of the system bus
• D) Determines the priority of I/O operations
6. GATE 2017: Which mode of data transfer is most suitable for transferring large data blocks between memory and I/O devices?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O

7. GATE 2019: What is the primary advantage of Interrupt-driven I/O over Programmed I/O?
• A) Lower CPU overhead
• B) Higher data transfer rates
• C) Simpler implementation
• D) Reduced latency

8. GATE 2018: Which statement best describes Programmed I/O transfer mechanism?
• A) CPU initiates and controls data transfer.
• B) DMA controller initiates and controls data transfer.
• C) I/O device initiates and controls data movement.
• D) Interrupt controller initiates and controls data transfer.

9. GATE 2020: Which mode of data transfer allows the CPU to be free from handling I/O operations once initiated?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O

10. GATE 2019: In DMA, which component temporarily takes control of the system bus for data transfer?
• A) CPU
• B) Memory
• C) DMA controller
• D) I/O device
11. GATE 2018: Which mode of data transfer is commonly used for high-speed peripherals like disk drives and network interfaces?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O

12. GATE 2017: Which of the following statements about Interrupt-driven I/O is true?
• A) It requires constant polling by the CPU.
• B) It allows the CPU to perform other tasks during I/O operations.
• C) It involves direct access to memory without CPU intervention.
• D) It is slower compared to Programmed I/O.

13. GATE 2016: Which mode of data transfer is most suitable for devices requiring minimal CPU intervention?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O

14. GATE 2019: What triggers the CPU to handle an I/O operation in Interrupt-driven I/O?
• A) Polling routine
• B) DMA transfer request
• C) System call
• D) Interrupt request

15. GATE 2018: Which mode of data transfer allows the CPU to be free from handling I/O operations once initiated?
• A) Programmed I/O
• B) Interrupt-driven I/O
• C) Direct Memory Access (DMA)
• D) Memory-mapped I/O
16. (GATE 2016) In computer architecture, which of the following is true about a daisy chain interrupt priority resolver?

a)It assigns the highest priority to the device connected at the end of the chain.
b)It assigns the highest priority to the device connected at the beginning of the chain.
c)It assigns priority to devices based on their physical proximity to the CPU.
d)It assigns equal priority to all devices in the chain.

17. (GATE 2018) Which of the following is NOT true regarding daisy-chaining of interrupt vectors?

a)It reduces the number of wires required to connect multiple devices to a CPU.
b)It simplifies the process of adding or removing devices from the system.
c)It allows for prioritization of interrupts based on their position in the chain.
d)It increases the complexity of the interrupt handling circuitry.

18. (GATE 2019) In a computer system with daisy-chained interrupt structure, an interrupt request from a device with a higher priority ca
be serviced

a) after servicing the lower priority interrupts.

b) immediately, regardless of the priorities of other interrupting devices.
c) only when no interrupt of lower priority is being serviced.
d) based on a round-robin scheduling algorithm.
Input/Output Organization 49

Overview

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor
Input/Output Organization 50

Direct Memory Access

* Block of data transfer between high speed devices like Disk and Memory
* DMA controller - Interface which takes over the buses to manage the transfer directly between
Memory and I/O Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory address and the block size (number of
words)
Fig 1: CPU bus signals for DMA transfer
Address bus
ABUS
Bus request BR DBUS Data bus
CPU
Bus granted BG RD Read
WR Write Fig 2: Block diagram of DMA controller

Data bus Data bus Address bus

buffers buffers
Address register:
Contains an address to specify

Internal Bus
DMA select DS
Desired location in memory Address register
RS
Word count register
Read RD Word count register
Holds no. of words to be transferred Write WR Control
logic
Control register Bus request BR Control register
Specifies the mode of transfer
Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device
Input/Output Organization 51

Direct Memory Access

RD and WR is bidirectional

When BG=0 CPU can communicate with DMA Register

When BG=1 CPU left the buses and DMA can communicate directly with memory

DMA Transfer can be made in several ways

(1)Burst Transfer : a block sequence consisting of memory words is transferred

in continuous burst while the DMA controller is master of memory
bus

- This mode of transfer is needed for fast devices such as magnetic

disk where data transmission cannot be stopped or slowed down
until an entire block is transferred

(2) Cycle stealing : Alternative technique called cycle stealing allows DMA controller to
transfer one data word at time after which it must return control of
the buses to the CPU.

- CPU merely delays its operation for one memory cycle to allow the
direct memory I/O transfer to “steal” one memory cycle
Input/Output Organization 52

DMA I/O Operation

DMA is first initialized by CPU. After that DMA starts and continues to transfer data
between memory and peripheral unit until an entire block is transferred.

CPU initializes the DMA by sending following information through data bus:

(1) Starting address of the memory block (for read/write)

(2) Word Count (no. of words in memory block)

(3) Control to specify mode of transfer (E.g. read/write)

(4) A control to start DMA Transfer

Input/Output Organization 54

DMA Transfer

Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data

Read control

Write control

Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS DMA I/O
Controller Peripheral
BR device
BG DMA request

Interrupt
Input/Output Organization 55

I/O Processor - Channel

Channel
- Processor with direct memory access capability that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Unlike DMA Controller, IOP can fetch and execute its own instruction
- IOP Instructions (Commands) specially designed to facilitate I/O transfer.

- Data gathered in IOP at device rate and bit capacity while CPU executing own program
- Transfer between IOP and Device similar to Programmed I/O and
transfer between IOP and Memory similar to DMA
- CPU is master while IOP is slave processor
- CPU initiates the channel by executing a channel I/O class instruction and once initiated,
channel operates independent of the CPU

Central
processing
unit (CPU)
Memory Bus

Peripheral devices
Memory
unit PD PD PD PD
Input-output
processor
(IOP) I/O bus