UNIT 4

Peripheral Devices and their

Characteristics
I/O Organization
I/O Organization

The Input / output organization of computer depends

upon the size of computer and the peripherals
connected to it. The I/O Subsystem of the computer,
provides an efficient mode of communication
between the central system and the outside
environment.
I/O Organization
The most common input output devices are:
i) Monitor
ii) Keyboard
iii) Mouse
iv) Printer
v) Magnetic tapes
The devices that are under the direct control of the computer are
said to be connected online.
Peripheral devices
 Peripheral (or I/O Device)
 Input or Output devices attached to the computer
 Monitor (Visual Output Device) : CRT, LCD
 KBD (Input Device) : light pen, mouse, touch screen, joy

stick, digitizer
 Printer (Hard Copy Device) : Dot matrix (impact), thermal,

ink jet, laser (non-impact)

 Storage Device : Magnetic tape, magnetic disk, optical disk
Input - Output Interface

Input Output Interface provides a method for

transferring information between internal storage and
external I/O devices. Peripherals connected to a
computer need special communication links for
interfacing them with the central processing unit.
COMMUNICATION BETWEEN CPU, MEMORY AND I/O
DEVICES
COMMUNICATION BETWEEN CPU, MEMORY AND I/O
DEVICES
Bus
 A bus is a bunch of wires through which data or
address or control signals flow.
 The microprocessor communicates with the memory
and the Input/Output devices via the three buses, viz.,
data bus, address bus and control bus.
 Data flow through the DB, while address comes out
of the AB and CB controls the activities of the
microprocessor system at any instant of time.
Input - Output Interface

The purpose of communication link is to

resolve the differences that exist between the
central computer and each peripheral.
 The Major Differences are:-
1. Peripherals are electromechnical and
electromagnetic devices and their manner of operation of
the CPU and memory, will differ. Therefore, a conversion
of signal values may be needed.
2. The data transfer rate of peripherals is usually slower than
the transfer rate of CPU and consequently, a
synchronization mechanism may be needed.
The Major Differences are:-

3. Data codes and formats in the peripherals differ

from the word format in the CPU and memory.
4. The operating modes of peripherals are different
from each other and must be controlled so as not to
disturb the operation of other peripherals connected
to the CPU.
Input - Output Interface

To Resolve these differences, computer systems

include special hardware components between the
CPU and Peripherals to supervises and synchronizes
all input and out transfers. These components are
called Interface Units because they interface between
the processor bus and the peripheral devices.
I/O BUS and Interface Module
 It defines the typical link between the processor and several
peripherals.
 The I/O Bus consists of data lines, address lines and control lines.
 The I/O bus from the processor is attached to all peripherals interface.
 To communicate with a particular device, the processor places a device
address on address lines.

Interface Module
I/O BUS and Interface Module
 Each Interface decodes the address and control received from
the I/O bus, interprets them for peripherals and provides signals
for the peripheral controller.
 It is also synchronizes the data flow and supervises the
transfer between peripheral and processor.
 Each peripheral has its own controller. For example, the
printer controller controls the paper motion, the print timing.
I/O BUS and Interface Module
The control lines are referred as an I/O command. The
commands are as following:
Control command- A control command is issued to
activate the peripheral and to inform it what to do.
Status command- A status command is used to test
various status conditions in the interface and the
peripheral.
I/O BUS and Interface Module
Output data command- A data output command
causes the interface to respond by transferring
data from the bus into one of its registers.
Input data command- The data input command is the
opposite of the data output. In this case the
interface receives on item of data from the
peripheral and places it in its buffer register.
I/O BUS and Interface Module
Data
Processor Address

Control

Interface Interface Interface

Keyboard
and Printer Magnetic
display disk
terminal

Connection of I/O bus to input-output devices

I/O Versus Memory Bus
To communicate with I/O, the processor must communicate with the memory
unit. Like the I/O bus, the memory bus contains data, address and read/write
control lines. There are 3 ways that computer buses can be used to
communicate with memory and I/O:
i. Use two Separate buses , one for memory and other for I/O.
ii. Use one common bus for both memory and I/O but separate
control lines for each.
iii. Use one common bus for memory and I/O with common control lines.
I/O Processor
 In the first method, the computer has independent sets of
data, address and control buses one for accessing memory and
other for I/O. This is done in computers that provides a
separate I/O processor (IOP).
 The purpose of IOP is to provide an independent pathway
for the transfer of information between external device and
internal memory.
I/O Processor

CPU is the master while the IOP is a slave processor. The

CPU performs the tasks of initiating all operations.
The operations include
 Starting an I/O transfer
 Testing I/O status conditions needed for making
decisions on various I/O activites.

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Asynchronous Data Transfer
 This Scheme is used when speed of I/O devices do not match with
microprocessor, and timing characteristics of I/O devices is not predictable.
 In this method, process initiates the device and check its status. As a
result, CPU has to wait till I/O device is ready to transfer data. When device
is ready CPU issues instruction for I/O transfer. In this method two types of
techniques are used based on signals before data transfer.

i. Strobe Control

ii. Handshaking
Strobe Signal

The strobe control method of Asynchronous data

transfer employs a single control line to time each
transfer. The strobe may be activated by either the
source or the destination unit.
Data Transfer Initiated by Source Unit

Data Bus
Source Destination
Strobe Unit
Unit

(a) Block Diagram

Data
Valid data

Strobe

(b) Timing Diagram

Source-Initiated strobe for Data Transfer

Data Transfer Initiated by Source Unit
In the block diagram fig. (a), the data bus carries the binary information from
source to destination unit. Typically, the bus has multiple lines to transfer an
entire byte or word. The strobe is a single line that informs the destination unit
when a valid data word is available.

The timing diagram fig. (b) the source unit first places the data on the
data bus. The information on the data bus and strobe signal remain in the active
state to allow the destination unit to receive the data.
Data Transfer Initiated by Destination Unit

Data Bus
Source Destination
Strobe Unit
Unit

(a) Block Diagram

Data
Valid data

Strobe

(b) Timing Diagram

Destination-Initiated strobe for Data Transfer

Data Transfer Initiated by Destination Unit

In this method, the destination unit activates the strobe pulse, to

informing the source to provide the data. The source will respond by
placing the requested binary information on the data bus.

The data must be valid and remain in the bus long enough
for the destination unit to accept it. When accepted the destination
unit then disables the strobe and the source unit removes the data
from the bus.
Disadvantage of Strobe Signal
The disadvantage of the strobe method is that, the source unit
initiates the transfer has no way of knowing whether the
destination unit has actually received the data item that was
places in the bus. Similarly, a destination unit that initiates the
transfer has no way of knowing whether the source unit has
actually placed the data on bus. The Handshaking method
solves this problem.
Handshaking

The handshaking method solves the problem of strobe

method by introducing a second control signal that
provides a reply to the unit that initiates the transfer.
 Principle of Handshaking
The basic principle of the two-wire handshaking method of data
transfer is as follow:

One control line is in the same direction as the data flows in the bus
from the source to destination. It is used by source unit to inform the
destination unit whether there a valid data in the bus. The other
control line is in the other direction from the destination to the
source. It is used by the destination unit to inform the source whether
it can accept the data. The sequence of control during the transfer
depends on the unit that initiates the transfer.
Source Initiated Transfer using Handshaking
The sequence of events shows four possible states that the
system can be at any given time. The source unit initiates
the transfer by placing the data on the bus and enabling
its data valid signal. The data accepted signal is activated
by the destination unit after it accepts the data from the
bus. The source unit then disables its data accepted
signal and the system goes into its initial state.
 Handshaking
Data Bus

Source Unit Data Valid Destination

Unit
Data accepted

(a) Block Diagram

Source unit Destination Unit
Place the data on bus.
Enable data Valid. Accept data from bus.
Enable data accepted.
Disable data valid.
Invalidate data on bus. Disable data accepted.
Ready to accept data.

(b) Sequence of events

Destination Initiated Transfer Using Handshaking
The name of the signal generated by the destination unit has been
changed to ready for data to reflects its new meaning. The source
unit in this case does not place data on the bus until after it
receives the ready for data signal from the destination unit. From
there on, the handshaking procedure follows the same pattern as in
the source initiated case.

The only difference between the Source Initiated and the

Destination Initiated transfer is in their choice of Initial sate.
 Data Bus

Source Data Valid Destination

Unit Unit
Ready for data

(a) Block Diagram

Destination Unit
Source unit
Ready to accept data.
Place the data on bus. Enable ready for data.
Enable data Valid.

Disable data valid. Accept data from bus.

Disable ready for data.
Invalidate data on bus.

(b) Sequence of events

Destination-Initiated transfer using Handshaking
Advantage of the Handshaking method
 The Handshaking scheme provides degree of flexibility and
reliability because the successful completion of data transfer
relies on active participation by both units.

 If any of one unit is faulty, the data transfer will not be

completed. Such an error can be detected by means of a
Timeout mechanism which provides an alarm if the data is not
completed within time.
Asynchronous Serial Transmission
The transfer of data between two units is serial or
parallel.
 In parallel data transmission, n bit in the message must
be transmitted through n separate conductor path.
 In serial transmission, each bit in the message is sent in
sequence one at a time. (one bit at a time)
Parallel transmission is faster but it requires many wires.
It is used for short distances and where speed is
important. Serial transmission is slower but is less
expensive.
 In Asynchronous serial transfer, each bit of message is sent a
sequence at a time, and binary information is transferred only
when it is available. When there is no information to be
transferred, line remains idle.
In this technique each character consists of three points :

i. Start bit

ii. Character bit

iii. Stop bit

 Asynchronous Serial Transmission
i. Start Bit- First bit, called start bit is always zero and used to
indicate the beginning character.

ii. Stop Bit- Last bit, called stop bit is always one and used to
indicate end of characters. Stop bit is always in the 1- state and
frame the end of the characters to signify the idle or wait state.

iii. Character Bit- Bits in between the start bit and the stop bit
are known as character bits. The character bits always follow
the start bit.
Asynchronous Serial Transmission

0 1 1 0 0 0 1 0 1

Start Stop
bit Character bits bits

Asynchronous Serial Transmission

Asynchronous Serial Transmission
Serial Transmission of Asynchronous is done by two ways:

a) Asynchronous Communication Interface

b) First In First out Buffer

 Asynchronous Communication Interface
It works as both a receiver and a transmitter. Its operation is
initialized by CPU by sending a byte to the control register.

The transmitter register accepts a data byte from CPU through the
data bus and transferred to a shift register for serial transmission.

The receive portion receives information into another shift register,

and when a complete data byte is received it is transferred to
receiver register.
 First In First Out Buffer (FIFO)

A First In First Out (FIFO) Buffer is a memory unit

that stores information in such a manner that the first
item is in the item first out. A FIFO buffer comes
with separate input and output terminals. The
important feature of this buffer is that it can input
data and output data at two different rates.
First In First Out Buffer (FIFO)
When placed between two units, the FIFO can accept data from
the source unit at one rate, rate of transfer and deliver the data
to the destination unit at another rate.

If the source is faster than the destination, the FIFO is useful

for source data arrive in bursts that fills out the buffer. FIFO is
useful in some applications when data are transferred
asynchronously.
Modes of Data Transfer
Transfer of data is required between CPU and peripherals or
memory or sometimes between any two devices or units of
your computer system. To transfer a data from one unit to
another one should be sure that both units have
 proper connection and
 At the time of data transfer the receiving unit is not busy.

This data transfer with the computer is Internal Operation.

Modes of Data Transfer
All the internal operations in a digital system are
synchronized by means of clock pulses supplied by a
common clock pulse Generator. The data transfer can
be
i. Synchronous or
ii. Asynchronous
Modes of Data Transfer
When both the transmitting and receiving units use
same clock pulse then such a data transfer is called
Synchronous process. On the other hand, if the there
is not concept of clock pulses and the sender operates
at different moment than the receiver then such a data
transfer is called Asynchronous data transfer.
Modes of Data Transfer
The data transfer can be handled by various modes. some of the
modes use CPU as an intermediate path, others transfer the data
directly to and from the memory unit and this can be handled by 3
following ways:

i. Programmed I/O

ii. Interrupt-Initiated I/O

iii. Direct Memory Access (DMA)

Input/Output (cont’d)
 Several ways of transferring data
 Programmed I/O
 Program uses a busy-wait loop

 Anticipated transfer

 Interrupt-driven I/O
 Interrupts are used to initiate and/or terminate data transfers

 Powerful technique

 Handles unanticipated transfers

 Direct memory access (DMA)

 Special controller (DMA controller) handles data transfers

 Typically used for bulk data transfer

Programmed I/O (1)
 CPU has direct control over I/O
 Sensing status
 Read/write commands
 Transferring data
 CPU waits for I/O module to complete
operation
 Wastes CPU time
Programmed I/O (2)
 CPU requests I/O operation
 I/O module performs operation
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
 I/O module does not interrupt CPU
 CPU may wait or come back later
Programmed I/O (3)
 I/O module performs the action
 Sets the appropriate bits in the I/O status
register
 CPU checks status bits periodically
 No interrupts occur
 Processor checks status until operation is
complete
 Programmed I/O
CPU issues the read or write
command to I/O module

I/O module informs about its

status to CPU

Status Error
Busy

Ready
CPU reads word from I/O module & writes it to memory or
CPU reads word from memory & writes it to I/O module

Is
transfer

NO complete

yes
Drawback of the Programmed I/O
 The CPU has to monitor the units all the times when the
program is executing.
 Thus the CPU stays in a program loop until the I/O unit
indicates that it is ready for data transfer.
 A time consuming process and the CPU time is wasted a lot
in keeping an eye to the execution of program.
 To remove this problem an Interrupt facility and
special commands are used.
Programmed Input/Output
 Several ways of mapping I/O
 Memory-mapped I/O
 Same address space
 Reading and writing similar to memory read/write

 Uses same memory read and write signals

 Most processors use this I/O mapping

 Isolated I/O
 Separate I/O address space

 Separate I/O read and write signals are needed

 Pentium supports isolated I/O

 Also supports memory-mapped I/O

Interrupt-Initiated I/O

Interrupts are used to initiate and/or

terminate data transfers
Basic Instruction Cycle
 Fetch and Execute
 Fetch Cycle
It includes certain steps like:
1. Fetching Instruction to be executed
2. Decoding of instruction
3. Reading the operands to be operated
 · Execute Cycle:

It includes steps like:

1. Executing or processing the operands in ALU
2. Storing the result at the destination
 Interrupt
Interrupt is mechanism of interrupting the
current execution of a process.
Interrupt Stage
 Processor checks for interrupts
 If interrupt occurred
 Suspend execution of program
 Execute interrupt-handler routine
 Afterwards control may be returned to
suspended program
Instruction Cycle with Interrupts
Interrupt-Initiated I/O
 In this method an interrupt facility an interrupt command
is used to inform the device about the start and end of
transfer.
 In the meantime the CPU executes other program.
 When the interface determines that the device is ready for
data transfer it generates an Interrupt Request and sends
it to the computer.
Interrupt-Initiated I/O
 One of the bus control lines, called an
interrupt-request line, is usually dedicated for
this purpose.
 An interrupt-service routine usually is
needed and is executed when an interrupt
request is issued.
Interrupt-Initiated I/O
When the CPU receives such an signal, it temporarily stops the
execution of the program and branches to a service program to
process the I/O transfer and after completing it returns back to
task, what it was originally performing.
Program Flow of Control
Program Flow of Control
Ways to choose service routine

Service routines of interrupt initiated I/O can

be chosen in two ways.
 Vectored interrupt
 Non-vectored interrupt
Ways to choose service routine
 There are two ways of redirecting the execution to
the ISR (Interrupt service routine) depending on
whether the interrupt is vectored or non-vectored.
 Vectored: The address of the subroutine is
already known to the Microprocessor
 Non Vectored: The device will have to supply
the address of the subroutine to the
Microprocessor
Direct Memory Access (DMA)
 In the Direct Memory Access (DMA) the interface transfer the data
into and out of the memory unit through the memory bus.

 The transfer of data between a fast storage device such as magnetic

disk and memory is often limited by the speed of the CPU.

 Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of transfer.
This transfer technique is called Direct Memory Access (DMA).
Computer System with DMA
Direct Memory Access (DMA)

During the DMA transfer, the CPU is idle and has

no control of the memory buses. A DMA Controller
takes over the buses to manage the transfer directly
between the I/O device and memory.
 Direct Memory Access (DMA)
The CPU may be placed in an idle state in a variety of ways. One
common method extensively used in microprocessor is to disable the
buses through special control signals such as:
 Bus Request (BR)
 Bus Grant (BG)
These two control signals in the CPU that facilitates the DMA
transfer. The Bus Request (BR) input is used by the DMA controller
to request the CPU. When this input is active, the CPU terminates the
execution of the current instruction and places the address bus, data
bus and read write lines into a high Impedance state. High
Impedance state means that the output is disconnected.
 Direct Memory Access (DMA)
ABUS Address Bus
Bus Request BR

DBUS Data Bus

High Impedance
(disable) when BG
is enable
RD Read

Bus Grant BG
WR Write

CPU bus Signals for DMA Transfer

Direct Memory Access (DMA)

The CPU activates the Bus Grant (BG) output to

inform the external DMA that the Bus Request (BR)
can now take control of the buses to conduct memory
transfer without processor.
Direct Memory Access (DMA)

When the DMA terminates the transfer, it disables the

Bus Request (BR) line. The CPU disables the Bus
Grant (BG), takes control of the buses and return to
its normal operation.
Direct Memory Access (DMA)

The transfer can be made in several ways that are:

i. DMA Burst

ii. Cycle Stealing

Direct Memory Access (DMA)
i) DMA Burst :- In DMA Burst transfer, a block sequence
consisting of a number of memory words is transferred in
continuous burst while the DMA controller is master of the
memory buses.

ii) Cycle Stealing :- Cycle stealing allows the DMA controller

to transfer one data word at a time, after which it must
returns control of the buses to the CPU.
DMA Controller

The DMA controller needs the usual circuits of an interface to

communicate with the CPU and I/O device. The DMA
controller has three registers:

i. Address Register

ii. Word Count Register

iii. Control Register

DMA Controller
i. Address Register :- Address Register contains an address to
specify the desired location in memory.

ii. Word Count Register :- WC holds the number of words to be

transferred. The register is incre/decre by one after each word
transfer and internally tested for zero.

iii. Control Register :- Control Register specifies the mode of

transfer.
DMA Controller
The unit communicates with the CPU via the data bus and control
lines. The registers in the DMA are selected by the CPU through the
address bus by enabling the DS (DMA select) and RS (Register
select) inputs. The RD (read) and WR (write) inputs are
bidirectional.
When the BG (Bus Grant) input is 0, the CPU can
communicate with the DMA registers through the data bus to read
from or write to the DMA registers. When BG =1, the DMA can
communicate directly with the memory by specifying an address in
the address bus and activating the RD or WR control.
DMA Transfer

When BG = 0 the RD and WR are input lines allowing the CPU to

communicate with the internal DMA registers. When BG=1, the RD
and WR are output lines from the DMA controller to the random
access memory to specify the read or write operation of data.
Address Bus

Data bus Address bus buffers

Data bus
buffers
I
N
T
DMA Select DS E
Address Register
R
Register Select RS N
A Word Count Register
Read RD L
B
Write WR U
S Control Register
Bus Request BR

Bus Grant BG DMA Request

Interrupt Interrupt to I/O devices
DMA Acknowledgment

Block Diagram of DMA Controller

 Brief Summary
 Interface is the point where a connection is made between two different parts
of a system.
 The strobe control method of Asynchronous data transfer employs a single
control line to time each transfer.
 The handshaking method solves the problem of strobe method by introducing
a second control signal that provides a reply to the unit that initiates the
transfer.
 Brief Summary
 Programmed I/O mode of data transfer ,the operations are the results in
I/O instructions which is a part of computer program.
 In the Interrupt Initiated I/O method , A interrupt command is used to
inform the device about the start and end of transfer.
 In the Direct Memory Access (DMA) The interface transfer the data into
and out of the memory unit through the memory bus.
Pros and Cons of DMA
 Advantages of DMA
 Computer system performance is improved by direct transfer
of data between memory and I/O devices, bypassing the CPU.
 CPU is free to perform operations that do not use system buses.

 Disadvantages of DMA
 In case of Burst Mode data transfer, the CPU is rendered
inactive for relatively long periods of time.
Privileged and non privileged
instructions
 Non-privileged
 Processor-memory
 Data Processing

 Arithmetic
 Shift Operations

 Flow control
 Branch
 Subroutine linkage

 Privileged
 Processor-I/O
 Control
Interrupts
Interrupts
 In program-controlled I/O, when the processor continuously
monitors the status of the device, it does not perform any useful
tasks.
 An alternate approach would be for the I/O device to alert the
processor when it becomes ready.
 Do so by sending a hardware signal called an interrupt to the
processor.
 At least one of the bus control lines, called an interrupt-request
line is dedicated for this purpose.
 Processor can perform other useful tasks while it is waiting for the
device to be ready.
Interrupts (contd..)
Program 1 Interrupt Service routine

1
2

Interrupt
occurs i
here
i +1

M
 Processor is executing the instruction located
at address i when an interrupt occurs.
 Routine executed in response to an interrupt
request is called the interrupt-service routine.
 When an interrupt occurs, control must be
transferred to the interrupt service routine.
 But before transferring control, the current
contents of the PC (i+1), must be saved in a
known location.
 This will enable the return-from-interrupt
instruction to resume execution at i+1.
 Return address, or the contents of the PC
are usually stored on the processor stack.
Interrupts (contd..)
Treatment of an interrupt-service routine is
very similar to that of a subroutine.
However there are significant differences:
 A subroutine performs a task that is required by the calling program.
 Interrupt-service routine may not have anything in common with the program it
interrupts.
 Interrupt-service routine and the program that it interrupts may belong to
different users.
 As a result, before branching to the interrupt-service routine, not only the PC,
but other information such as condition code flags, and processor registers used
by both the interrupted program and the interrupt service routine must be
stored.
 This will enable the interrupted program to resume execution upon return from
interrupt service routine.
Interrupts (contd..)
 Saving and restoring information can be done automatically by the processor
or explicitly by program instructions.
 Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and
the start of execution of the interrupt-service routine. This delay is called
interrupt latency.
 In order to reduce the interrupt latency, most processors save only the minimal
amount of information:
 This minimal amount of information includes Program Counter and
processor status registers.
 Any additional information that must be saved, must be saved explicitly by the
program instructions at the beginning of the interrupt service routine.
Interrupts (contd..)
When a processor receives an interrupt-
request, it must branch to the interrupt service
routine.
It must also inform the device that it has
recognized the interrupt request.
This can be accomplished in two ways:
 Some processors have an explicit interrupt-acknowledge control signal for this
purpose.
 In other cases, the data transfer that takes place between the device and the
processor can be used to inform the device.
Interrupts (contd..)
Interrupt-requests interrupt the
execution of a program, and may alter the
intended sequence of events:
 Sometimes such alterations may be undesirable, and must not be
allowed.
 For example, the processor may not want to be interrupted by the
same device while executing its interrupt-service routine.
 Processors generally provide the ability to enable and disable such
interruptions as desired.
 One simple way is to provide machine instructions such as Interrupt-
enable and Interrupt-disable for this purpose.
 To avoid interruption by the same device during the execution of an
interrupt service routine:
 First instruction of an interrupt service routine can be Interrupt-
disable.
 Last instruction of an interrupt service routine can be Interrupt-
enable.
Interrupts (contd..)
Multiple I/O devices may be connected to
the processor and the memory via a bus.
Some or all of these devices may be
capable of generating interrupt requests.
 Each device operates independently, and hence no definite
order can be imposed on how the devices generate interrupt
requests?
 How does the processor know which device has generated an
interrupt?
 How does the processor know which interrupt service routine needs to
be executed?
 When the processor is executing an interrupt service routine for one
device, can other device interrupt the processor?
 If two interrupt-requests are received simultaneously, then how to
break the tie?
Interrupts (contd..)
 Consider a simple arrangement where all devices send their
interrupt-requests over a single control line in the bus.
 When the processor receives an interrupt request over this
control line, how does it know which device is requesting an
interrupt?
 This information is available in the status register of the device
requesting an interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.
 Interrupt service routine can poll the I/O devices connected to
the bus. The first device with IRQ equal to 1 is the one that is
serviced.
 Polling mechanism is easy, but time consuming to query the
status bits of all the I/O devices connected to the bus.
Interrupts (contd..)
The device requesting an interrupt may
identify itself directly to the processor.
 Device can do so by sending a special code (4 to 8 bits) the processor over the
bus.
 Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.
 The remainder of the starting address is obtained by the processor based on
other information such as the range of memory addresses where interrupt
service routines are located.
Usually the location pointed to by the
interrupting device is used to store the starting
address of the interrupt-service routine.
Interrupts (contd..)
 Previously, before the processor started executing
the interrupt service routine for a device, it disabled
the interrupts from the device.
 In general, same arrangement is used when multiple
devices can send interrupt requests to the processor.
 During the execution of an interrupt service routine of device, the processor does not
accept interrupt requests from any other device.
 Since the interrupt service routines are usually short, the delay that this causes is generally
acceptable.
 However, for certain devices this delay may not be
acceptable.
 Which devices can be allowed to interrupt a processor when it is executing an interrupt
service routine of another device?
Interrupts (contd..)
I/O devices are organized in a priority
structure:
 An interrupt request from a high-priority device is accepted while the processor
is executing the interrupt service routine of a low priority device.
A priority level is assigned to a processor that
can be changed under program control.
 Priority level of a processor is the priority of the program that is currently being
executed.
 When the processor starts executing the interrupt service routine of a device, its
priority is raised to that of the device.
 If the device sending an interrupt request has a higher priority than the
processor, the processor accepts the interrupt request.
Interrupts (contd..)
Processor’s priority is encoded in a few bits of
the processor status register.
 Priority can be changed by instructions that write into the processor status
register.
 Usually, these are privileged instructions, or instructions that can be executed
only in the supervisor mode.
 Privileged instructions cannot be executed in the user mode.
 Prevents a user program from accidentally or intentionally changing the priority
of the processor.
If there is an attempt to execute a privileged
instruction in the user mode, it causes a special
type of interrupt called as privilege exception.
 Interrupts (contd..)
IN T R 1 INTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

•Each device has a separate interrupt-request and interrupt-acknowledge

line.
•Each interrupt-request line is assigned a different priority level.
•Interrupt requests received over these lines are sent to a priority
arbitration circuit in the processor.
•If the interrupt request has a higher priority level than the priority of the
processor, then the request is accepted.
Interrupts (contd..)
 Which interrupt request does the processor accept if
it receives interrupt requests from two or more
devices simultaneously?.
 If the I/O devices are organized in a priority
structure, the processor accepts the interrupt
request from a device with higher priority.
 Each device has its own interrupt request and interrupt acknowledge line.
 A different priority level is assigned to the interrupt request line of each device.
 However, if the devices share an interrupt request
line, then how does the processor decide which
interrupt request to accept?
 Interrupts (contd..)
Polling scheme:
•If the processor uses a polling mechanism to poll the status registers of I/O devices to
determine which device is requesting an interrupt.
•In this case the priority is determined by the order in which the devices are polled.
•The first device with status bit set to 1 is the device whose interrupt request is
accepted.

Daisy chain scheme:

Processor I NTR

Device 1 Device 2 Device n

INTA
• Devices are connected to form a daisy chain.
• Devices share the interrupt-request line, and interrupt-acknowledge line is
connected to form a daisy chain.
• When devices raise an interrupt request, the interrupt-request line is activated.
• The processor in response activates interrupt-acknowledge.
• Received by device 1, if device 1 does not need service, it passes the signal to device
2.
• Device that is electrically closest to the processor has the highest priority.
 Interrupts (contd..)
•When I/O devices were organized into a priority structure, each
device had its own interrupt-request and interrupt-acknowledge
line.
•When I/O devices were organized in a daisy chain fashion, the
devices shared an interrupt-request line, and the interrupt-
acknowledge propagated through the devices.
•A combination of priority structure and daisy chain scheme can
also used. I NTR1

Device Device
INTA1
Processor

INTR p

Device Device
INTAp
Priority arbitration
circuit
•Devices are organized into groups.
•Each group is assigned a different priority level.
•All the devices within a single group share an interrupt-request line, an
connected to form a daisy chain.
Interrupts (contd..)
 Only those devices that are being used in a program should be
allowed to generate interrupt requests.
 To control which devices are allowed to generate interrupt
requests, the interface circuit of each I/O device has an interrupt-
enable bit.
 If the interrupt-enable bit in the device interface is set to 1, then the device is allowed to generate an
interrupt-request.
 Interrupt-enable bit in the device’s interface circuit determines
whether the device is allowed to generate an interrupt request.
 Interrupt-enable bit in the processor status register or the
priority structure of the interrupts determines whether a given
interrupt will be accepted.
Exceptions
 Interrupts caused by interrupt-requests sent by I/O devices.
 Interrupts could be used in many other situations where the
execution of one program needs to be suspended and execution
of another program needs to be started.
 In general, the term exception is used to refer to any event that
causes an interruption.

Interrupt-requests from I/O devices is one type of an exception.
 Other types of exceptions are:
 Recovery from errors
 Debugging
 Privilege exception
Exceptions (contd..)
 Many sources of errors in a processor. For
example:
 Error in the data stored.
 Error during the execution of an instruction.
 When such errors are detected, exception
processing is initiated.
 Processor takes the same steps as in the case of I/O interrupt-request.
 It suspends the execution of the current program, and starts executing an exception-
service routine.
 Difference between handling I/O interrupt-
request and handling exceptions due to errors:
 In case of I/O interrupt-request, the processor usually completes the execution of an
instruction in progress before branching to the interrupt-service routine.
 In case of exception processing however, the execution of an instruction in progress
usually cannot be completed.
Exceptions (contd..)
Debugger uses exceptions to provide
important features:
 Trace,
 Breakpoints.

Trace mode:
 Exception occurs after the execution of every instruction.
 Debugging program is used as the exception-service routine.

Breakpoints:
 Exception occurs only at specific points selected by the user.
 Debugging program is used as the exception-service routine.
Exceptions (contd..)
Certain instructions can be executed only when
the processor is in the supervisor mode. These
are called privileged instructions.
If an attempt is made to execute a privileged
instruction in the user mode, a privilege
exception occurs.
Privilege exception causes:
 Processor to switch to the supervisor mode,
 Execution of an appropriate exception-servicing routine.
 Processes: The Process Model

 Multiprogramming of four programs

 Conceptual model of 4 independent, sequential processes
 Only one program active at any instant

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 Processes and programs
The difference between a process and a program:
 Baking analogy:
o Recipe = Program
o Baker = Processor
o Ingredients = data
o Baking the cake = Process
 Interrupt analogy
o The baker’s son runs in with a wounded hand
o First aid guide = interrupt code

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Process Creation
?When is a new process created

1. System initialization (Daemons)

2. Execution of a process creation system call by a
running process
3. A user request to create a process
4. Initiation of a batch job

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Process Termination
?When does a process terminate

1. Normal exit (voluntary)

2. Error exit (voluntary)
3. Fatal error (involuntary)
4. Killed by another process (involuntary)

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Process States
 Running - actually using the CPU
 Ready – runnable, temporarily stopped to let
another process run
 Blocked - unable to run until some external event
happens

A process can block itself, but not “run” itself

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 Process State Transitions
When do these
Running
transitions
?occur
1. Process blocks for input
1
or waits for an event 2
2. End of time-slice, or
3
preemption
3. Scheduler switches back Blocked
to this process
4. Input becomes available, Ready
4
event arrives
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Amnon Meisels
120
Ben-Gurion University
Five-State Process Model
Dispatch Release
Admit
New Ready Running Exit

Time-out

Event Event
Occurs Wait

Blocked

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 Scheduling: Single Blocked Queue
Ready Queue
Dispatch Release
Admit
Processor

Time-out

Event Wait

Event
Occurs
Blocked Queue

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 Scheduling: Multiple Blocked
Queues
Ready Queue
Dispatch Release
Admit
Processor

Time-out

Event 1 Event 1 Wait

Occurs
Event 1 Queue

Event 2 Event 2 Wait

Occurs
Event 2 Queue
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Suspended Processes
 Processor is much faster than I/O so many processes
could be waiting for I/O
 Swap some of these processes to disk to free up more
memory
 Blocked state becomes blocked-suspended state when
swapped to disk, ready becomes
ready-suspended
 Two new states
o Blocked-suspended
o Ready-suspended

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 Process State Transition Diagram with Two
Suspend States
New

Admit Suspend
Admit

Activate Dispatch
Ready, Ready Running Exit
suspend
Suspend Time out

Event Event
Event
Occurs Wait
Occurs

Activate
Blocked, Blocked
suspend
Suspend Operating Systems, 2013, Meni Adler, Michael Elhadad & 125
Amnon Meisels
 Process Management Operations
Process creation and termination
 Process scheduling and dispatching
 Process switching
 Process synchronization and support for inter-
process communication

The OS maintains process data in the

Process Control Blocks (PCB)

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Process Table
 Process image consists of program (code/text), data,
stack, and attributes
 Control Attributes form the Process Control Block -
PCB
o Unique ID (may be an index into the PT)
o User ID; User group ID, Parent process ID
o process control information
o Processor state information

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127
Process Control Information
 Additional information needed by the operating system to
control and coordinate the various active processes
o Execution state: see next slide…
o Scheduling-related information - state; priority; scheduling
info
o inter-process communication - signals; pipes
o Time of next alarm
o memory management - pointers to text/data/stack
segments
o resource ownership and utilization - open files
o Process relationships: Parent, process group…
o Environment variables

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Processor State Information
 Contents of processor registers
o General registers
o Program counter
o Program Status Word (PSW)
• condition codes
• mode (user/kernel)
• status register - interrupts disabled/enabled
o Stack pointers - user and kernel stacks

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Process-State-Management
Process
Control
Block

Runnin
g
Ready
Blocked

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Memory Hierarchy
 Different storage technologies have widely
different access times.
 Faster technologies cost more per byte than
slower ones and have less capacity.
 The gap between CPU and main memory
speed is widening.
Memory Hierarchy
 At the highest level (L0) are a small number of fast CPU
registers that the CPU can access in a single clock cycle.
 Next are one or more small to moderate-sized SRAM-
based cache memories that can be accessed in a few CPU
clock cycles.
 These are followed by a large DRAM-based mainmemory
that can be accessed in tens to hundreds of clock cycles.
 Next are slow but enormous local disks.
 Finally, some systems even include an additional level of
disks on remote servers that can be accessed over a
network.
Cache Memory
LOAD-THROUGH
STORE-THROUGH
 Load-Through : When the CPU needs to read a
word from the memory, the block containing the
word is brought from MM to CM, while at the same
time the word is forwarded to the CPU.

 Store-Through : If store-through is used, a word to

be stored from CPU to memory is written to both
CM (if the word is in there) and MM. By doing so, a
CM block to be replaced can be overwritten by an
in-coming block without being saved to MM.
WRITE METHODS
 Note: Words in a cache have been viewed simply
as copies of words from main memory that are
read from the cache to provide faster access.
However this view point changes.
 There are 3 possible write actions:
 Write the result into the main memory
 Write the result into the cache
 Write the result into both main memory and cache
memory
 Write Through: A cache architecture in which
data is written to main memory at the same time
as it is cached.

 Write Back / Copy Back: CPU performs write only

to the cache in case of a cache hit. If there is a
cache miss, CPU performs a write to main
memory.
When the cache is missed :

 Write Allocate: loads the memory block into

cache and updates the cache block

 No-Write allocation: this bypasses the cache

and writes the word directly into the
memory.
Direct Mapping Cache
Organization
Cache Read/Write