unit4-part1of2
unit4-part1of2
Input-Output Organization
UNIT 4
Input-Output Interface
Modes of Transfer
Priority Interrupt
Input-Output Processor
2
– I/O Subsystem
• Provides an efficient mode of communication between the
central system and the outside environment
Peripheral Devices
• Devices that are under direct control of computer are said to be
connected on-line.
A- ITEMS
B- SORCES
C- PERIPHERALS
D- GADGETS
5
• ASCII Code :
• It uses 7 bits to code 128 characters (94 printable and 34 non printing)
• 7 bit - 00 - 7F ( 0 - 127 )
I/O Interface
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
(1) Peripherals – Electromechanical or Electromagnetic
Devices CPU or Memory - Electronic Device
– Conversion of signal values required
(2) Data Transfer Rate
• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
– Some kinds of Synchronization mechanism may be needed
Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal
Interface :
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
4 types of command interface can receive : control, status, data o/p and data i/p
11
• Status command : used to test various status condition in the interface and
the peripherals
• data i/p command : interface receives an item of data from the peripheral and
places it in its buffer register.
12
(1) use two separate buses, one to communicate with memory and
the other with I/O interfaces
- Computer has independent set of data, address and control bus one for
accessing memory and another I/O.
- done in computers that have separate IOP other than CPU.
(2) Use one common bus for memory and I/O but separate control lines
for each
(3) Use one common bus for memory and I/O with common control
lines for both
13
I/O Interface
Port A I/O data
register
Bidirectional
Bus
data bus buffers
Port B I/O data
register
Internal bus
CPU
Chip select I/O
CS
Register select
Control Control Device
RS1
Register select Timing register
RS0 and
I/O read Control
RD Status
I/O write Status
WR register
A-address bus
B-i/o bus
C-bidirectional data bus
D-control bus
There are ….. types of commands that an interface
may receive.
A- 3
B-4
C-5
Data Transfer
Synchronous Data Transfer:
Clock pulses are applied to all registers within a unit and all data
transfer among internal registers occur simultaneously during the
occurrence of a clock pulse.
Two units such as CPU and I/O Interface are designed independently
of each other. If the registers in the interface share a common clock
with CPU registers, the transfer between the two is said to be
synchronous.
Asynchronous Data Transfer:
Internal timing in each unit (CPU and Interface) is independent.
Each unit uses its own private clock for internal registers.
2
2
1
Timeout : If the return handshake signal does not respond within a given time period,
the unit assumes that an error has occurred.
– Asynchronous Serial Transfer
• Synchronous transmission :
– The two unit share a common clock frequency
– Bits are transmitted continuously at the rate dictated by the clock
pulses
• Asynchronous transmission :
– Binary information sent only when it is available and line remain
idle otherwise
– Special bits are inserted at both ends of the character code
– Each character consists of three parts :
» 1) start bit : always “0”, indicate the beginning of a character
» 2) character bits : data
» 3) stop bit : always “1”
• Asynchronous transmission rules :
– ① When a character is not being sent, the line is kept in
the 1-state
– ② The initiation of a character transmission is detected
from the start bit, which is always “0”
– ③ The character bits always follow the start bit
– ④ After the last bit of the character is transmitted, a stop
bit is detected when the line returns to the 1-state for at
least one bit time
• Baud Rate : Data transfer rate in bits per second
– 10 character per second with 11 bit format = 110 bit per
second
26
Chip select
CS
Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and
RD and clock 1 0 WR Transmitter register
Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register
Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register
- Receives serial information into another shift
register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character,
whether to generate and check parity, and no. of stop
bits