Digital Logic Design

Chapter 6 Lecture Notes

By: Dr. A. Sattar Chan

 Summary
Half-Adder

Basic rules of binary addition are performed by a

Inputs Outputs
half adder, which has two binary inputs (A and B)
A B Cout S
and two binary outputs (Carry out and Sum). 0 0
0 0
0 1 0 1
The inputs and outputs can be summarized on 1 0 0 1
a truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

S S
A S
A
Cout
B Cout B

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder
Inputs Outputs
A B Cin Cout S
By contrast, a full adder has three binary
0 0 0 0 0
inputs (A, B, and Carry in) and two binary 0 0 1 0 1
outputs (Carry out and Sum). The truth table 0 1 0 0 1
summarizes the operation. 0 1 1 1 0
1 0 0 0 1
A full-adder can be constructed from two 1 0 1 1 0
half adders as shown: 1 1 0 1 0
1 1 1 1 1
S S
A A S A S Sum
S
B B Cout B Cout A S
B
Cout
Cin Cin

Cout Symbol

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder
S S 0 Sum
1 A S 1 A S

0 B Cout 0 B Cout 1
For the given inputs, determine the
intermediate and final outputs of the full 1 Cout
adder. 1

The first half-adder has inputs of 1 and 0; therefore the Sum

=1 and the Carry out = 0.

The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the
Carry out = 1.

The OR gate has inputs of 1 and 0, therefore the final carry out = 1.

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder

Notice that the result from the previous example can be read directly on the
truth table for a full adder.

Inputs Outputs
A B Cin Cout S
S S 0 Sum
0 0 0 0 0 1 A S 1 A S
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 0 B Cout 0 B Cout 1
1 0 0 0 1
1 0 1 1 0 1 Cout
1 1 0 1 0
1 1 1 1 1 1

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Two bit adder
 Summary
Parallel Adders

Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S4 S3 S2 S1

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel Adders

The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimize the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Comparators

The function of a comparator is to compare the magnitudes of two

binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
(a) Logic Symbol

(b) Logic symbol for 1-bit Comparator

4-Bit Comparator
2-Bit Comparator
 Summary
Decoders

A decoder is a logic circuit that detects the presence of a specific

combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders

Assume the output of the decoder shown is a logic 1. What

are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
The 3-Bit decoder
 Summary
Decoders

IC decoders have multiple outputs to decode any combination of inputs. For

example the binary-to-decimal decoder shown here has 16 outputs – one for
each combination of binary inputs.

Bin/Dec
0 1
For the input shown, 1 1
2 1
what is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 BCD to decimal decoder
BCD-to-decimal decoders accept a binary coded decimal input and activate one of ten possible decimal digit indications.
BCD to 7-Segment Decoder
 7-Segment Display
it is used to display the decimal numbers0 to 9. It has seven segments a,b,c,d,e,f,g
Function table for segment a
Function table for segment b
Function table for segment c
Function table for segment d
Function table for segment e
Function table for segment f
Function table for segment g
 Active low BCD to 7 segment decoder
(74LS42)
• Logic symbol

55
 Summary
Encoders

An encoder accepts an active logic level on one of its inputs and converts it to
a coded output, such as BCD or binary.

1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the
4
active digit. The basic logic diagram 5 A2
6
is shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A Decimal to BCD Encoder
 Summary
Encoders

Show how the decimal-to-BCD encoder converts the

decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0011.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
0 A2
6 0
7
8 0 0
A3
0
9

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Encoders

The 74HC147 is an example of an IC encoder. It is has ten active-LOW inputs

and converts the active input to an active-LOW BCD output.
VCC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. This means that if more (1)
3
1
(9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
input 4 output
with the highest order decimal (3)
(4)
6
8
(14)
digit will be active. (5)
7
8
(10) 9
(8)
74HC147
The next slide shows an application … GND

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
What is Gray Code? and Advantages
of Gray Code: This code belongs to a
class of codes called minimum change
code in which only one bit in the code
group changes when going from one
step to the next.
This is an un-weighted code which
means that there are no specific
weights assigned to the bit
positions. Because of this the Gray
code is not suited for arithmetic
operations but finds applications in
input/output devices and some types
of analog to digital converters (ADCs).
In Gray code, if we go from one
decimal number to next, only one bit
of the gray code changes. Because of
this feature, an amount of switching is
minimized and the reliability of the
switching systems is improved.
 Summary
Code converters

There are various code converters that change

one code to another. Two examples are the
four bit binary-to-Gray converter and the
Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Multiplexers

A multiplexer (MUX) selects one data line from two or more input lines and
routes data from the selected line to the output. The particular data line that
is selected is determined by the select inputs.

MUX
Two select lines are shown 0
S0 0
Data 1
here to choose any of the select S1
1
four data inputs.
D0 0 Data
D1 1 output
Data
D 2
inputs D2
Which data line is selected if 3 3
S1S0 = 10? D2

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Demultiplexers
 Summary
Parity Generators/Checkers

Parity is an error detection method that uses an extra

bit appended to a group of bits to force them to be
either odd or even. In even parity, the total number of
ones is even; in odd parity the total number of ones is
odd.

The ASCII letter S is 1010011. Show the parity bit for the letter
S with odd and even parity.

S with odd parity = 11010011

S with even parity = 01010011

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parity Generators/Checkers

The 74LS280 can be used to generate a parity bit or to check an incoming data
stream for even or odd parity.

Checker: The 74LS280 can test codes with up (8)

A
(9)
to 9 bits. The even output will normally be (10)
B
C
HIGH if the data lines have even parity; Data (11)
D (5) S Odd
otherwise it will be LOW. Likewise, the odd inputs (12)
(13)
E (6) S Even
output will normally be HIGH if the data lines (1)
F
G
have odd parity; otherwise it will be LOW. (2)
H
(4)
I
Generator: To generate even parity, the parity
bit is taken from the odd parity output. To
74LS280
generate odd parity, the output is taken from
the even parity output.

Floyd, Digital Fundamentals, 10 th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved