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15 - Carry Look Ahead Adder

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62 views21 pages

15 - Carry Look Ahead Adder

Uploaded by

kudesiat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Carry Look

Ahead Adder
Contents
• Basics of Binary Addition
• Ripple Adder
• Look Ahead Carry Generator
• Carry Look Ahead Adder
Binary Addition (two bits)
Inputs outputs
• When two bits A and B are added, a sum (S) and
A B C S
carry (C) are generated as per the following truth
table 0 0 0 0

0 1 0 1
• The circuit that adds two bits is known as Half
Adder. 1 0 0 1

1 1 1 0
Binary Addition ( Three bits)
• A Full adder is a circuit that adds three bits.

• A full adder has three inputs and two outputs:


• Inputs: two input bits A and B, the carry input
Cin.
• Outputs: the sum S, and the carry output Cout.
Binary Addition ( 4-bit numbers)
• At every bit position (stage), we
require to add 3 bits:
 1 bit for number X
 1 bit for number Y
 1 carry bit coming from the
previous stage
Binary Addition ( n-bit numbers)
• The binary addition of two n-bit numbers
• X (Xn-1 Xn-2…X2X1X0) and Y (Yn-1Yn-2…Y2Y1Y0)
• produces n-bit Sum (Sn-1 Sn-2 ….S2S1S0) and Carry output (CnCn-1…….C2C1) .
Binary Addition ( n-bit numbers)
Examples
Ripple Carry Adder
n full adders are cascaded to create a n-bit parallel adder.
The carry output of the stage-i is connected to the carry input of the next
stage-(i+1).

Therefore, the sum and carry at stage-(i+1) cannot be produce until the
input carry from stage-i occurs. This leads to a significant time delay in
addition process. This delay is called carry propagation delay.
4-bit binary parallel Adder
Propagation Delay

Delay is proportional to n.
Where  is the delay of basic gates (NOT, AND, and OR)
Delay in Carry and Sum output
Drawback of parallel binary
adder
• In ripple carry adders, the carry propagation time is the major
speed limiting factor due to sequential carry propagation.
• In the worst-case, carry ripples through all the stages.
• The total delay is proportional to the number of bits n.
• Performance degradation for large values of n.
Carry look-ahead adder
• The carry look-ahead adder uses the principle of carry look-ahead
for solving the problem of carry propagation delay by calculating
the carry signals in advance, based on the input signals.

• All the carry bits for the various stages are generated in parallel
before the actual addition starts.

• After the initial delay, all the additions can be done in parallel
Carry look-ahead adder
• In this circuit, the 2 internal signals Pi and Gi are
given by:
• Carry propagate Pi = Ai  Bi
• Carry Generate Gi=Ai.Bi
• The output sum and carry can be defined as :
• Sum Si= Pi  Ci
• Carry Ci+1 = Gi + Pi.Ci
Carry look-ahead adder
• Gi = 1 represents the condition when a carry is
generated in stage-i independent of the other
stages.

• Pi = 1 represents the condition when an input carry


Ci will be propagated to the output carry Ci+1.

Carry propagate Pi = Ai  Bi
Carry Generate Gi=Ai.Bi
Design of 4-bit CLA
i Output = Gi + Pi.Ci
i Sum Output Si= Pi  Ci carry Ci+1
0 S0 S0 =P0  C0 0 C1 = G0+P0.C0

1 S1 S1 = P1  C1 1 C2 = G1+P1.C1
=G1+P1.[ G0+P0.C0 ]
2 S2 S2 =P2  C2
2 C3 = G2+P2.C2
3 S3 S3 =P3  C3 = G2+P2.[ G1+P1.[ G0+P0.C0 ]]
3 C4 =G3+P3.C3
= G3+P3.[ G2+P2.[ G1+P1.[ G0+P0.C0 ]]
Design of 4-bit CLA
4-bit CLA Block Diagram
Why Carry look-ahead adders
required?
• Most other arithmetic operations, e.g. multiplication and division are implemented using
several addition steps. Thus, improving the speed of addition will improve the speed of
all other arithmetic operations.

• Faster addition
Thank
You

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