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UNIT NO 2
THE 8086 MICROPROCESSOR

TIMING DIAGRAM OF 8086

III V

EC8691
MICROPROCESSOR AND MICROCONTROLLER
(Common to CSE & IT)
 EC8691
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MICROPROCESSORS AND MICROCONTROLLERS(Common to CSE & IT)

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SYSTEM TIMING DIAGRAMS

T-state
One clock period is referred to as a T-state
An operation takes an integer number of T-states

CPU Bus Cycle:

When any external memory or I/O device are accessed, only 4 clock cycles
are required to perform a read or write operation. These 4 clock cycles are
grouped and called as bus cycle.

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 EC8691
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MICROPROCESSORS AND MICROCONTROLLERS(Common to CSE & IT)

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MEMORY WRITE TIMING DIAGRAM

•Dump address on address bus.
•Dump data on data bus
•Issue a write(WR) and set M/IO to 1

MEMORY READ TIMING DIAGRAM

●Dump address o address bus
●Issue a read (RD) and set M/IO to 1.
●Wait for memory access cycle

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 EC8691
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MICROPROCESSORS AND MICROCONTROLLERS(Common to CSE & IT)

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BUS TIMING
DURING T1
The address is placed on the address/data bus. Control signals M/IO, ALE and
DT/R specify memory or I/O, latch the address onto the address bus and set the
direction of data transfer on data bus
DURING T2
8086 issues the RD or WR signal, DEN and for a write the data. DEN enables
the memory or I/O device to receive the data for write and 8086 to receive the
data for read
DURING T3
This cycle is provided to allow memory to access data.READY is sampled at
the end of T2. If low, T3 becomes a wait state. Otherwise the data bus is
sampled at the end of T3
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 INFORMATION TECHNOLOGY EC8691
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During T4:
All bus signals are deactivated, in preparation for next bus cycle
Data is sampled for reads, writes occur for writes

STEP TIME: The time before the rising edge of the clock, while the data
must be valid and constant
HOLD TIME: The time after the rising edge of the clock during which the data
must remain valid and constant

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A wait state (Tw) is an extra clocking period, inserted between T2 and T3, to
lengthen the bus cycle, allowing slower memory and I/O components to
respond
The READY input is sampled at the end of T2, and again if necessary in the
middle of Tw. If READY is ‘o’ then a Tw is inserted.

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 INFORMATION TECHNOLOGY EC8691
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MICROPROCESSOR
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HERE MICROCONTROLLER (COMMON TO CSE & IT)

MEMORY/ I/O READ TIMING DIAGRAM- Minimum Mode

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 INFORMATION TECHNOLOGY EC8691
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MICROPROCESSOR
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MEMORY READ TIMING DIAGRAM- Maximum Mode

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 INFORMATION TECHNOLOGY EC8691
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MICROPROCESSOR
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HERE MICROCONTROLLER (COMMON TO CSE & IT)

MEMORY WRITE TIMING DIAGRAM- Minimum Mode

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 INFORMATION TECHNOLOGY EC8691
SUBJECT CODE
MICROPROCESSOR
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HERE MICROCONTROLLER (COMMON TO CSE & IT)

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