UNIT IV

SEQUENTIAL CIRCUITS-I
 INTRODUCTION
• So far we have studied the analysis and design of combinational digital
circuits. It constitutes only a part of digital systems. The other major aspect
of digital system is analysis and design sequential circuits.
• There are many applications in which digital outputs are required to be
generated in accordance with the sequence in which the input signals
received. This requirement cannot be satisfied using a combinational logic
system.
• In sequential circuits the output variables depend not only the present
input variables but the also depend upon the past history of these
input variables.
 Combinational
Inputs
circuit Outputs

Memory elements
Present state Next state
 Difference Between Combinational Logic Circuits and Sequential Logic
Circuits

Combinational circuits Sequential circuits

• In combinational circuits, the output variables • In sequential circuits the output variables
are at all times dependent on the combination of depend not only the present input variables but
input variables. the also depend upon the past history of these
input variables.
• Memory unit is not required. • Memory unit is required to store the past history
of input variables.
• These circuits are fast in speed because the delay • Sequential circuits are slower than the
between input and output is due to propagation combinational circuits.
delay of gates. • Sequential circuits are comparatively harder to
• combinational circuits are easy to design. design.
• Serial adder is a sequential circuit.
• Parallel adder is a combinational circuit.
 Classification of Sequential Circuits

Synchronous sequential circuits Asynchronous sequential circuits

• In synchronous circuits, memory elements • In asynchronous circuits, memory
clocked flip-flops elements are either unclocked flip-flops or
• In synchronous circuit, the change in input time delay elements
signals can affect memory element upon • In asynchronous circuit, the change in
activation of clock signal input signals can affect memory element at
• The maximum operating speed of clock any instant of time
depends on time delay involved. • Because of absence of clock,
• Easier to design asynchronous circuits can operate faster
than synchronous circuits
• More difficult to design
 Latches Vs Flip-Flops

Latches Flip-Flops
• A simple latch is the basis for • Flip-flop is built by connecting
flip-flop building some additional components
• Latch is level triggered either around a latch
positive or negative level • Flip-flop is pulse or clock edge
triggered triggered either positive or
• The latch output responds to negative edge triggered
inputs, until active level is • Flip-flop output responds to
maintained at the enable input inputs only at the specified
(positive or negative) edges of
clock pulse.
 Level Triggering
• In the level triggering the output state is allowed to change according to
input(s) when active level (either positive or negative) is maintained at the
enable input.
• There are two types of level triggered latches
Positive level triggered:
The output of latch responds to the input changes only when its
enable input is 1(High).
LATCH IS
ENABLED ONLY
V WHEN THE
LEVEL OF E
1 INPUT IS HIGH
ENABLE INPUT
0
 Negative level triggered:
The output of latch responds to the input changes only when its
enable input is 0(Low).

1
ENABLE INPUT
0

LATCH IS
ENABLED ONLY
WHEN THE
LEVEL OF E
INPUT IS LOW
 Edge Triggering
In the edge triggering the output responds to the changes in the input only at
the positive or negative edge of the clock pulse at the clock input.
There are two types of edge triggering.
Positive edge triggering:
Here, the output responds to the changes in the input only at the
positive edge of the clock pulse at the clock input.
V

1
CLOCK INPUT
0

Output responds
only at the
positive edges of
the pulse
Negative edge triggering:
Here, the output responds to the changes in the input only at the
negative edge of the clock pulse at the clock input.

1
CLOCK INPUT
0

Output responds
only at the
positive edges of
the pulse
SR Latch using NOR Gate
Present Next
Inputs state
state
S R 𝑸 𝒏 𝑸 𝒏+𝟏
R
𝟎 𝑸 𝒏𝟎 𝟎 𝟎 𝟎
𝟎 𝟎
𝟏 𝟎 𝟎 𝟏 𝟏
𝟎 𝟏 𝟎 𝟎
𝟎
𝑸 𝒏𝟏 𝟎 𝟏 𝟏 𝟎
𝟎 S 𝟏 𝟏 𝟎 𝟏
𝟎
𝟏 𝟎 𝟏 𝟏
𝟏 𝟏 𝟎 𝑿
𝟏 𝟏 𝟏 𝑿
 SR LATCH USING NAND GATE
Present Next
Inputs state
state
S S R 𝑸 𝒏 𝑸 𝒏+𝟏
𝑸𝒏
𝟎 𝟎 𝟎 𝑿
𝟎 𝟎 𝟏 𝑿
𝑸𝒏 𝟎 𝟏 𝟎 𝟏
R 𝟎 𝟏 𝟏 𝟏
𝟏 𝟎 𝟎 𝟎
𝟏 𝟎 𝟏 𝟎
𝟏 𝟏 𝟎 𝟎
𝟏 𝟏 𝟏 𝟏
 S 𝑸𝒏
Present Next
Inputs state
state
En S R 𝑸 𝒏 𝑸 𝒏+𝟏
R 𝑸𝒏
𝟏 𝟎 𝟎 𝟎 𝟎
𝟏 𝟎 𝟎 𝟏 𝟏
𝑮𝑨𝑻𝑬𝑫 𝑺𝑹𝑳𝑨𝑻𝑪𝑯
𝟏 𝟎 𝟏 𝟎 𝟎
S 𝟏 𝟎 𝟏 𝟏 𝟎
𝑸𝒏 𝟏 𝟏 𝟎 𝟎 𝟏
𝟏 𝟏 𝟎 𝟏 𝟏
En
𝟏 𝟏 𝟏 𝟎 𝑿
𝑸𝒏 𝟏 𝟏 𝟏 𝟏 𝑿
R
D latch
𝑫 S
𝑸𝒏

En

𝑸𝒏
R

En 𝑫 𝑸 𝒏 𝑸 𝒏+𝟏

𝑿 𝑸𝒏 𝑸𝒏
 𝑺𝑹𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷 𝑼𝑺𝑰𝑵𝑮 𝑵𝑨𝑵𝑫 𝑮𝑨𝑻𝑬
S
𝑸𝒏

CP

𝑸𝒏 Present Next
R Inputs state
state
CP S R 𝑸 𝒏 𝑸 𝒏+𝟏
𝟏 𝟎 𝟎 𝟎 𝟎
𝟏 𝟎 𝟎 𝟏 𝟏
𝟏 𝟎 𝟏 𝟎 𝟎
𝟏 𝟎 𝟏 𝟏 𝟎
𝟏 𝟏 𝟎 𝟎 𝟏
𝟏 𝟏 𝟎 𝟏 𝟏
𝟏 𝟏 𝟏 𝟎 𝑿
𝟏 𝟏 𝟏 𝟏 𝑿
𝑺𝑹𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷 𝑼𝑺𝑰𝑵𝑮 𝑵𝑶𝑹𝑮𝑨𝑻𝑬
S
𝑸𝒏

CP

𝑸𝒏
R
S 𝑸𝒏
CP
S
R 𝑸𝒏
𝑸𝒏
CP

𝑸𝒏
R
 𝑫 𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷 CP 𝑫 𝑸 𝒏 𝑸 𝒏+𝟏
𝑫 S
𝑸𝒏

CP
𝑿 𝑸𝒏 𝑸𝒏
𝑸𝒏
R 𝑫 S 𝑸𝒏
CP

S R 𝑸𝒏
𝑫
𝑸𝒏

CP

𝑸𝒏

R
 𝑱𝑲 𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷
J 𝑸𝒏

CP

K 𝑸𝒏 Present Next
Inputs state
state
CP J K 𝑸 𝒏 𝑸 𝒏+𝟏
𝟏 𝟎 𝟎 𝟎 𝟎
𝟏 𝟎 𝟎 𝟏 𝟏
𝟏 𝟎 𝟏 𝟎 𝟎
J 𝑸𝒏 𝟏 𝟎 𝟏 𝟏 𝟎
CP 𝟏 𝟏 𝟎 𝟎 𝟏
K 𝑸𝒏 𝟏 𝟏 𝟎 𝟏 𝟏
𝟏 𝟏 𝟏 𝟎 𝟏
𝟏 𝟏 𝟏 𝟏 𝟎
Race-around condition

• In JK flip-flop , when J=K=1, the output toggles. Consider that initially

Q=0 and J=K=1.
• After a time interval equal to the propagation delay through two NAND
gates in series, the output will change to Q=1 and after another time
interval of the output will change back to Q=0. this toggling will continue
until the flip-flop is enabled and J=K=1. at the end of clock pulse the flip-
flop is disabled and the value of Q is uncertain.
• This situation is referred to as the race-around condition. This condition
exists when we can avoid race around condition.
• We can keep b keeping the duration of edge less than . A more practical
method for overcoming this difficult is the use of the Master-Slave (MS)
configuration.
MASTER-SLAVE JK FLIP-FLOP
• When J=1 and K=0, the master sets on the positive clock. The
high Y output of the master drives the J input of the slave, so
at negative clock, slave sets, coping the action of the master.
• When J=0 and K=1, the master resets on the positive clock.
The high output of the master goes to the K input of the slave.
Therefore, at the negative clock slave resets, again coping the
action of the master.
• When J=K=1, master toggles on the positive clock and slave
then copies the output of master on the negative clock.
• When J=K=0, the output of master remains same at the
positive clock. Thus the output of slave also remains same at
the negative clock.
 T FLIP-FLOP
T J
𝑸𝒏

CP

𝑸𝒏
K CP 𝑻 𝑸 𝒏 𝑸 𝒏+𝟏

T
J 𝑸𝒏
CP 𝑿 𝑸𝒏 𝑸𝒏
K 𝑸𝒏
 PRESET AND CLEAR (ASNCHRONOUS) INPUTS

• For the flip-flops discussed so far, the SR, D, JK and T, the

inputs are called synchronous inputs because data on these
inputs are transferred to the flip-flops output only on the
triggering edge of the clock pulse; that is, the data are
transferred synchronously with the clock.
• When power is turn ON, the state of the flip-flop is uncertain.
It ma come to set or reset state. In many applications, it is
necessary to initially set or reset the flip-flop. Such initial state
of the flip-flop can be accomplished b using the direct or
asynchronous inputs of the flip-flop.
• These inputs are: () and () the can be applied at an time
between clock pulses and are not in synchronism with the
clock.
 𝑺𝑹𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷

()
()

S
𝑸𝒏
S 𝑸𝒏
CP
CP
𝑸𝒏 R 𝑸𝒏
R

()
()
𝑫 𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷 ()

𝑫 S
𝑸𝒏

CP

𝑸𝒏
()
R

()
𝑫 S 𝑸𝒏
CP

R 𝑸𝒏

()
• The SR and D flip-flops with preset and clear inputs. These
are active-low inputs.
• When = = 1, the circuit operates in accordance with the truth
table of SR flip-flop.
• If = 1, = 0, the flip-flop is reset.
• If = 0, = 1, the flip flop is set
Flip-Flop Excitation Table
EXCITATION TABLE
𝑺𝑹𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷
TRUTH TABLE

Present Next 𝑸 𝒏 𝑸 𝒏+𝟏 S R

Inputs state
state
S R 𝑸 𝒏 𝑸 𝒏+𝟏 𝟎 𝟎 𝟎 𝑿
𝟎 𝟎 𝟎 𝟎 𝟎 𝟏 𝟏 𝟎
𝟎 𝟎 𝟏 𝟏
𝟏 𝟎 𝟎 𝟏
𝟎 𝟏 𝟎 𝟎
𝟎 𝟏 𝟏 𝟎 𝟏 𝟏 𝑿
𝟏 𝟎 𝟎 𝟏
𝟏 𝟎 𝟏 𝟏
S R
𝟏 𝟏 𝟎 𝑿 𝟎 𝟎
𝟏 𝟏 𝟏 𝑿 𝟎 𝟏
𝑫 𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷
EXCITATION TABLE
TRUTH TABLE

𝑸 𝒏 𝑸 𝒏+𝟏 𝑫
CP 𝑫 𝑸 𝒏 𝑸 𝒏+𝟏
𝟎 𝟎
𝟎 𝟏
𝟏 𝟎
𝑿 𝑸𝒏 𝑸𝒏 𝟏 𝟏
𝑱𝑲 𝑭𝑳𝑰𝑷 𝑭𝑳𝑶𝑷

TRUTH TABLE EXCITATION TABLE

Present Next
Inputs state
state
J K 𝑸 𝒏 𝑸 𝒏+𝟏 𝑸 𝒏 𝑸 𝒏+𝟏 J K

𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝟎 𝑿
𝟎 𝟎 𝟏 𝟏
𝟎 𝟏 𝟏 𝑿
𝟎 𝟏 𝟎 𝟎
𝟎 𝟏 𝟏 𝟎 𝟏 𝟎 𝑿 𝟏
𝟏 𝟎 𝟎 𝟏 𝟏 𝟏 𝑿 𝟎
𝟏 𝟎 𝟏 𝟏
𝟏 𝟏 𝟎 𝟏
𝟏 𝟏 𝟏 𝟎
T FLIP-FLOP
TRUTH TABLE EXCITATION TABLE

𝑸 𝒏 𝑸 𝒏+𝟏 𝑻
CP 𝑻 𝑸 𝒏 𝑸 𝒏+𝟏
𝟎 𝟎
𝟎 𝟏
𝟏 𝟎
𝑿 𝑸𝒏 𝑸𝒏
𝟏 𝟏
CONVERSION FROM ONE FLIP-FLOP TO ANOTHER FLIP-FLOP

• SR Flip-Flop to D Flip-Flop
• SR Flip-Flop to JK Flip-Flop
• SR Flip-Flop to T Flip-Flop
• D Flip-Flop to SR Flip-Flop
• D Flip-Flop to JK Flip-Flop
• D Flip-Flop to T Flip-Flop
• JK Flip-Flop to SR Flip-Flop
• JK Flip-Flop to D Flip-Flop
• JK Flip-Flop to T Flip-Flop
• T Flip-Flop to SR Flip-Flop
• T Flip-Flop to D Flip-Flop
• T Flip-Flop to JK Flip-Flop
 SR Flip-Flop to D Flip-Flop

I/P PS NS FLIP FLOP I/PS 𝑫 S 𝑸𝒏

𝑫 𝑸 𝒏 𝑸 𝒏+𝟏 S R CP
R 𝑸𝒏
𝟎 𝑿

𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹 𝑺 𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹 𝑹

𝑸𝒏
𝑫 𝑸𝒏
𝑫
𝑿
𝑿 𝑫
𝑺=𝑫
𝑹=𝑫
D Flip-Flop to SR Flip-Flop 𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹 𝑫
R𝑸 𝒏
S
I/P PS NS F/F I/PS

S R 𝑸 𝒏 𝑸 𝒏+𝟏 𝑫
𝑿 𝑿
𝟎𝟎 𝟎 𝟎
𝟎𝟎 𝟏 𝟏 S
𝑫=𝑺+𝑹𝑸 𝒏𝑹 𝑸 𝒏
𝟎𝟏 𝟎 𝟎
𝟎𝟏 𝟏 𝟎
S
𝑫 𝑸𝒏
𝟏 𝟎 𝟎 𝟏 CP
𝟏𝟎 𝟏 𝟏 𝑸𝒏
𝟏𝟏 𝟎 𝑿 𝑿
𝟏 𝟏 𝟏 𝑿 𝑿
R
APPLICATIONS OF FLIP-FLOPS

• It can be used as a memory element.

• It can be used to eliminate key debounce.
• It is used as basic building block in sequential circuits such as
counters and registers.
• It can be used as a delay element.
REGISTERS

• We have seen that a flip-flop is nothing but a binary cell

capable of storing one bit information, and can be connected
together to perform counting operations. Such a group of flip-
flops is called counter.
• We have also seen that group of flip-flops can be used to store
a word, which is called register.
• A flip-flop can store 1-bit information, so an n-bit register has
a group of n flip-flops and is capable of storing any binary
information/number containing n-bits.
Buffer Register
• Buffer registers are a type of registers used to store a binary
word. These can be constructed using a series of flip-flops as
each flip-flop can store a single bit. This means that in order to
store an n-bit binary word one should design an array of n flip-
flops.
• As shown in below figure a 4 bit synchronous buffer register
formed by cascading four positive edge triggered D flip-flops.
Here the entire input data word B1B2B3B4 is loaded onto the
register at a single clock tick. This means that at every leading
edge of the clock the values of flip-flop outputs follow their
input bits i.e. Q1 = B1, Q2 = B2, Q3 = B3 and Q4 = B4 as
shown by Figure input and output waveforms.
 4 bit buffer register
𝑩𝟏 𝑩𝟐 𝑩𝟑 𝑩𝟒

𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐 𝑫𝟑 𝑸𝟑 𝑫𝟒 𝑸𝟒
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒

CLK
CONTROLLED BUFFER REGISTER
• In this design, tri-state switches are used to control the
operation of loading and/or retrieval of the data to/from the
buffer register. Here one has to pull the or control line (blue
line) low in order to store the data into the register, while
control line (red line) should be made low to read the data.
SHIFT REGISTERS

• The binary information (data) in a register can be moved from

stage to stage within the register or into or out of the register
upon application of clock pulses.
• This type of bit movement or shifting is essential for certain
arithmetic and logic operations used in microprocessors. This
gives rise to a group of registers called shift registers. They are
very important in applications involving the storage and
transfer of data in a digital system.
Data bits

Serial shift right

Data bits

Data bits Serial shift left

Parallel shift in Data bits

Parallel shift out

Rotate right
Rotate left
 Serial in Serial out Shift Register
𝟎
𝟎
𝑫 𝒊𝒏 1 1 1 1 𝟎1 𝟎
1 1 𝟎1 𝟎1 1 𝑫 𝒐𝒖𝒕
𝟎 𝟎 𝟎 𝟎
𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐 𝑫𝟑 𝑸𝟑 𝑫𝟒 𝑸𝟒
11 11
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒

CLK
 CP 𝑫 𝒊𝒏 𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒

INITIALLY 1 0 0 0 0

1 1 0 0 0
1 ST

2 nd 1 1 1 0 0

3 rd 1 1 1 1 0

4 th 1 1 1 1 1
 Serial in Parallel out Shift Register
𝟎
𝟎
𝑫 𝒊𝒏 1 1 1 1 𝟎1 𝟎
1 1 𝟎1 𝟎1 1 𝑫 𝒐𝒖𝒕
𝟎 𝟎 𝟎 𝟎
𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐 𝑫𝟑 𝑸𝟑 𝑫𝟒 𝑸𝟒
11 11
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒

CLK

𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒
1
1 1 1
 Parallel in Parallel out Shift Register
𝑫𝟏 1 𝑫 𝟐0 𝑫 𝟑1 𝑫 𝟒0

𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐 𝑫𝟑 𝑸𝟑 𝑫𝟒 𝑸𝟒
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒

CLK

𝑸𝟏 𝑸𝟐 𝑸𝟑 𝑸𝟒
1 0
1 0
Parallel in Serial out Shift Register
𝑫𝟏 𝑫𝟐 𝑫𝟑 𝑫𝟒
 Bidirectional Shift Register
RIGHT/

SERIAL DATA
IN FOR LEFT
SERIAL DATA SHIFT
IN FOR
RIGHT SHIFT
Universal Shift Register
MODE CONTROL
REGISTER OPERATION
𝑺𝟏 𝑺𝟎

𝟎 𝟎 NO CHANGE

𝟎 𝟏 SHIFT RIGHT

𝟏 𝟎 SHIFT LEFT

𝟏 𝟏 PARALLEL LOAD
Counters
• A group of flip-flops connected together forms a register.
• A register storing and shifting data which is in the form of 1s
and / or 0s, entered from an external source. It has no specific
sequence of states except in certain very specialized
applications.
• A counter is a register capable of counting the number of clock
pulses arriving at its clock input. Count represents the number
of clock pulses arrived. On arrival of each clock pulse, the
counter is incremented by one. In case down counter, it is
decremented by one.
• The n-bit binary counter has n flip-flops and it has distinct
states of outputs.
• For example 2–bit counter has 2 flip flops and it has distinct
states: 00, 01, 10 and 11
• If 3-bit counter has 3 flip-flops and it has distinct states: 000,
001, 010, 011, 100, 101, 110 and 111.
• The maximum count that the binary counter can count - 1.
• For example, in 2–bit binary counter, the maximum count is -
1 = 4-1 =3 (11 in binary). After reaching the maximum count
the counter resets to 0 on arrival of the next clock pulse and it
starts counting again.
• Synchronous Counter:
When counter is clocked such that each flip-flop in the
counter is triggered at the same time, the counter is called
synchronous counter.

• Asynchronous Counter / Ripple Counter :

A binary asynchronous / ripple counter consists of a series
connection of complementing flip-flops, with the output each
flip-flop connected to the clock input of the next higher order
flip-flop.
 𝑫 𝒊𝒏

𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐
D FLIP-FLOP D FLIP-FLOP
𝑸𝟏 𝑸𝟐

CLK
𝑫 𝒊𝒏

𝑫𝟏 𝑸𝟏 𝑫𝟐 𝑸𝟐
D FLIP-FLOP D FLIP-FLOP
CLK 𝑸𝟏 𝑸𝟐
Comparison between synchronous and asynchronous counters

asynchronous counters synchronous counters

• In this type of counter flip-flops are • In this type there is no connection
connected in such a way that output between output of first flip-flop and
of first flip-flop drives the clock for clock input of the next flip-flop.
the next flip-flop. • All the flip-flops are clocked
• All the flip-flops are not clocked simultaneously.
simultaneously.
• Design involves complex logic circuit
• Logic circuit is very simple even for as number of states increases
more number of states.
• As clock is simultaneously given to
• Main drawback of these counters is all flip-flops there is no problem of
their low speed as the clock is propagation delay. Hence they are
propagated through number of flip- high speed counters and are preferred
flops before it reaches last flip-flop. when number of flip-flops increases
in the given design.
 Asynchronous / Ripple Counters
2-BIT ASYNCHRONOUS BINARY UP COUNTER
1

𝑱 𝑨 𝑸𝑨 𝑱𝑩 𝑸𝑩
CP f/f a f/f b
𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩

CP

0 0 1 0
1
𝑸𝑨

0 0 1 1 0
𝑸𝑩
 3-BIT ASYNCHRONOUS BINARY UP COUNTER

𝑱 𝑨 𝑸𝑨 𝑱𝑩 𝑸𝑩 𝑱𝑪 𝑸𝑪
CP f/f a f/f b f/f C
𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩 𝑲 𝑪 𝑸𝑪

CP

0 1 0 1 0 1 0 1 0
𝑸𝑨
0 0 1 1 0 0 1 1 0
𝑸𝑩
0 0 0 0 1 1 1 1 0
𝑸𝑪
 2-BIT ASYNCHRONOUS BINARY DOWN COUNTER
1

𝑱 𝑨 𝑸𝑨 𝑱𝑩 𝑸𝑩
CP f/f a f/f b
𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩

CP
0 1 0 1 0
𝑸𝑨
𝑸𝑨 1 0 1 0 1

𝑸𝑩 0 1 1 0 0

𝑸𝑩 1 0 0 1 1
 ASYNCHRONOUS UP/ DOWN COUNTER
𝑸𝑸
𝑴
INPUTS O/P
1 1
𝑴 𝑸 𝑸 𝒀
1 1
0 0 0 0
Y=𝑸
0 0 1 1 FOR DOWN 𝑴 𝑸 𝑴𝑸
0 1 0 0 COUNTING
𝒀 =𝑴 𝑸 +𝑴𝑸
0 1 1 1
0 0
𝑴 𝑴𝑸
1 0
1 1 Y= Q
0 0 𝑸
1 1 0 1 FOR UP 𝒀 =𝑴 𝑸 +𝑴𝑸
1 1 1 1 COUNTING

𝑴𝑸
𝑸
𝑴

1
𝑱 𝑩𝑸 𝑩 𝑱 𝑪𝑸𝑪
𝑱 𝑨𝑸 𝑨
f/f C
CP f/f b
f/f a
𝑲 𝑩𝑸 𝑩 𝑲 𝑪𝑸 𝑪
𝑲 𝑨𝑸𝑨
𝒖𝒑 /𝒅𝒐𝒘𝒏 =1

CP

0 1 0 1 0 1 0 1 0
𝑸𝑨
0 0 1 1 0 0 1 1 0
𝑸𝑩
0 0 0 0 1 1 1 1 0
𝑸𝑪
𝒖𝒑 /𝒅𝒐𝒘𝒏 =0

CP

0 1 0 1 0 1 0 1 0
𝑸𝑨
𝑸𝑨 1 0 1 0 1 1 0 1 0

𝑸𝑩 0 1 1 0 0 1 1 0 0

𝑸𝑩 1 0 0 1 1 0 0 1 1
0 1 1 0 0 0 0
𝑸𝑪 1 1

𝑸𝑪 1 0 0 0 0 1 1 1 1
DESIGN OF RIPPLE/ASYNCHRONOUS COUNTERS

• Determine the number of flip-flops needed.

• Choose the type of flip-flops to be used: T or JK. If T flip-
flops are used connect T input of all flip-flops to logic 1. if JK
flip-flops are used connect both J and K inputs of all flip-flops
to logic 1.
• Write the truth table for the counter.
• Derive the reset logic by k-map simplification.
• Draw the logic diagram.
1.Design mod 6 ripple counter using T flip-flops
• Determine the number of flip-flop required. Here, counter
goes through 0 to 5 states, i.e., total states. Thus N=6 and for
we need n=3 , i.e., 3 flip-flops.
OUTPUT OF
CLK A B C
RESET LOGIC Y
0 0 0 0 1
1 0 0 1 1
2 0 1 0 1 1 1 1 1

3 0 1 1 1 1 1
4 1 0 0 1
5 1 0 1 1 𝑩 𝑨
1 1 0
- 0 𝒀 = 𝑨+𝑩
- 1 1 1 0
 1

𝑻 𝑨 𝑸𝑨 𝑻 𝑩 𝑸𝑩 𝑻𝑪 𝑸𝑪
f/f a f/f b f/f C
CP
𝑸𝑨 𝑸 𝑸𝑪
CLR CLR 𝑩 CLR

2.Design BCD ripple counter using T flip-flops

Synchronous Counters
2-BIT SYNCHRONOUS BINARY UP COUNTER
1

𝑱 𝑨 𝑸𝑨 𝑱𝑩 𝑸𝑩
CP f/f a f/f b
𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩

CP

𝑸𝑨 0 0 1 0
1

0 0 1 1 0
𝑸𝑩
2-BIT SYNCHRONOUS BINARY DOWN COUNTER
1

𝑱 𝑨 𝑸𝑨 𝑱𝑩 𝑸𝑩
CP f/f a f/f b
𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩

CP
0 0 1 0
𝑸𝑨 1

𝑸𝑨

𝑸𝑩 0 1 1 0 0

𝑸𝑩
DESIGN OF SYNCHRONOUS COUNTERS

• Determine the number of flip-flops needed. If n represents

number of flip-flops number of states in the counter.
• Choose the type of flip-flops to be used.
• Using excitation table for selected flip-flop determine the
excitation table for the counter.
• Use K-map or another simplification method to derive the flip-
flop input functions.
• Draw the logic diagram.
 Design a MOD-5 synchronous counter using JK flip-flops and
implement it.
• Flip-flops required are N
N=5 ., n=3 i.e., 3 flip-flops are required
PRESENT STATE NEXT STATE FLIP-FLOP INPUTS
𝑸 𝑪 𝑸 𝑩𝑸 𝑨 𝑸 𝑪 +𝟏𝑸 𝑩+𝟏𝑸 𝑨+𝟏 𝑱 𝑪 𝑲𝑪 𝑱𝑩 𝑲𝑩 𝑱𝑨 𝑲𝑨
0 0 0 0 0 1 𝟎 𝑿 𝟎 𝑿 𝟏 𝑿
0 0 1 0 1 0 𝟎 𝑿 𝟏 𝑿 𝑿 𝟏
0 1 0 0 1 1 𝟎 𝑿 𝑿 𝟎 𝟏 𝑿
0 1 1 1 0 0 𝟏 𝑿 𝑿 𝟏 𝑿 𝟏
1 0 0 0 0 0 𝑿 𝟏 𝟎 𝑿 𝟎 𝑿
1 0 1 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿
1 1 0 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿
1 1 1 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿 𝑿
𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑱 𝑪 𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑲 𝑪
𝑸𝑸
𝑩 𝑨 𝑸𝑸
𝑩 𝑨
𝑸𝑪 𝑸𝑪
𝟏 𝑿 𝑿 𝑿 𝑿
𝑿 𝑿 𝑿 𝑿 𝟏 𝑿 𝑿 𝑿

𝑱 𝑪 =𝑸 𝑩 𝑸 𝑨 𝑸𝑸
𝑩 𝑨 𝟏 𝑲 𝑪 =𝟏
𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑱 𝑩
𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑲 𝑩
𝑸𝑸
𝑩
𝑸𝑪 𝑨 𝑸𝑸
𝑩 𝑨

𝑿 𝟏 𝑿 𝑸𝑪
𝑿 𝑿 𝟏
𝑿 𝑿 𝑿
𝑿 𝑿 𝑿 𝑿
𝑱 𝑩 =𝑸 𝑨 𝑸 𝑨 𝑸𝑨
𝑲 𝑩 =𝑸 𝑨
 𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑱 𝑨 𝑲 − 𝑴𝑨𝑷 𝑭𝑶𝑹= 𝑲 𝑨
𝑸𝑸
𝑩 𝑨
𝑸𝑸
𝑩 𝑨 𝑸𝑪
𝑸𝑪
𝑿 𝟏 𝟏 𝑿
𝟏 𝑿 𝑿 𝟏
𝑿 𝑿 𝑿 𝑿
𝑿 𝑿 𝑿

𝑸𝑪 𝟏 𝑲 𝑨 =𝟏
𝑱 𝑨 =𝑸 𝑪

𝑱 𝑨 𝑸𝑨 𝑱 𝑩 𝑸𝑩 𝑱𝑪 𝑸𝑪

f/f a f/f B f/f C

𝟏 𝑲 𝑨 𝑸𝑨 𝑲𝑩 𝑸𝑩 𝟏 𝑲 𝑪 𝑸𝑪

CP
𝑸𝑪
𝑸𝑨 𝑸𝑩
 Ring Counter

𝑷𝑹𝑬
𝑫𝑨 𝑸𝑨 𝑫 𝑩 𝑸𝑩 𝑫𝑪 𝑸𝑪 𝑫 𝑫 𝑸𝑫
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝑨 𝑸𝑩 𝑸𝑪 𝑸𝑫

CLK

𝑪𝑳𝑹
 CLOCK PULSE 𝑸 𝑨𝑸 𝑩 𝑸 𝑪 𝑸 𝑫
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0

CP

𝑸𝑨

𝑸𝑩

𝑸𝑪

𝑸𝑫
 Johnson or Twisted Ring Counter

𝑫𝑨 𝑸𝑨 𝑫 𝑩 𝑸𝑩 𝑫𝑪 𝑸𝑪 𝑫 𝑫 𝑸𝑫
D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
𝑸𝑨 𝑸𝑩 𝑸𝑪 𝑸𝑫

CLK
 CLOCK PULSE 𝑸 𝑨𝑸 𝑩 𝑸 𝑪 𝑸 𝑫
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

CP

𝑸𝑨

𝑸𝑩

𝑸𝑪
𝑸𝑫