Sequential Circuits

O U TLI N E O F CH APTER 5

Sequential Latches Flip-flop Analysis of State Reduction

Circuits Clocked and Assignment
Sequential Circuits

Design Procedure
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SEQ U EN TI AL CI RCU I TS
• Every digital system is likely to have combinational circuits.
• Most systems encountered in practice also include storage
elements, which require that the system be described in terms
of sequential logic.

Inputs Outputs
Combinational
Circuit
Memory
Elements
 5

SEQ U EN TI AL CI RCU I TS
• The storage elements are devices capable of storing binary
information.
• The binary information stored in these elements at any given
time defines the state of the sequential circuit at that time.

• The sequential circuit receives binary information from external

inputs.
• These inputs, together with the present state of the storage
elements, determine the binary value of the outputs.
 6

SEQ U EN TI AL CI RCU I TS
• They also determine the condition for changing the state in the
storage elements.
• A sequential circuit is specified by a time sequence of inputs,
output, and internal states.
 7

SEQ U EN TI AL CI RCU I TS
• There are two main types of sequential circuits.

• Their classification depends on the timing of their signals.

Synchronous Asynchronous

Sequential
Circuit
 8

SEQ U EN TI AL CI RCU I TS
• Asynchronous Sequential Circuit

Inputs Outputs
Combinational
Circuit
Memory
Elements

– The behaviour of the circuit depends upon the input signals at any
instant of time and the order in which the inputs change.
 9

SEQ U EN TI AL CI RCU I TS
• Asynchronous Sequential Circuit
– In gate – type asynchronous systems, the storage elements consist
of logic gates whose propagation delay provides the required
storage.

– Thus, an asynchronous sequential circuit may be regarded as a

combinational circuit with feedback.

– Because of the feedback among logic gates, an asynchronous

sequential circuit may become unstable at times.
 10

SEQ U EN TI AL CI RCU I TS
• Synchronous Sequential Circuit

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

– The behaviour can be defined from the knowledge of its signals at

discrete instants of time.
 11

SEQ U EN TI AL CI RCU I TS
• Synchronous Sequential Circuit
– Employs signals that affect the storage elements only at discrete
instants of time.

– Synchronisation is achieved by a timing device called a clock

generator.

• Provides a periodic train of clock pulses.

• Clock pulses are distributed throughout the system in such a way that
storage elements are affected only with the arrival of each pulse.
 12

SEQ U EN TI AL CI RCU I TS

• Synchronous Sequential Circuit

• In practice, the clock pulses are applied with other signals that specify the
required change in the storage elements.

– Circuits that use clock pulses in the inputs of storage elements are
called clocked sequential circuits.
– The storage elements used in clocked sequential circuits are called
flip – flops.
– A flip – flop is a binary storage device capable of storing one bit of
information.
 14

LATCH ES
• Latches are the basic circuits from which all flip – flops are
constructed.
• Although latches are useful for storing binary information and
for the design of asynchronous sequential circuits.

• They are not practical for use in synchronous sequential circuits.

 14

LATCH ES Ba sics

NAND gate
NOR gate
 15

LATCH ES
• SR Latch

Reset (R) 1 0
Q

NOR gate

Set (S) 0 Q
1
 15

LATCH ES
• SR Latch

Reset (R) 0 1
Q

NOR gate

Set (S) 1 Q
0
 15

LATCH ES
• SR Latch

Reset (R) 1 0
Q

NOR gate

Set (S) 1 Q
0
Invalid State
 15

LATCH ES
• SR Latch

Reset (R) 0 Q

NOR gate

Set (S) 0 Q
Previous state
 16

LATCH ES
• SR Latch
SR Q
R Q 0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S Q
Q SR
0 0 Q=Q’=1 Invalid
0 1 1 Set
R Q 1 0 0 Reset
1 1 Q0 No change
 17

LATCH ES
• SR Latch with Control Input
R R S S
Q Q

C C
R Q
S Q R
S
C S R Q
0 X X HOLD No change

1 0 0 HOLD No change

1 0 1 Q=0 Reset

1 1 0 Q=1 Set
Invalid
1 1 1 Q = Q’
 18

LATCH ES
• D Latch (D = Data)
– One way to eliminate the undesirable condition of the indeterminate
state in the SR- latch is to ensure that inputs S and R are never equal
to 1 at the same time.

– D latch has two inputs

• D (data) - directly goes to the S input and its complement is applied to
the R input.

• C (control)
 20

LATCH ES
• D Latch (D = Data)
D S
Q
C
R Q

C D Q
0 X HOLD No change

1 0 Q=0 Reset

1 1 Q=1 Set
 21

LATCH ES
• D Latch (D = Data)
– The D latch has an ability to hold data in its internal storage.

– It is suited for use as a temporary storage for binary information.

– This circuit is often called transparent latch.

• The output follow changes in the data input as long as the control input
is enabled.
 23

FLI P – FLO PS
• Flip – flops are constructed in such a way to make D latches operate
properly when they are part of a sequential circuit that employs a
common clock.

• The problem with the latch is that

– It responds to a change in the level of a clock pulse.
• Positive level response in the control input allows changes, in the output
when the D input changes while the control pulse stays at logic 1.

• The key to the proper operation of a flip – flop is

– to trigger it only during a signal transition.
 24

FLI P – FLO PS
• Controlled latches are level – triggered

• Flip-Flops are edge – triggered

CLK Positive Edge

CLK Negative Edge

 25

FLI P – FLO PS
• There are two ways that a latch can be modified to form a flip –
flop.
1. Employ two latches in a special configuration that
• isolates the output of the flip – flop from being affected while its input is
changing.

2. Produce a flip – flop that triggers only during a signal transition.

• From 0 to 1 or from 1 to 0 only.

• Disabled during the rest of the clock pulse duration.

 26

FLI P – FLO PS
• Master – Slave D flip – flops
D D Q D Q Q
D Latch D Latch
(M aster) (Slave)
C C
M aster Slave
CLK
CL

Looks like it is negative

KD
edge-triggered
QM aster
QSlave
 27

FLI P – FLO PS
• Edge-Triggered D Flip – Flop • Two latches respond to the
external D (data) and CLK (clock
inputs).
S
Q • Third latch provides the outputs
CLK for the flip – flop.
R
Q

D
 28

FLI P – FLO PS
• Edge-Triggered D Flip – Flop I. When CLK = 0, S = 1 and R =
1.Output = present state.

S II. If D = 0, when CLK à 1

Q 1. R changes to 0
CLK 2. Flip – flop goes to the RESET
R
Q state.

3. Q = 0.

D
 29

FLI P – FLO PS
• Edge-Triggered D Flip – Flop III. If D changes when CLK = 1 then
1. R remains at 0.
2. Flip – flop is locked out
S
3. Unresponsive to further changes
Q in the input.
CLK
R IV. When CLK à 0,
Q
1. R à 1
2. Placing the output latch in the
quiescent condition.
D
3. No change in the output.
 30

FLI P – FLO PS
• Edge-Triggered D Flip – Flop V. If D = 1 when CLK = 0 à 1,
1. S changes to 0.

S 2. Circuit goes to SET state

Q 3. Q = 1.
CLK 4. Any change in D while CLK = 1
R
Q does not affect the output.

D
 31

FLI P – FLO PS
• Edge-Triggered D Flip – Flop • When CLK in the positive-edge-
triggered flip – flop
– Makes positive transition
S
• The value of D is transferred
Q
to Q.
CLK
R – Makes negative transition
Q
• Does not affect the output.
– Steady CLK 1 or 0
D • Does not affect the output.
 32

FLI P – FLO PS
• Edge-Triggered D Flip – Flop
– The timing of the response of a flip – flop to input data and clock
must be taken into consideration when using edge – triggered flip -
flops.
• There is a minimum time, called setup time, for which the D input must
be maintained at a constant value prior to the occurrence of the clock
transition.

• There is a minimum time, called hold time, for which the D input must
not change after the application of the positive transition of the clock.
 33

FLI P – FLO PS
• Edge-Triggered D Flip – Flop
D Q

Q
Q Positive Edge
CLK Dynamic
Q input
D Q

Q
D
Negative Edge
 34

FLI P – FLO PS
• The most economical and efficient flip – flop constructed is the
edge – triggered D flip – flop.
– It requires smallest number of gates.
• Other types of flip – flops can be constructed by using the D flip –
flop and external logic.

– JKflip – flops

– T flip - flops
 35

FLI P – FLO PS
• There are three operations that can be performed with a flip –
flop:
– Set it to 1

– Reset it to 0

– Complement its output

 36

FLI P – FLO PS
• JK Flip – Flop • When J= 1, sets the flip – flop
– Performs all three operations. to 1.
• When K = 1, resets the flip –
J
D Q Q flop to 0.
K

CLK Q Q

D = JQ’ + K’Q
 37

FLI P – FLO PS
• JK Flip – Flop Operation 1

• When J= 1 and K = 0,
– D = 1.Q’ + 1.Q (Post2b)
J
D Q Q – D = Q’ + Q (Post5a)
K

CLK Q Q
– D=1
– Next clock edge sets the output
to 1.
D = JQ’ + K’Q
 38

FLI P – FLO PS
• JK Flip – Flop Operation 2

• When J= 0 and K = 1,
– D = 0.Q’ + 0.Q (Theo2b)
J
D Q Q – D=0+0
K

CLK Q Q
– D=0
– Next clock edge sets the output
to 0.
D = JQ’ + K’Q
 39

FLI P – FLO PS
• JK Flip – Flop Operation 3

• When J= 1 and K = 1,
– D = 1.Q’ + 0.Q (Post2b)
J
– D = Q’ + 0 .Q (Theo2b)
D Q Q
K
– D = Q’ + 0 (Post2a)
CLK Q Q

– D = Q’

D = JQ’ + K’Q – Next clock edge complements

the output.
 40

FLI P – FLO PS
• JK Flip – Flop • When J= 0 and K = 0,
– D = 0.Q’ + 1.Q (Theo2b)
– D = 0 + 1 .Q (Post2b)

J – D=0+Q (Post2a)
D Q Q
K
– D=Q
CLK Q Q
– Next clock edge the output is
unchanged.
D = JQ’ + K’Q
 41

FLI P – FLO PS
• JK Flip – Flop

J J Q
D Q Q
K

CLK Q Q
K Q

D = JQ’ + K’Q
 42

FLI P – FLO PS
• T (toggle) Flip – Flop
– Complementing flip – flop.
– Can be obtained from a JK T J Q
flip – flop. C
– When inputs Jand K are tied K Q
together.
– Useful for designing binary D = JQ’ + K’Q
counters. D = TQ’ + T’Q = T Å Q
 43

FLI P – FLO PS
• T (toggle) Flip – Flop
– When T = 0 (J= K = 0)
– A clock edge does not T J Q
change the output. C
– When T = 1 (J= K = 1) K Q
– A clock edge complements
the output. D = JQ’ + K’Q
D = TQ’ + T’Q = T Å Q
 44

FLI P – FLO PS
• T (toggle) Flip – Flop
– Can be constructed with a D
flip – flop and an XOR gate.
D Q
– When T = 0 then D = Q T
• No change in the output.
C Q
– When T = 1 then D = Q’
• Output complements D = TQ’ + T’Q = T Å Q
 45

FLI P – FLO PS
• T (toggle) Flip – Flop

T J Q
D Q T Q
T
C
K Q C Q C Q

(a) From JKFlip – Flop (b) From D Flip – Flop (c) Graphic Symbol
 46

FLI P – FLO PS
• Flip – Flop Characteristics Table

D Q D Q (t+1)
0 0 Reset

1 1 Set
Q

Q(t+1) = D
 47

FLI P – FLO PS
• Flip – Flop Characteristics Table
J K Q (t+1)
J Q 0 0 Q(t) No change

0 1 0 Reset

1 0 1 Set
K Q
1 1 Q’(t) Toggle

Q(t+1) = JQ’ + K’Q

 48

FLI P – FLO PS
• Flip – Flop Characteristics Table

T Q T Q (t+1)
0 Q(t) No change

1 Q’(t) Toggle
Q

Q(t+1) = T Q
 49

FLI P – FLO PS
• Some flip – flops have asynchronous inputs that are used to
force the flip – flop to a particular state independent of the
clock.

• The input that sets the flip – flop to 1 is called preset.

• The input that clears the flip – flop to 0 is called clear or direct
reset.
• When power is on in a digital system, the state of the flip flop is
unknown.
 50

FLI P – FLO PS
• When power is on in a digital system, the state of the flip flop is
unknown.
• The direct inputs are useful for bringing all flip – flops in the
system to a known starting state prior to the clocked operation.
 51

FLI P – FLO PS
• Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q

R
Reset
 52

FLI P – FLO PS
• Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
1 1 ↑ 1
R
Reset
 53

FLI P – FLO PS
• Asynchronous Preset and Clear
Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 x x 0

Q
CLR
Reset
23 Decem ber , 2016
 54

FLI P – FLO PS
• Asynchronous Preset and Clear
Preset
PR’ CLR’ D CLK Q(t+1)
PR
D Q 1 0 x x 0
0 1 x x 1
Q
CLR
Reset
 55

FLI P – FLO PS
• Asynchronous Preset and Clear
Preset
PR’ CLR’ D CLK Q(t+1)
PR
D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1

Reset
2
 57

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

• The behaviour of a clocked sequential circuit is determined from:

– The inputs

– The outputs

– The state of its flip – flops

• The outputs and the next state are both a function of

– The inputs

– The present state

 58

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

• The analysis of sequential circuit consists of:

– Obtaining a table or a diagram for the time sequence of
• Inputs

• Outputs

• Internal states
– It is also possible to write Boolean expression that describe the
behaviour of the sequential circuit.
 59

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Equations
• The behaviour of a clocked sequential circuit can be described
algebraically by means of state equations (transition equations).

• A state equation specifies the next state as a function of

– The present state
– Inputs
 60

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Consider: • Circuit consists of:

– Two D flip – flops A and B.
x
D Q A – An input x.

Q – An output y.
– It is possible to write a set of
D Q B equations for the circuit.

CLK Q

y
 61

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Consider: • A(t+1) = A(t) . x(t) + B(t) . x(t)

• B(t+1) = A’(t) . x(t)

x
D Q A
– (t+1) à next state of the flip flop
Q A’ – Right side of the equation is a
Boolean expression
D Q B
• Specifies the present state
CLK Q B’ • Input conditions that make the
next state = 1.
y
 62

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Consider: • A(t+1) = A(t) . x(t) + B(t) . x(t)

x
• B(t+1) = A’(t) . x(t)
D Q A
– Since all the variables in the
Q A’ Boolean expression are a
function of the present state
D Q B
– We can omit the designation (t)
CLK Q B’
• A(t+1) = A . x + B . x
y
• B(t+1) = A’ . x
 63

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Consider: • Similarly,

• y(t) = [A(t) + B(t)] x’(t)

x
D Q A
• y = (A + B) x’
Q A’

D Q B

CLK Q B’

y
 64

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Consider: • A(t+1) = A . x + B . x

• B(t+1) = A’ . x
x
D Q A
• y = (A + B) x’
Q A’

D Q B

CLK Q B’

y
 65

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Table
• The time sequence of inputs, outputs and flip – flop can be enumerated
in state table (transition table).

• In general, a sequential circuit with m flip – flops and n inputs needs

2m+n rows in the state table.
 66

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Table • A(t+1) = A . x + B . x

Present Input Next State
Output
State (t) (t) (t+1) • B(t+1) = A’ . x
A B x A B y
0 0 0 0 0 0
• y = (A + B) x’
0 0 1 0 1 0
x
0 1 0 0 0 1 D Q A

0 1 1 0 1 0 Q A’

1 0 0 0 0 1
D Q B
1 0 1 1 0 0
CLK Q B’
1 1 0 0 0 1
y
1 1 1 1 0 0
 67

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Table 2 • A(t+1) = A . x + B . x

Present Next State
Output
State (t+1) • B(t+1) = A’ . x
(t) x=0 x=1 x=0 x=1
AB AB AB y y
• y = (A + B) x’
00 00 01 0 0
x
D Q A
01 00 11 1 0
Q A’
10 00 10 1 0

11 00 10 1 0 D Q B

CLK Q B’

y
 68

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Diagram
• The information available in a state table can be represented graphically
in the form of a state diagram.

• State is represented by a circle

• Transition between states are indicated by directed lines connecting the

circles.
 69

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

State Diagram 0/ 0 1/ 0
Present Next State
Output
State (t+1) 0/ 1
(t) x=0 x=1 x=0 x=1
AB AB AB y y 00 10
00 00 01 0 0
0/ 1
01 00 11 1 0
1/ 0 0/ 1 1/ 0
10 00 10 1 0

11 00 10 1 0

01 11
AB input/output
1/ 0
 77

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Mealy and Moore Models

• The most general model of a sequential circuit has:
– Inputs
– Outputs
– Internal states.

• Sequential circuits are divided into two (they differ in the way output is
generated:
– Mealy model
– Moore model
 78

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Mealy and Moore Models

• Mealy model:
– The output is a function of both the present state and input.
– The outputs may change if the inputs change during the clock pulse period.
• The outputs may have momentary false values unless the inputs are
synchronized with the clocks.

– Example of Sequential Circuit

 79

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Mealy and Moore Models

• Moore model:

– The output is function of the present state only.

– The outputs are synchronous with the clocks.

– Example of Sequential Circuit
 80

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

Mealy and Moore Models

Mealy Machine

Inputs Next State State Output

Outputs
Combinational Register Combinational
(Mealy – type)
Logic Logic
clock

Moore Machine

Inputs Next State State Output

Outputs
Combinational Register Combinational
(Moore – type)
Logic Logic
clock
 81

AN ALYSI S O F CLO CKED SEQ U EN TI AL CI RCU I TS

M ealy M oore
Present Next Present Next
I/P O/P I/P O/P
State State State State
A B x A B y A B x A B y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 1 0 0 0 1 0 1 0 0 1 0
0 1 1 1 1 0 0 1 1 1 0 0
1 0 0 0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 1
1 1 1 1 0 0 1 1 1 0 0 1

For the same state, For the same state,

the output changes with the input the output does not change with the input
 83

STATE REDUCTION AND ASSIGNMENT

• The analysis of sequential circuits
– starts from a circuit diagram and

– culminates in a state table or diagram.

• The design of a sequential circuits

– starts from a set of specifications and

– culminates in a logic diagram.

 84

STATE REDUCTION AND ASSIGNMENT

• State – reduction algorithms are concerned with procedures for
reducing the number of states in a state table, while keeping the
external input – output requirements unchanged.

• Since m flip – flops produce 2 m states,

– a reduction in the number of states may (or may not) result in a reduction in
the number of flip – flops.

• An unpredictable effect in reducing the number of flip – flops is that

sometimes the equivalent circuit (with fewer flip – flops) may require
more combinational gates.
 85

STATE REDUCTION AND ASSIGNMENT

• Consider a sequential circuit 0/ 0

whose specification is given in a

0/ 0 0/ 0
the state diagram. 1/ 0

0/ 0 0/ 0
• There are infinite number of b c
1/0
input sequence that may be 1/ 0

applied to the circuit; 0/ 0

g d e
– Each results in a unique output 1/ 1 1/ 1
0/ 0 1/ 1
sequence. f
1/ 1
 86

STATE REDUCTION AND ASSIGNMENT

• Consider input sequence 0/ 0

– 01010110100 a
0/ 0 0/ 0
– Starting from the initial state a. 1/ 0

0/ 0 0/ 0
– Each input of 0/1 produces an b c

output of 0/1 and causes circuit 1/ 0 1/0

to go to the next state. 0/ 0

g d e
1/ 1 1/ 1
0/ 0 1/ 1
f
1/ 1
 87

STATE REDUCTION AND ASSIGNMENT

• Consider input sequence 0/0

– 01010110100 a
0/0 0/0
1/0
0/0
state

a a b c d e f f g f g a 0/0 b c
1/0
1/ 0
input

0 1 0 1 0 1 1 0 1 0 0 0/0
g d e
1/1 1/1
outpu

0 0 0 0 0 1 1 0 1 0 0 0/0 1/1
f
t

1/ 1
 88

STATE REDUCTION AND ASSIGNMENT

• Two circuits are equivalent
– Have identical outputs for all input sequences;

– The number of states is not important.

• The problem of state reduction is

– To find ways of reducing the number of states in a sequential circuit
without altering the input – output relationships.
 89

STATE REDUCTION AND ASSIGNMENT

• Equivalent States
– Two states are said to be equivalent if,
• For each member of the set of inputs,

• they give exactly the same output and

• send the circuit to the same state or to an equivalent state.

– When two states are equivalent, one of them can be removed
without altering the input – output relationships.
 90

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states 0/0

a
– Draw a state table 0/0 0/0
Next state Output 1/0

0/0 0/0
Present state x=0 x=1 x=0 x=1 b c
a a b 0 0 1/0
1/0
b c d 0 0
0/0
c a d 0 0 g d e
d 1/1 1/1
e f 0 1
e 0/0 1/1
a f 0 1
f
f g f 0 1
1/1
g a f 0 1
 91

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
– e = g (remove g)
Present Next state Output
– The row g is removed. state x=0 x=1 x=0 x=1
a a b 0 0
– State g is replaced by state e
b c d 0 0
each time it occurs in the
c a d 0 0
next – state columns. d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
 92

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
– Present state f has now next
Present Next state Output
states e and f and outputs 0 state x=0 x=1 x=0 x=1
and 1 for x = 0 and x = 1. a a b 0 0
b c d 0 0
– Then, d = f (remove f)
c a d 0 0
– The row f is removed. d e f 0 1
e a f 0 1
– The state f is replaced by
f e f 0 1
state d.
 93

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
– Final table
Present Next state Output
– This table satisfies the state x=0 x=1 x=0 x=1
original input – output a a b 0 0
b c d 0 0
specifications and will
c a d 0 0
produce the required output d e d 0 1
sequence for any given input e a d 0 1

sequence.
 94

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
0/0

Present Next state Output a

state x=0 x=1 x=0 x=1
0/ 0 1/ 0 0/ 0
a a b 0 0
0/ 0
b c d 0 0 g b c
c a d 0 0 1/ 1 1/ 0
d e d 0 1 0/ 0 1/ 0

e d
a d 0 1
1/ 1
 95

STATE REDUCTION AND ASSIGNMENT

• Reduce the number of states
– The checking of each pair of states for possible equivalence can be
done systematically using Implication Table.

– The unused states are treated as don't-care condition Þ fewer

combinational gates.
 96

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– The state-reduction procedure for completely specified state tables is based
on the algorithm that two states in a state table can be combined into one if
they can be shown to be equivalent. There are occasions when a pair of
states do not have the same next states, but, nonetheless, go to equivalent
next states. Consider the following state table:
 97

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– Consider the following state Present Next state Output
table: state x=0 x=1 x=0 x=1
a c b 0 1
– (a, b) imply (c, d) and (c, d) imply
b d a 0 1
(a, b). Both pairs of states are
c a d 1 0
equivalent; i.e., a and b are d b d 1 0
equivalent as well as c and d.
 98

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– The checking of each pair of states for possible equivalence in a table with a
large number of states can be done systematically by means of an
implication table. This a chart that consists of squares, one for every
possible pair of states, that provide spaces for listing any possible implied
states. Consider the following state table:
 99

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– Consider the following state table: Implication table:

Next state Output

Present state x=0 x=1 x=0 x=1
a d b 0 0
b e a 0 0
c g f 0 1
d a d 1 0
e a d 1 0
f c b 0 0
g a e 1 0
 100

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– On the left side along the vertical are listed all the states defined in the state
table except the last, and across the bottom horizontally are listed all the
states except the last.

– The states that are not equivalent are marked with a ‘x’ in the corresponding
square, whereas their equivalence is recorded with a ‘√’.
 101

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– Some of the squares have entries of implied states that must be further
investigated to determine whether they are equivalent or not.

– The step-by-step procedure of filling in the squares is as follows:

1. Place a cross in any square corresponding to a pair of states whose outputs are not
equal for every input.

2. Enter in the remaining squares the pairs of states that are implied by the pair of states
representing the squares. We do that by starting from the top square in the left
column and going down and then proceeding with the next column to the right.
 102

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
3.Make successive passes through the table to determine whether any
additional squares should be marked with a ‘x’. A square in the table is crossed
out if it contains at least one implied pair that is not equivalent.

4.Finally, all the squares that have no crosses are recorded with check marks.
The equivalent states are: (a, b), (d, e), (d, g), (e, g).
 103

STATE REDUCTION AND ASSIGNMENT

• Implication Table (extra reading)
– We now combine pairs of states into larger groups of equivalent
states. The last three pairs can be combined into a set of three
equivalent states (d, e,g) because each one of the states in the
group is equivalent to the other two. The final partition of these
states consists of the equivalent states found from the implication
table, together with all the remaining states in the state table that
are not equivalent to any other state:

– (a, b) (c) (d, e, g) (f)

 104

STATE REDUCTION AND ASSIGNMENT

• State Assignment
– In order to design a sequential circuit with physical components, it is
necessary to assign coded binary values to the states.

– To minimize the cost of the combinational circuits.

– For a circuit with m states, the codes must contain n bits where 2n =
≥ m.
– Ex: with 3 bits it is possible to assign codes to 8 states denoted by
binary numbers 000 trough 111.
 105

STATE REDUCTION AND ASSIGNMENT

• State Assignment
– If the state table1 is used, we must assign binary values to 7 states.
• Remaining state is unused.

– If the state table2 is used, only five states need binary assignment.
• Remaining 3 state is unused.
• Unused states treated as don’t care conditions.
• Since don’t care conditions usually help in obtaining a simpler circuit, it is
more likely that the circuit with five states will require fewer
combinational gates than the one with seven states.
 106

STATE REDUCTION AND ASSIGNMENT

• State Assignment
Present Assignment 1 Assignment 2 Assignment 3
state Binary Gray Code One-hot
a 000 000 00001
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000
 10
7

STATE REDUCTION AND ASSIGNMENT

• State Assignment
Present Next state Output
– Any binary number
state x=0 x=1 x=0 x=1
assignment is satisfactory as 000 000 001 0 0
long as each state is 001 010 011 0 0
010 000 011 0 0
assigned a unique number.
011 100 011 0 1
– Use binary assignment 1. 100 000 011 0 1
 109

D ESI GN PRO CED U RE

• The design of a clocked sequential circuit starts from
– a set of specifications and

– culminates in a logic diagram or

– a list of Boolean functions from which the logic diagram can be
obtained.
 110

D ESI GN PRO CED U RE

1. Derive a state diagram for the circuit from the word description.
2. Reduce the number of states if necessary.

3. Assign binary values to the states.

4. Obtain the binary-coded state table.

5. Choose the type of flip-flops.

6. Derive the simplified flip-flop input equations and output equations.

7. Draw the logic diagram.
 111

D ESI GN PRO CED U RE

• Example: We wish to design a circuit that detects three or more
consecutive 1’s in a string of bits coming through an input line.
0 1
• State diagram:
S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1
1
 112

D ESI GN PRO CED U RE

• This is a Moore model
0 1
sequential circuit since the
S0 / 0 S1 / 0 output is 1 when the circuit is
0
in State3 and 0 otherwise.
0 1
0
State A B
S0 0 0
S3 / 1 S2 / 0 S1 0 1
1
1 S2 1 0
S3 1 1
 113

D ESI GN PRO CED U RE

Present Next
I/P O/P
0 State State
1
A B x A B y
S0 / 0 S1 / 0 0 0 0 0 0 0

0 0 0 1 0 1 0
0 1 0 0 0 0
0 1
0 0 1 1 1 0 0
1 0 0 0 0 0
S3 / 1 S2 / 0 1 0 1 1 1 0
1
1 1 1 0 0 0 1
1 1 1 1 1 1
 114

D ESI GN PRO CED U RE

• To implement the circuit,
– Two D flip-flops are chosen to represent the four states and label
their outputs A and B.

– There is one input x.

– There is one output y.

– The characteristic equation of the D flip – flop is

• Q(t+1) = DQ.
 11
5

D ESI GN PRO CED U RE

Present Next
• To implement the circuit, I/P O/P
State State
– The flip – flop input equations A B x A B y
can be obtained directly from 0 0 0 0 0 0
the next – state columns of A 0 0 1 0 1 0

and B and expressed in sum of 0 1 0 0 0 0

minterms. 0 1 1 1 0 0
1 0 0 0 0 0
– A(t+1) = DA(A,B,x) = ∑ (3, 5, 7)
1 0 1 1 1 0
– B(t+1) = DB(A,B,x) = ∑ (1, 5, 7) 1 1 0 0 0 1
– y(A,B,x) = ∑ (6, 7) 1 1 1 1 1 1
 11
6

D ESI GN PRO CED U RE

• Synthesis using D Flip - flops • DA’s K - Map
– A(t+1) = DA(A,B,x) = ∑ (3, 5, 7)
– B(t+1) = DB(A,B,x) = ∑ (1, 5, 7) Bx B
A 00 01 11 10
– y(A,B,x) = ∑ (6, 7) m0 m1 m3 M2
0
1
m4 m5 m7 M6
A 1
1 1

DA = Ax + Bx
 11
7

D ESI GN PRO CED U RE

• Synthesis using D Flip – flops • DB’s K - Map
– A(t+1) = DA(A,B,x) = ∑ (3, 5, 7)
– B(t+1) = DB(A,B,x) = ∑ (1, 5, 7) Bx B
A 00 01 11 10
– y(A,B,x) = ∑ (6, 7) m0 m1 m3 M2
0
1
m4 m5 m7 M6
A 1
1 1

DA = Ax + B’x
 11
8

D ESI GN PRO CED U RE

• Synthesis using D Flip – flops • y’s K - Map
– A(t+1) = DA(A,B,x) = ∑ (3, 5, 7)
– B(t+1) = DB(A,B,x) = ∑ (1, 5, 7) Bx B
A 00 01 11 10
– y(A,B,x) = ∑ (6, 7) m0 m1 m3 M2
0

m4 m5 m7 M6
A 1
1 1

y = AB
 11
9

D ESI GN PRO CED U RE

• Synthesis using D Flip – flops • Logic Diagram of Sequence
– DA = Ax + Bx Detector
– DB = Ax + B’x
x D Q A
– y = AB
Q
y

D Q B

CLK Q
 120

D ESI GN PRO CED U RE

• When – D type flip-flops are employed, the input equations are obtained
directly from the next state.
• This is not the case for the JKand T types of flip-flops. In order to
determine the input equations for these flip flops, it is necessary to
derive a functional relationship between the state table and the input
equations.
 121

D ESI GN PRO CED U RE

• During the design process we usually know the transition from present
state to the next state and wish to find the flip – flop input conditions
that will cause the required transition.

• For this reason, we need a table that lists the required inputs for a given
change of state. Such table is called an excitation table.
 122

D ESI GN PRO CED U RE

• D Flip – Flop Excitation table

Present Next F.F.

D Flip – Flop Characteristic Table
State State Input
D Q (t+1) Q(t) Q(t+1) D
0 0 0 0 0

1 1 0 1 1

1 0 0
Q(t+1) = D
1 1 1
 123

D ESI GN PRO CED U RE

• JK Flip – Flop Excitation table

Present Next F.F.

JKFlip – Flop Characteristic Table
State State Input
J K Q (t+1)
Q(t) Q(t+1) J K 0 0 (No change)
0 0 Q(t) 1 1 (Reset)
0 0 0 X
2 0 (Set)
0 1 0 0 1 1 1 (Toggle)
1 X
1 0 1 1 1 (Reset)
1 0 X 1 2 1 (Toggle)
1 1 Q’(t) 1 1 X 0 3 0 (No change)
4 0 (Set)
Q(t+1) = JQ’ + K’Q
 124

D ESI GN PRO CED U RE

• T Flip – Flop Excitation table

Present Next F.F.

T Flip – Flop Characteristic Table
State State Input
T Q (t+1) Q(t) Q(t+1) T

0 Q(t) 0 0 0

1 Q’(t) 0 1 1
1 0 1
Q(t+1) = T Q 1 1 0
 125

D ESI GN PRO CED U RE

• Synthesis Using JK Flip – Flops: Detect 3 or more consecutive 1’s

0 1

S0 / 0 S1 / 0
0

0 1
0

S3 / 1 S2 / 0
1
1
 126

D ESI GN PRO CED U RE

• Synthesis Using JK Flip – Flops: Detect 3 or more consecutive 1’s
Present Next Flip-Flop
Input
State State Inputs
A B x A B JA KA JB KB
0 0 0 0 0 0 X 0 X JA (A, B, x) = ∑ (3, 4, 5, 6, 7)
0 0 1 0 1 0 X 1 X
KA (A, B, x) = ∑ (0, 1, 2, 3, 4, 6)
0 1 0 0 0 0 X X 1
0 1 1 1 0 1 X X 1 JB (A, B, x) = ∑ (1, 2, 3, 5, 6, 7)
1 0 0 0 0 X 1 0 X KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5, 6)
1 0 1 1 1 X 0 1 X
1 1 0 0 0 X 1 X 1
1 1 1 1 1 X 0 X 0
 12
7

D ESI GN PRO CED U RE

• Synthesis Using JKFlip – Flops: • JA’s K-Map
Detect 3 or more consecutive 1’s
– JA (A, B, x) = ∑ (3, 4, 5, 6, 7) Bx B
A 00 01 11 10
– KA (A, B, x) = ∑ (0, 1, 2, 3, 4, 6)
m0 m1 m3 m2
– JB(A, B, x) = ∑ (1, 2, 3, 5, 6, 7) 0
1
– KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5, 6) m4 m5 m7 m6
A 1
X X X X

JA = Bx
 12
8

D ESI GN PRO CED U RE

• Synthesis Using JKFlip – Flops: • KA’s K-Map
Detect 3 or more consecutive 1’s
– JA (A, B, x) = ∑ (3, 4, 5, 6, 7) Bx B
A 00 01 11 10
– KA (A, B, x) = ∑ (0, 1, 2, 3, 4, 6)
m0 m1 m3 m2
– JB(A, B, x) = ∑ (1, 2, 3, 5, 6, 7) 0
X X X X
– KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5, 6) m4 m5 m7 M6
A 1
1 1

KA = x’
 12
9

D ESI GN PRO CED U RE

• Synthesis Using JKFlip – Flops: • JB’s K-Map
Detect 3 or more consecutive 1’s
– JA (A, B, x) = ∑ (3, 4, 5, 6, 7) Bx B
A 00 01 11 10
– KA (A, B, x) = ∑ (0, 1, 2, 3, 4, 6)
m0 m1 m3 m2
– JB(A, B, x) = ∑ (1, 2, 3, 5, 6, 7) 0
1 X X
– KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5, 6) m4 m5 m7 M6
A 1
1 X X

JB = x
 13
0

D ESI GN PRO CED U RE

• Synthesis Using JKFlip – Flops: • KB’s K-Map
Detect 3 or more consecutive 1’s
– JA (A, B, x) = ∑ (3, 4, 5, 6, 7) Bx B
A 00 01 11 10
– KA (A, B, x) = ∑ (0, 1, 2, 3, 4, 6)
m0 m1 m3 m2
– JB(A, B, x) = ∑ (1, 2, 3, 5, 6, 7) 0
X X 1 1
– KB (A, B, x) = ∑ (0, 1, 2, 3, 4, 5, 6) m4 m5 m7 m6
A 1
X X 1

KB = A’+ x’
 13
1

D ESI GN PRO CED U RE

• Synthesis Using JKFlip – Flops: • Logic Diagram of Sequence
Detect 3 or more consecutive 1’s Detector
– JA = Bx
– KA = x’ J Q A

– JB = x
x K Q y
– KB = A’ + x’

J Q B

K Q

CLK
 132

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3-bit Counter. An n-bit binary
counter consists of n flip – flops that can count in binary from 0
to 2n – 1. 000
111 001

110 010

101 011
100
 133

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3-bit Counter.
Present Next Flip-Flop
State State Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1 TA2 (A2, A1, A0) = ∑ (3, 7)
0 0 1 0 1 0 0 1 1
TA1 (A2, A1, A0) = ∑ (1, 3, 5, 7)
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1 TA0 (A2, A1, A0) = ∑ (0, 1, 2, 3, 4, 5, 6, 7)
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
 13
4

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3- • TA2’s K-Map
bit Counter.
– TA2 (A2, A1, A0) = ∑ (3, 7) A1A0 A1
A2 00 01 11 10
– TA1 (A2, A1, A0) = ∑ (1, 3, 5, 7)
m0 m1 m3 m2
– TA0 (A2, A1, A0) = ∑ (0, 1, 2, 3, 4, 5, 0
1
6, 7) m4 m5 m7 m6
A 1
1

A0

TA2 = A1A0
 13
5

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3- • TA1’s K-Map
bit Counter.
– TA2 (A2, A1, A0) = ∑ (3, 7) A1A0 A1
A2 00 01 11 10
– TA1 (A2, A1, A0) = ∑ (1, 3, 5, 7)
m0 m1 m3 m2
– TA0 (A2, A1, A0) = ∑ (0, 1, 2, 3, 4, 5, 0
1 1
6, 7) m4 m5 m7 m6
A 1
1 1

A0

TA1 = A0
 13
6

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3- • TA0’s K-Map
bit Counter.
– TA2 (A2, A1, A0) = ∑ (3, 7) A1A0 A1
A2 00 01 11 10
– TA1 (A2, A1, A0) = ∑ (1, 3, 5, 7)
m0 m1 m3 m2
– TA0 (A2, A1, A0) = ∑ (0, 1, 2, 3, 4, 5, 0
1 1 1 1
6, 7) m4 m5 m7 m6
A 1
1 1 1 1

A0

TA0 = 1
 13
7

D ESI GN PRO CED U RE

• Synthesis Using T Flip – Flops: 3- • Logic Diagram of 3-bit Binary
bit Counter. Counter
– TA2 = A1A0 T Q A2

– TA1 = A0 Q

– TA0 = 1
T Q A1

1 T Q A0

CLK