Chapter four

Register Transfer Language

and Micro Operations

COMPUTER ORGANIZATION AND ARCHITECTURE

By ahmed s.
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 Register Transfer Language
Microoperation
• Is the operations executed on data stored in registers (shift, clear, load, count).
Internal Hard Ware Organization(best defined by specifying)
1. The set of registers it contains and their functions
2. The sequence of microoperations.
3. The sequence control of microoperations.
 Register Transfer Language (RTL)
• The symbolic notation used to describe the microoperation transfer among
registers.
• The use of symbols instead of a narrative explanation provides an organized and
concise manner
• So that, a RTL is a convenient tool for describing the internal organization of
digital computers in concise and precise manner 2
 REGISTER TRANSFER
• Registers :
Designated by Capital Letter(sometimes followed by numerals)
to denote the function of the register. See fig 4-1
 For example:
 MAR(Memory Address Register) => to hold memory address
PC(Program Counter) => to hold the address of next instruction
IR(Instruction Register) => to hold instruction code
DR(Data Register) => to hold memory data
AC(Accumulator) => general purpose processing register
R1(Processor Register) => Processing register

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 Contd…
The individual F/Fs in an n-bit register is numbered in sequence from 0(rightmost position)
through n-1.
The numbering of bits in a 16-bit register is marked on top of the box.
A 16-bit register partitioned into two parts : bit 0-7(symbol “L” Low byte), bit 8-15(symbol “H”
High byte).

Fig. 4-1 Block diagram of

registers
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 Contd…
Transfer of the contents of one register to another is a register transfer, and can
be designated in symbolic form.
 The statement : R2 ← R1 , denotes
A transfer of the content of register R1 into register R2(replacement of the content of R2
by the content of R1).
A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse.
The content of the source register R1 does not change after the transfer.
 A register transfer such as : R2 ← R1, Implies that the digital system has:
The data lines from the source register (R1) to the destination register (R2)
Parallel load in the destination register (R2)
Control lines to perform the action

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 CONTROL FUNCTIONS

Normally, the transfer action is occur only when a predetermined control

condition is true .
This can be shown by means of an if‐then statement, as follow:
• If(P = 1) then (R2 ← R1), where p is control signal
A control function is a Boolean variable that is equal to 1 or 0.
The control condition is terminated with a CoIon:
P: R2 ← R1, which means “if P = 1, then load the contents of register R1 into
register R2”, i.e., if (P = 1) then (R2 ← R1)
Every statement written in a register transfer notation implies a hardware
construction for implementing the transfer.
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 HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFER
S
Figure 3-2 shows the Implementation of controlled transfer:
P: R2 ← R1
The n-output of register R1 are connected to the n-inputs of register R2, where
n is the number of bits of register.
Register R2 has a load input that is
activated by the control variable P.
The same clock controls the circuits
that generate the control function and Fig. 4-2 a) Block diagram of P: R2 ← R1

the two registers.

 It is assumed that the control variable is synchronized with the same clock as
the one applied to the registers.
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 BASIC SYMBOLS FOR REGISTER TRANSFER
symbols Description Example
Capital letters and Denotes a register MAR,R2
numerals
Parentheses () Denotes parts of a register R2(0-7), R2(L)
Arrow ← Denotes transfer of information R2←R1
Colon : Denotes termination of control P:
function
Comma , Separates two micro-operations A←B, B←A

If two or more operations are to occur simultaneously, they are separated
with commas
P: R3 ← R5, MAR ← IR
Here, if the control function P = 1, load the contents of R5 into R3, and at
the same time (clock), load the contents of register IR into register MAR.
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 Bus and Memory Transfers
A typical digital computer has many registers, and paths must be provided to
transfer information from one register to another.
The number of wires will be excessive if separate lines are used b/n each
register in the system.
A more efficient scheme for transferring information b/n registers in a
multiple‐register configuration is a common bus system.
Bus is a path(of a group of wires) over which information is transferred, from any of
several sources to any of several destinations.
Control signals determine which register is selected by the bus
during each particular register transfer.
One way of constructing a common bus system is with multiplexers.
The multiplexers select the source register whose binary information is then placed
on the Bus 9
 contd…
 The construction of a Bus system for four registers is shown in fig. 4-3

Fig. 4-3. Bus system by using MUXs.

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 Cont’d…
 Each register has 4-bits, so that the bus system has 4-common lines.
 The bus consists of four 4x1 multiplexers each having four data inputs, and two selection inputs lines, S1 and
S0.
 Each register are of 4‐bit register, so we need 4‐MUXs to carry the 4‐bits of register on 4‐line
common bus(one line carry only one bit at a time).
 Multiplexers are to select one of four registers and transfer its content to the
4‐line common bus
 The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers.
 The selection lines choose the four bits of one register and transfer them into the 4‐lines
common bus.
 When S1So = 00,the 0 data inputs of all four multiplexers are selected and
applied to the outputs that form the bus.
 This causes the bus lines to receive the content of register A
 Similarly, register B is selected if S1S0 = 01, and so on.
 Table 4‐2 shows the register that is selected by the bus for each of the four possible binary 11
 Cont’d…
The bits in the same significant position in each register are connected to the
corresponding number of MUX. S0 S1 Register Selected
For example: since register A 0 0 A
is selected by S1S0=00, 0 1 B
A0 is connected to input 0 of
1 0 C
MUX 0, 1 1 D
A1 is connected to input 0
of MUX 1
A2 is connected to input 0 of MUX 2 Table 4-2 Function table for bus fig4-3
A3 is connected to input 0 of MUX 3
Similarly, register B is selected by S1S0=01,
B0 is connected to input 1 of MUX 0 ,B1 is connected to input 1 of MUX 1,
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B2 is connected to input 1 of MUX 2, B3 is connected to input 1 of MUX 3 and so on.
 Cont’d…
In general, a bus system which multiplex k registers of n‐bits each to produce an
n‐line common bus.
The number of multiplexers needed to construct the bus is equal to n,
the number of bits in each register.
The size of each multiplexer must be k x 1 since it muItipIexes k data lines.
For example:‐ A digital computer has a common bus system for 8 registers of 16 bits
each.
a)What size of MUXs are needed?
b)How many MUXs are there in the Bus?
c)How many selection inputs are there in each MUX?
Solution:‐
a)Since there are 8 registers, we need size of 8x1 MUXs
b)Since each register are with 16‐bits , there are 16 MUXs in the Bus.
c)Since each MUXs are with 8x1, 3 selection lines inputs in each MUXs. 13
 Cont’d…
The transfer of information from a bus into one of many destination registers can be
accomplished by connecting the bus lines to the inputs of all destination
registers and activating the load control of the particular destination register selected.
The symbolic statement for a bus transfer may mention the bus or
its presence may be implied in the statement.
 When the bus is includes in the statement, the register transfer is symbolized as
follows: BUS ← R1, R2 ← BUS
The content of register R1 is placed on the bus, and the content of the BUS is
loaded into register R2 by activating its load control input.
If the bus is known to exist in the system, it may be convenient just to show the direct
transfer.
R2 ← R1 14
 THREE STATE BUS BUFFERS
A Bus system can be constructed with three‐state gates instead of MUXs.
A three‐state gate is a digital circuit that exhibits three states.
These states are 0, 1, High‐impedance(Open circuit)
 Buffer is:
A device designed to be inserted between other devices to match impedance,
to prevent mixed interactions, and to supply additional drive or relay capability.
Buffer types are classified as inverting or noninverting
 Tri‐state buffer gate: Figure 4-4 Graphic symbol for three-sate buffer.
When control input =1 :
The output is enabled(output Y = input A)
When control input =0 :
The output is disabled(output Y = high‐impedance) 15
 Cont’d …
The construction of a bus system with three‐state buffer is demonstrated in
fig 4-5.
A0
The outputs of four buffer are connected B0
Bus line for bit 0

together to form a single bus line(Tristate C0

D0
buffer).
Select input S1 0

No more than one buffer may be S0 2* 4 1

Enable input E
dec o der
2

in the active state at any given 3

fig. 4-5. bus system using three‐state buffers

time(the 2X 4 Decoder is to control the buffers)
To construct a common bus for 4 register with n‐bits each using three‐state
buffers, we need n circuits with 4 buffers in each as shown in fig. 4-5.
Each group of 4 buffers receives one‐bit from the 4 registers.
Since each registers are with n‐bits, the total common bus lines will be n. 16
 MEMORY TRANSFER
 The two operations of Memory unit are Read and Write.
 Memory read :‐ The transfer of information from a memory word to the outside
environment.
 Memory write:‐The transfer of new information to be stored into the memory.
 A memory word will be symbolized by M and, Particular memory word among
the many available is selected by memory address.
 This will be done by enclosing the address in square brackets following letter
M (M[AR]).
 The read operation can be stated as follows:
Read: DR ← M[AR],
where, DR = data register, AR = address register, M[AR] = memory word
 This causes a transfer of information into DR from the memory word M selected by the address in AR.
 The write operation can be stated as follows: (assume that the input data are in register R1 and the addre
ss is in AR.)
Write: M[AR]← R1 17
 Quiz -2 5%
 A digital computer has a common bus system for 16 registers of 32 bits each.
a) What size of MUXs are needed? (2 point)
b) How many MUXs are there in the Bus? (2 point)
c) How many selection inputs are there in each MUX? (1 point)

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 ARITHMETIC MICROOPERATIONS
A microopration is an elementary operation performed with the data stored in
a registers.
The microoprations most often encountered in digital computer are classified ino four categ
ories:
Register transfer microoperations(transfer of binary information).
Arithmetic microoperations( Arithmetic operation on numeric data).
Logic microoperations (logical operation on non‐numeric data).
Shift microoperations (shift operation on data stored in register).
Register transfer microoperations was introduces in pervious sections.
In this section we introduce a set of Arithmetic microoperations.
The basic Arithmetic microoperations are:
Addition
Subtraction
Increment 19
 Cont’d…
The arithmetic microoperation defined by the statement, R3 ←R1 + R2, specifies an
add microoperation.
It state the Contents of R1 plus R2 transferred to R3.
The other basic arithmetic microoperations are listed in table 4-3.
Table 4-3. Summary of Typical Arithmetic Micro-Operations

Subtraction can be done using complementation and addition like :

R3 ← R1 ‐ R2 = > R3 ← R1 + R2’+ 1
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
 LOGIC MICROOPERATIONS
Logic microoperations are bit‐
wise operations, i.e., they work on the individual bits of data.
These operations consider each bit of the register separately and treat them as binary va
riables.
For example,the exclusive‐OR microoperation with the contents of two registes R1
and R2 is symbolized by the statement :
P : R1 ← R1 ⊕ R2
Let, R1 =1010 and R2 =1100 , the exclusive‐OR logic computation will be done bit‐by‐
bit on pairs of bits as following:
1010 Content of R1
⊕ 1100 Content of R2
0110 Content of R1 after P=1
Logic microoperations useful for bit manipulations on binary data and for making 21
 Cont’d
 Special symbols will be adopted for …
the logic microoperations
OR (),
AND (), and
Complement(a bar on top ), to distinguish them from the corresponding symbols used
to express Boolean functions
 By using different symbols, it will be possible to differentiate between logic microoperations
and a control( or Boolean) function.
 The reason is to distinguish the symbol “ + “, when used to symbolized arithmetic plus or
logic OR operation.
 When the symbol + occurs in a microoperation, it denote arithmetic plus and when it occurs
in a control function, it denote logic OR operation
 We will never use “ + “ to symbolize an OR microoperation.
 Example:

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 LIST OF LOGIC MICROOPERATIONS
• There are, in principle, 16 different logic operations that can be defined over two binary input
variables(X and Y)
• Truth Table for 16 logic functions for 2 variables is shown as below : Tab. 4-4

• In the table, each of the 16 columns F0 through F15 represents a truth table of one possible
Boolean function for the two variables X and Y.
• The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first
column of table 4-4.
• The corresponding 16 logic micro-operations are derived from these function by replacing 23
 Cont’d…
• The corresponding 16 logic micro-operations are listed as below

Boolean Function Micro-Operations Name

F0 =0 F0 Clear
F1 = xy FAB AND
F2 = xy' F  A  B’
F3 =x FA Transfer A
F4 = x'y F  A’ B
F5 = y FB Transfer B
F6 =xy FAB Exclusive-
OR
F7 = x + y FAB OR
F8 = (x + y)' F  A  B)’ NOR
F9 = (x  y)‘ F  (A  B)’ Exclusive-
NOR
F10 = y' F  B’
Complement B
F11 = x + y' FAB
F12 = x' F  A’ Complement A 24
 SHIFT MICROOPERATIONS
• Shift microoperations are used for serial transfer of data.
• The content of a register can be shifted to the right or the left.
• During a shift-left operation the serial input transfers a bit into the rightmost position.
SI

• During a shift-right operation the serial input transfers a bit into the leftmost position.
SI

• There are three types of shifts:

Logical shift
Circular shift and
Arithmetic shift
• The information transferred through the serial input determines the type of shift.
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 LOGICAL SHIFT
 A logical shift is one that transfers 0 through the serial input.
 We have two logical shift:

0 A logical right-shift operation

A logical left-shift operation

0

 We will adopt the symbols shl and shr for logical shift-left and shift- right
microoperations respectively.
 Examples: R1  shr R1 , R2  shl R2
Specify a 1-bit shift to the right of the content of register R1 and a 1-bit shift to the left
of the content of register R2.
The register symbol must be the same on both sides of the arrow.
The bit transferred to the end position through the serial input is assumed to be 026 during
 CIRCULAR SHIFT
• The circular shift (also known as a rotate operation) circulates the bits of the
register around the two ends without loss of information.
• This is accomplished by connecting the serial output of the shift register to its
serial input.
• In a circular shift the serial input is the bit that is shifted out of the other end of
the register.
• A right circular shift operation: A left circular shift operation:

• In a RTL, the following notation is used

• Cil for a circular shift left
• Cir for a circular shift right
• Examples:
• R2  cir R2
• R3  cil R3 27
 ARITHMETIC SHIFT
 An arithmetic shift is a microoperation that shifts a signed binary number to-the
left or right.
 An arithmetic shift-left multiplies a signed binary number by 2 and An
arithmetic shift-right divides the number by 2.
 Arithmetic shifts must leave the sign bit unchanged because the sign of the
number remains the same when it is multiplied or divided by 2.
 The Leftmost bit in a register holds the sign bit, and the remaining bits hold
the number.
 The sign bit is 0 for positive and 1 is for negative.
 Negative numbers are in 2’s complement form.
 There are two arithmetic shift microoperations
Arithmetic shift-right and => ashr
Arithmetic shift-left => ashl
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 A RIGHT ARITHMETIC SHIFT OPERATION:
• Figure 4-8 shows a typical register of n bits arithmetic shift-right operation:

Figure 4-8 Arithmetic shift-right

• Bit Rn-1 in the left most position holds the sign bit.
• Rn-2 is the MSB of the number and R0 is LSB of the number.
• Arithmetic shift-right leaves the sign bit unchanged and shifts the number
(including the sign bit) to the right.
• Thus, Rn-1 remains the same, Rn-2 receives the bit from Rn-1 , and so on for the other
bits in the register, and the bit in R0 is lost.
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 A LEFT ARITHMETIC SHIFT OPERATION:
• Figure 4-9 shows a typical register of n bits arithmetic shift-left operation:

Figure 4-8 Arithmetic shift-

right
• The arithmetic shift-left insert a 0 into R0 , and shifts all other bits to the left.
• The initial bit of Rn-1 is lost and replaced by the bit from Rn-2.
• A sign reversal occurs if the bit in Rn-1 change in value after the shift.

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