REGISTER TRANSFER AND MICROOPERATIONS

CONTENTS:

✓ Register Transfer Language

✓ Register Transfer

✓ Bus And Memory Transfers

✓ Types of Micro-operations

✓ Arithmetic Micro-operations

✓ Logic Micro-operations

✓ Shift Micro-operations

✓ Arithmetic Logic Shift Unit

BASIC DEFINITIONS:

➢ A digital system is an interconnection of digital hardware modules.

➢ The modules are registers, decoders, arithmetic elements, and control logic.
➢ The various modules are interconnected with common data and control paths to form a digital
computer system.
➢ Digital modules are best defined by the registers they contain and the
operations that are performed on the data stored in them.
➢ The operations executed on data stored in registers are called microoperations.
➢ A microoperation is an elementary operation performed on the information stored in one or more
registers.
➢ The result of the operation may replace the previous binary
information of a register or may be transferred to another register.
➢ Examples of microoperations are shift, count, clear, and load.
➢ The internal hardware organization of a digital computer is best defined
by specifying:

1. The set of registers it contains and their function.

2. The sequence of microoperations performed on the binary information

stored in the registers.
3. The control that initiates the sequence of microoperations.

REGISTER TRANSFER LANGUAGE:

➢ The symbolic notation used to describe the micro-operation transfer among registers is called RTL
(Register Transfer Language).
➢ The use of symbols instead of a narrative explanation provides an organized and concise manner
for listing the micro-operation sequences in registers and the control functions that initiate them.
 ➢ A register transfer language is a system for expressing in symbolic form the microoperation
sequences among the registers of a digital module.
➢ It is a convenient tool for describing the internal organization of digital computers in concise and
precise manner.

Registers:

➢ Computer registers are designated by upper case letters (and optionally followed by digits or
letters) to denote the function of the register.
➢ For example, the register that holds an address for the memory unit is usually called a memory
address register and is designated by the name MAR.
➢ Other designations for registers are PC (for program counter), IR (for instruction register, and R1
(for processor register).
➢ The individual flip-flops in an n-bit register are numbered in sequence from 0 through n-1, starting
from 0 in the rightmost position and increasing the numbers toward the left.
➢ Figure 4-1 shows the representation of registers in block diagram form.

➢ The most common way to represent a register is by a rectangular box with the name of the
register inside, as in Fig. 4-1(a).
➢ The individual bits can be distinguished as in (b).
➢ The numbering of bits in a 16-bit register can be marked on top of the box as shown in (c).
➢ 16-bit register is partitioned into two parts in (d). Bits 0 through 7 are assigned the symbol L (for
low byte) and bits 8 through 15 are assigned the symbol H (for high byte).
➢ The name of the 16-bit register is PC. The symbol PC (0-7) or PC (L) refers to the low-order byte
and PC (8-15) or PC (H) to the high-order byte.

Register Transfer:

➢ Information transfer from one register to another is designated in symbolic form by means of a
replacement operator.
➢ The statement R2← R1 denotes a transfer of the content of register R1 into register R2.
➢ It designates a replacement of the content of R2 by the content of R1.
➢ By definition, the content of the source register R 1 does not change after the transfer.
➢ If we want the transfer to occur only under a predetermined control condition then it can be
shown by an if-then statement.
if (P=1) then R2← R1
➢ P is the control signal generated by a control section.
➢ We can separate the control variables from the register transfer operation by specifying a Control
Function.
➢ Control function is a Boolean variable that is equal to 0 or 1.
➢ control function is included in the statement as
P: R2← R1
➢ Control condition is terminated by a colon implies transfer operation be executed by the
hardware only if P=1.
➢ Every statement written in a register transfer notation implies a hardware construction for
implementing the transfer.
➢ Figure 4-2 shows the block diagram that depicts the transfer from R1 to R2.

➢ The n outputs of register R1 are connected to the n inputs of register R2.

➢ The letter n will be used to indicate any number of bits for the register. It will be replaced by an
actual number when the length of the register is known.
➢ Register R2 has a load input that is activated by the control variable P.
➢ It is assumed that the control variable is synchronized with the same clock as the one applied to
the register.
➢ As shown in the timing diagram, P is activated in the control section by the rising edge
of a clock pulse at time t.
➢ The next positive transition of the clock at time t + 1 finds the load input active and the data inputs
of R2 are then loaded into the register in parallel.
 ➢ P may go back to 0 at time t+1; otherwise, the transfer will occur with every clock pulse transition
while P remains active.
➢ Even though the control condition such as P becomes active just after time t, the actual transfer
does not occur until the register is triggered by the next positive transition of the clock at time
t +1.
➢ The basic symbols of the register transfer notation are listed in below table

Symbol Description Examples

Letters(and numerals) Denotes a register MAR, R2

Parentheses ( ) Denotes a part of a register R2(0-7), R2(L)

Arrow <-- Denotes transfer of information R2 <-- R1

Comma , Separates two microoperations R2 <-- R1, R1 <-- R2

➢ A comma is used to separate two or more operations that are executed at the same time.
➢ The statement
T : R2← R1, R1← R2 (exchange operation)
denotes an operation that exchanges the contents of two rgisters during one common clock pulse
provided that T=1.

Bus and Memory Transfers:

➢ A more efficient scheme for transferring information between registers in a multiple-register
configuration is a Common Bus System.
➢ A common bus consists of a set of common lines, one for each bit of a register.
➢ Control signals determine which register is selected by the bus during each particular register
transfer.
➢ Different ways of constructing a Common Bus System
✓ Using Multiplexers
✓ Using Tri-state Buffers

Common bus system is with multiplexers:

➢ The multiplexers select the source register whose binary information is then placed
on the bus.
➢ The construction of a bus system for four registers is shown in below Figure.
➢ The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two
selection inputs, S1 and S0.
➢ For example, output 1 of register A is connected to input 0 of MUX 1 because this input is labelled
A 1.
➢ The diagram shows that the bits in the same significant position in each register are connected to
the data inputs of one multiplexer to form one line of the bus.
➢ Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the
registers, and similarly for the other two bits.
➢ The two selection lines Si and So are connected to the selection inputs of all four multiplexers.
➢ The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
➢ When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs
that form the bus.
➢ This causes the bus lines to receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.
➢ Similarly, register B is selected if S1S0 = 01, and so on.
➢ Table 4-2 shows the register that is selected by the bus for each of the four possible binary value
of the selection lines.

➢ In general a bus system has

✓ multiplex “k” Registers
 ✓ each register of “n” bits
✓ to produce “n-line bus”
✓ no. of multiplexers required = n
✓ size of each multiplexer = k x 1
➢ When the bus is includes in the statement, the register transfer is symbolized as follows:
BUS← C, R1← BUS
➢ The content of register C is placed on the bus, and the content of the bus is loaded into register R1
by activating its load control input. If the bus is known to exist in the system, it may be convenient
just to show the direct transfer.

R1← C

Three-State Bus Buffers:

➢ A bus system can be constructed with three-state gates instead of multiplexers.

➢ A three-state gate is a digital circuit that exhibits three states.
➢ Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.
➢ The third state is a high-impedance state.
➢ The high-impedance state behaves like an open circuit, which means that the output is
disconnected and does not have logic significance.
➢ Because of this feature, a large number of three-state gate outputs can be connected with wires
to form a common bus line without endangering loading effects.
➢ The graphic symbol of a three-state buffer gate is shown in Fig. 4-4.

➢ It is distinguished from a normal buffer by having both a normal input and a control input.
➢ The control input determines the output state. When the control input is equal to 1, the output is
enabled and the gate behaves like any conventional buffer, with the output equal to the normal
input.
➢ When the control input is 0, the output is disabled and the gate goes to a high-impedance state,
regardless of the value in the normal input.
➢ The construction of a bus system with three-state buffers is shown in Fig. 4
 ➢ The outputs of four buffers are connected together to form a single bus line.
➢ The control inputs to the buffers determine which of the four normal inputs will communicate with
the bus line.
➢ No more than one buffer may be in the active state at any given time. The connected buffers
must be controlled so that only one three-state buffer has access to the bus line while all other
buffers are maintained in a high impedance state.
➢ One way to ensure that no more than one control input is active at any given time is to use a
decoder, as shown in the diagram.
➢ When the enable input of the decoder is 0, all of its four outputs are 0, and the bus line is in a
high-impedance state because all four buffers are disabled.
➢ When the enable input is active, one of the three-state buffers will be active, depending on the
binary value in the select inputs of the decoder.

Memory Transfer:
➢ The transfer of information from a memory word to the outside environment is called a read
operation.
➢ The transfer of new information to be stored into the memory is called a write operation.
➢ A memory word will be symbolized by the letter M.
➢ The particular memory word among the many available is selected by the memory address during
the transfer.
➢ It is necessary to specify the address of M when writing memory transfer operations.
➢ This will be done by enclosing the address in square brackets following the letter M.
➢ Consider a memory unit that receives the address from a register, called the address register,
symbolized by AR.
➢ The data are transferred to another register, called the data register, symbolized by DR.
➢ The read operation can be stated as follows:

Read: DR<- M [AR]

➢ This causes a transfer of information into DR from the memory word M selected by the address in
AR.
➢ The write operation transfers the content of a data register to a memory word M selected by the
address. Assume that the input data are in register R1 and the address is in AR.
➢ The write operation can be stated as follows:
Write: M [AR] <- R1

Types of Micro-operations:

➢ Register Transfer Micro-operations: Transfer binary information from one register to another.
➢ Arithmetic Micro-operations: Perform arithmetic operation on numeric data stored in registers.
➢ Logical Micro-operations: Perform bit manipulation operations on data stored in registers.
➢ Shift Micro-operations: Perform shift operations on data stored in registers.

➢ Register Transfer Micro-operation doesn’t change the information content when the binary
information moves from source register to destination register.
 ➢ Other three types of micro-operations change the information change the information content
during the transfer.

Arithmetic Micro-operations:
➢ The basic arithmetic micro-operations are
o Addition
o Subtraction
o Increment
o Decrement
o Shift
➢ The arithmetic Micro-operation defined by the statement below specifies the add micro-
operation.
R3 ← R1 + R2
➢ It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
➢ To implement this statement hardware requires 3 registers and digital component that performs
addition
➢ Subtraction is most often implemented through complementation and addition.
➢ The subtract operation is specified by the following statement
R3 ← R1 + R2 + 1
➢ instead of minus operator, we can write as
➢ R2 is the symbol for the 1’s complement of R2
➢ Adding 1 to 1’s complement produces 2’s complement
➢ Adding the contents of R1 to the 2's complement of R2 is equivalent to R1-R2.

Binary Adder:

➢ Digital circuit that forms the arithmetic sum of 2 bits and the previous carry is called FULL ADDER.
➢ Digital circuit that generates the arithmetic sum of 2 binary numbers of any lengths is called
BINARY ADDER.
➢ Figure 4-6 shows the interconnections of four full-adders (FA) to provide a 4-bit binary adder.

➢ The augends bits of A and the addend bits of B are designated by subscript numbers from
right to left, with subscript 0 denoting the low-order bit.
➢ The carries are connected in a chain through the full-adders. The input carry to the
binary adder is Co and the output carry is C4. The S outputs of the full-adders generate
the required sum bits.
➢ An n-bit binary adder requires n full-adders.
Binary Adder – Subtractor:
➢ The addition and subtraction operations can be combined into one common circuit by including an
exclusive-OR gate with each full-adder.
➢ A 4-bit adder-subtractor circuit is shown in Fig. 4-7.

➢ The mode input M controls the operation. When M = 0 the circuit is an adder and when M = 1 the
circuit becomes a subtractor.
➢ Each exclusive-OR gate receives input M and one of the inputs of B
➢ When M = 0, we have B xor 0 = B. The full-adders receive the value of B, the input carry is 0, and
the circuit performs A plus B.
➢ When M = 1, we have B xor 1 = B' and Co = 1.
➢ The B inputs are all complemented and a 1 is added through the input carry.
➢ The circuit performs the operation A plus the 2's complement of B.

Binary Incrementer:

➢ The increment microoperation adds one to a number in a register.

➢ For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is incremented.
➢ This can be accomplished by means of half-adders connected in cascade.
➢ The diagram of a 4-bit 'combinational circuit incrementer is shown in Fig. 4-8.

➢ One of the inputs to the least significant half-adder (HA) is connected to logic-1 and the other
input is connected to the least significant bit of the number to be incremented.
➢ The output carry from one half-adder is connected to one of the inputs of the next-higher-order
half-adder.
➢ The circuit receives the four bits from A0 through A3, adds one to it, and generates the
incremented output in S0 through S3.
➢ The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs S0
through S3 to go to 0.
 ➢ The circuit of Fig. 4-8 can be extended to an n -bit binary incrementer by extending the diagram to
include n half-adders.
➢ The least significant bit must have one input connected to logic-1. The other inputs receive the
number to be incremented or the carry from the previous stage.

Arithmetic Circuit:
➢ The basic component of an arithmetic circuit is the parallel adder.
➢ By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic
operations.
➢ The diagram of a 4-bit arithmetic circuit is shown in Fig. 4-9. It has four full-adder circuits that
constitute the 4-bit adder and four multiplexers for choosing different operations.
 ➢ There are two 4-bit inputs A and B and a 4-bit output D.
➢ The four inputs from A go directly to the X inputs of the binary adder.
➢ Each of the four inputs from B are connected to the data inputs of the multiplexers.
➢ The multiplexers data inputs also receive the complement of B.
➢ The other two data inputs are connected to logic-0 and logic-1.
➢ The four multiplexers are controlled by two selection inputs S1 and S0. The input carry Cin, goes to
the carry input of the FA in the least significant position. The other carries are connected from one
stage to the next.
➢ By controlling the value of Y with the two selection inputs S1 and S0 and making Cin equal to 0 or 1,
it is possible to generate the eight arithmetic microoperations listed in Table 44.

Addition:

➢ When S1S0= 00, the value of B is applied to the Y inputs of the adder.
✓ If Cir, = 0, the output D =A+B.
✓ If Cin = 1, output D=A+B + 1.
➢ Both cases perform the add microoperation with or without adding the input carry.

Subtraction:

➢ When S1S0 = 01, the complement of B is applied to the Y inputs of the adder.
✓ If Cin = 1, then D = A + B + 1. This produces A plus the 2's complement of B, which is
equivalent to a subtraction of A -B.
✓ When Cin = 0 then D = A + B. This is equivalent to a subtract with borrow, that is,
A-B-1.

Increment:

➢ When S1S0 = 10, the inputs from B are neglected, and instead, all 0's are inserted into the Y inputs.
The output becomes D = A + 0 + Cin. This gives D = A when Cin = 0 and D = A + 1 when Cin = 1.
➢ In the first case we have a direct transfer from input A to output D.
➢ In the second case, the value of A is incremented by 1.
Decrement:

➢ When S1S0= 11, all l's are inserted into the Y inputs of the adder to produce the decrement
operation D = A -1 when Cin = 0.
➢ This is because a number with all 1's is equal to the 2's complement of 1 (the 2's complement
of binary 0001 is 1111). Adding a number A to the 2's complement of 1 produces F = A + 2's
complement of 1 = A — 1. When Cin = 1, then D = A -1 + 1=A, which causes a direct transfer from
input A to output D.

Logic Micro-operations:

➢ Logic microoperations specify binary operations for strings of bits stored in registers.
➢ These operations consider each bit of the register separately and treat them as binary variables.
➢ For example, the exclusive-OR microoperation with the contents of two registers RI and R2 is
symbolized by the statement

➢ It specifies a logic microoperation to be executed on the individual bits of the registers provided
that the control variable P = 1.

List of Logic Microoperations:

➢ There are 16 different logic operations that can be performed with two binary variables.
➢ They can be determined from all possible truth tables obtained with two binary variables as
shown in Table 4-5.

➢ The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first
column of Table 4-6.
➢ The 16 logic microoperations are derived from these functions by replacing variable x by the
binary content of register A and variable y by the binary content of register B.
➢ The logic micro-operations listed in the second column represent a relationship between the
binary content of two registers A and B.
Hardware Implementation:

➢ The hardware implementation of logic microoperations requires that logic gates be inserted for
each bit or pair of bits in the registers to perform the required logic function.
➢ Although there are 16 logic microoperations, most computers use only four--AND, OR, XOR
(exclusive-OR), and complement from which all others can be derived.
➢ Figure 4-10 shows one stage of a circuit that generates the four basic logic microoperations.
➢ It consists of four gates and a multiplexer. Each of the four logic operations is generated through a
gate that performs the required logic.
➢ The outputs of the gates are applied to the data inputs of the multiplexer. The two selection
inputs S1 and S0 choose one of the data inputs of the multiplexer and direct its value to the output.
Some Applications:

➢ Logic micro-operations are very useful for manipulating individual bits or a portion of a word stored in a
register.
➢ They can be used to change bit values, delete a group of bits or insert new bits values into a register.
➢ The following example shows how the bits of one register (designated by A) are manipulated by logic
microoperations as a function of the bits of another register (designated by B).
➢ Selective set
✓The selective-set operation sets to 1 the bits in register A where there are corresponding
l's in register B. It does not affect bit positions that have 0's in B. The following numerical
example clarifies this operation:

✓ The OR microoperation can be used to selectively set bits of a register.

➢ Selective complement
✓ The selective-complement operation complements bits in A where there are corresponding
1's in B. It does not affect bit positions that have 0's in B. For example:

✓ The exclusive-OR microoperation can be used to selectively complement bits of a register.

➢ Selective clear
✓ The selective-clear operation clears to 0 the bits in A only where there are
corresponding l's in B. For example:

✓ The corresponding logic microoperation is

➢ Mask
✓ The mask operation is similar to the selective-clear operation except that the bits of A are cleared
only where there are corresponding O's in B . The mask operation is an AND micro operation as
seen from the following numerical example:

➢ Insert
✓ The insert operation inserts a new value into a group of bits. This is done by first masking the bits
and then ORing them with the required value.
 ✓ For example, suppose that an A register contains eight bits, 0110 1010. To replace the four leftmost
bits by the value 1001 we first mask the four unwanted bits:

✓ The mask operation is an AND microoperation and the insert operation is an OR

microoperation.

➢ Clear
✓ The clear operation compares the words in A and B and produces an all 0's result if the two
numbers are equal. This operation is achieved by an exclusive-OR microoperation as shown
by the following example

Shift Microoperations:
➢ Shift microoperations are used for serial transfer of data.
➢ The contents of a register can be shifted to the left or the right.
➢ During a shift-left operation the serial input transfers a bit into the rightmost position.
➢ During a shift-right operation the serial input transfers a bit into the leftmost position.
➢ There are three types of shifts: logical, circular, and arithmetic.
➢ The symbolic notation for the shift microoperations is shown in Table 4-7.

➢ Logical Shift:
o A logical shift is one that transfers 0 through the serial input.
o The symbols shl and shr for logical shift-left and shift-right microoperations.
 o The microoperations that specify a 1-bit shift to the left of the content of register R and a
1-bit shift to the right of the content of register R shown in table 4.7.
o The bit transferred to the end position through the serial input is assumed to be 0 during
a logical shift.

➢ Circular Shift:
o The circular shift (also known as a rotate operation) circulates the bits of the register
around the two ends without loss of information.
o This is accomplished by connecting the serial output of the shift register to its serial input.
o We will use the symbols cil and cir for the circular shift left and right, respectively.
➢ Arithmetic Shift:
o An arithmetic shift is a microoperation that shifts a signed binary number to the left or
right.
o An arithmetic shift-left multiplies a signed binary number by 2.
o An arithmetic shift-right divides the number by 2.
o Arithmetic shifts must leave the sign bit unchanged because the sign of the number
remains the same when it is multiplied or divided by 2.

Hardware Implementation:

➢ A combinational circuit shifter can be constructed with multiplexers as shown in Fig. 4-12.
➢ The 4-bit shifter has four data inputs, A0 through A3, and four data outputs, H0 through H3.
➢ There are two serial inputs, one for shift left (IL) and the other for shift right (IR).
➢ When the selection input S=0 the input data are shifted right (down in the diagram).
➢ When S = 1, the input data are shifted left (up in the diagram).
➢ The function table in Fig. 4-12 shows which input goes to each output after the shift.
➢ A shifter with n data inputs and outputs requires n multiplexers.
➢ The two serial inputs can be controlled by another multiplexer to provide the three possible types
of shifts.
Arithmetic Logic Shift Unit:

➢ Instead of having individual registers performing the microoperations directly, computer systems
employ a number of storage registers connected to a common operational unit called an
arithmetic logic unit, abbreviated ALU.
➢ The ALU is a combinational circuit so that the entire register transfer operation from the
source registers through the ALU and into the destination register can be performed during one
clock pulse period.
➢ The shift microoperations are often performed in a separate unit, but sometimes the shift unit is
made part of the overall ALU.
➢ The arithmetic, logic, and shift circuits introduced in previous sections can be combined into one
ALU with common selection variables. One stage of an arithmetic logic shift unit is shown in Fig. 4-
13.
➢ Particular microoperation is selected with inputs S1 and S0. A 4 x 1 multiplexer at the output
chooses between an arithmetic output in Di and a logic output in Ei.
➢ The data in the multiplexer are selected with inputs S3 and S2. The other two data inputs to the
multiplexer receive inputs Ai-1 for the shift-right operation and Ai+1 for the shift-left operation.
➢ The circuit whose one stage is specified in Fig. 4-13 provides eight arithmetic operation, four logic
operations, and two shift operations.
➢ Each operation is selected with the five variables S3, S2, S1, S0 and Cin.
➢ The input carry Cin is used for selecting an arithmetic operation only.
 ➢ Table 4-8 lists the 14 operations of the ALU. The first eight are arithmetic operations
and areselected with S3S2 = 00.
➢ The next four are logic and are selected with S3S2 = 01.
➢ The input carry has no effect during the logic operations and is marked with don't-care x’s.
➢ The last two operations are shift operations and are selected with S3S2= 10 and 11.

0 CHARAN’S DEGREE COLLEGE

 ➢ The other three selection inputs have no effect on the shift.

INPUT-OUTPUT

Peripheral Devices:
The Input / output organization of computer depends upon the size of computer and the
peripherals connected to it. The I/O Subsystem of the computer, provides an efficient
mode of communication between the central system and the outside environment

The most common input output devices are:

i) Monitor

ii) Keyboard

iii) Mouse

iv) Printer

v) Magnetic tapes

The devices that are under the direct control of the computer are said to be
connected online.

Input - Output Interface

1 CHARAN’S DEGREE COLLEGE
 Input Output Interface provides a method for transferring information between
internal storage and external I/O devices.

Peripherals connected to a computer need special communication links for interfacing

them with the central processing unit.

The purpose of communication link is to resolve the differences that exist between
the central computer and each peripheral.

The Major Differences are:-

1. Peripherals are electromechnical and electromagnetic devices and CPU and

memory are electronic devices. Therefore, a conversion of signal values may be
needed.

2. The data transfer rate of peripherals is usually slower than the transfer rate of
CPU and consequently, a synchronization mechanism may be needed.

3. Data codes and formats in the peripherals differ from the word format in the CPU
and memory.

2 CHARAN’S DEGREE COLLEGE

 4. The operating modes of peripherals are different from each other and must be
controlled so as not to disturb the operation of other peripherals connected to
the CPU.

To Resolve these differences, computer systems include special hardware components

between the CPU and Peripherals to supervises and synchronizes all input and out
transfers

◼ These components are called Interface Units because they interface between
the processor bus and the peripheral devices.

I/O BUS and Interface Module

It defines the typical link between the processor and several peripherals.

The I/O Bus consists of data lines, address lines and control lines.

The I/O bus from the processor is attached to all peripherals

interface.

To communicate with a particular device, the processor places a device address on

address lines.

Each Interface decodes the address and control received from the I/O bus, interprets them
for peripherals and provides signals for the peripheral controller.

It is also synchronizes the data flow and supervises the transfer between peripheral and
processor.

Each peripheral has its own controller.

For example, the printer controller controls the paper motion, the print timing

The control lines are referred as I/O command. The commands are as following:

Control command- A control command is issued to activate the peripheral and to inform
it what to do.

Status command- A status command is used to test various status conditions in the
interface and the peripheral.

Data Output command- A data output command causes the interface to respond
by transferring data from the bus into one of its registers.

Data Input command- The data input command is the opposite of the data output.

In this case the interface receives on item of data from the peripheral and places it in
3 CHARAN’S DEGREE COLLEGE
its buffer register. I/O Versus Memory Bus

4 CHARAN’S DEGREE COLLEGE

 To communicate with I/O, the processor must communicate with the memory unit. Like the
I/O bus, the memory bus contains data, address and read/write control lines. There are 3
ways that computer buses can be used to communicate with memory and I/O:

i. Use two Separate buses , one for memory and other for I/O.

ii. Use one common bus for both memory and I/O but separate control lines for each.

iii. Use one common bus for memory and I/O with common control

lines. I/O Processor

In the first method, the computer has independent sets of data, address and control
buses one for accessing memory and other for I/O. This is done in computers that
provides a separate I/O processor (IOP). The purpose of IOP is to provide an independent
pathway for the transfer of information between external device and internal memory.

Asynchronous Data Transfer :

This Scheme is used when speed of I/O devices do not match with microprocessor, and
timing characteristics of I/O devices is not predictable. In this method, process initiates the
device and check its status. As a result, CPU has to wait till I/O device is ready to transfer
data. When device is ready CPU issues instruction for I/O transfer. In this method two types
of techniques are used based on signals before data transfer.

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 i. Strobe Control

ii. Handshaking

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 Strobe Signal :

The strobe control method of Asynchronous data transfer employs a single control line to
time each transfer. The strobe may be activated by either the source or the destination
unit.

Data Transfer Initiated by Source Unit:

In the block diagram fig. (a), the data bus carries the binary information from source to
destination unit. Typically, the bus has multiple lines to transfer an entire byte or word.
The strobe is a single line that informs the destination unit when a valid data word is
available.

The timing diagram fig. (b) the source unit first places the data on the data
bus. The information on the data bus and strobe signal remain in the active state to allow
the destination unit to receive the data.

Data Transfer Initiated by Destination Unit:

In this method, the destination unit activates the strobe pulse, to informing the source
to provide the data. The source will respond by placing the requested binary information
on the data bus.

The data must be valid and remain in the bus long enough for the
destination unit to accept it. When accepted the destination unit then disables the strobe
and the source unit removes the data from the bus.

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 Disadvantage of Strobe Signal :

The disadvantage of the strobe method is that, the source unit initiates the transfer has no
way of knowing whether the destination unit has actually received the data item that was
places in the bus. Similarly, a destination unit that initiates the transfer has no way of
knowing whether the source unit has actually placed the data on bus. The Handshaking
method solves this problem.

Handshaking:

The handshaking method solves the problem of strobe method by introducing a

second control signal that provides a reply to the unit that initiates the transfer.

Principle of Handshaking:

The basic principle of the two-wire handshaking method of data transfer is as follow:

One control line is in the same direction as the data flows in the bus from the source to
destination. It is used by source unit to inform the destination unit whether there a valid
data in the bus. The other control line is in the other direction from the destination to the
source. It is used by the destination unit to inform the source whether it can accept the
data. The sequence of control during the transfer depends on the unit that initiates the
transfer.

Source Initiated Transfer using Handshaking:

The sequence of events shows four possible states that the system can be at any given time.
The source unit initiates the transfer by placing the data on the bus and enabling its data
valid signal. The data accepted signal is activated by the destination unit after it accepts the
data from the bus. The source unit then disables its data accepted signal and the system
goes into its initial state.

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Destination Initiated Transfer Using Handshaking:

The name of the signal generated by the destination unit has been changed to ready for
data to reflects its new meaning. The source unit in this case does not place data on the
bus until after it receives the ready for data signal from the destination unit. From there
on, the handshaking procedure follows the same pattern as in the source initiated case.

The only difference between the Source Initiated and the Destination Initiated transfer is
in their choice of Initial sate.

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Advantage of the Handshaking method:

➢ The Handshaking scheme provides degree of flexibility and reliability because

the successful completion of data transfer relies on active participation by both
units.

➢ If any of one unit is faulty, the data transfer will not be completed. Such an error can
be detected by means of a Timeout mechanism which provides an alarm if the data
is not completed within time.

Asynchronous Serial Transmission:

The transfer of data between two units is serial or parallel. In parallel data transmission, n
bit in the message must be transmitted through n separate conductor path. In serial
transmission, each bit in the message is sent in sequence one at a time.

Parallel transmission is faster but it requires many wires. It is used for short distances
and where speed is important. Serial transmission is slower but is less expensive.

In Asynchronous serial transfer, each bit of message is sent a sequence at a time, and
binary information is transferred only when it is available. When there is no information to
be transferred, line remains idle.

In this technique each character consists of three points :

i. Start bit

ii. Character bit

iii. Stop bit

i. Start Bit- First bit, called start bit is always zero and used to indicate the beginning
character.

ii. Stop Bit- Last bit, called stop bit is always one and used to indicate end of
characters. Stop bit is always in the 1- state and frame the end of the characters
to signify the idle or wait state.

iii. Character Bit- Bits in between the start bit and the stop bit are known as
character bits. The character bits always follow the start bit.

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 Serial Transmission of Asynchronous is done by two ways:

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 a) Asynchronous Communication Interface

b) First In First out Buffer

Asynchronous Communication Interface:

It works as both a receiver and a transmitter. Its operation is initialized by CPU by sending
a byte to the control register.

The transmitter register accepts a data byte from CPU through the data bus and
transferred to a shift register for serial transmission.

The receive portion receives information into another shift register, and when
a complete data byte is received it is transferred to receiver register.

CPU can select the receiver register to read the byte through the data bus. Data in
the status register is used for input and output flags.

First In First Out Buffer (FIFO):

A First In First Out (FIFO) Buffer is a memory unit that stores information in such a manner
that the first item is in the item first out. A FIFO buffer comes with separate input and
output terminals. The important feature of this buffer is that it can input data and output
data at two different rates.

When placed between two units, the FIFO can accept data from the source unit at one
rate, rate of transfer and deliver the data to the destination unit at another rate.

If the source is faster than the destination, the FIFO is useful for source data arrive in
bursts that fills out the buffer. FIFO is useful in some applications when data are
transferred asynchronously.

Modes of Data Transfer :

Transfer of data is required between CPU and peripherals or memory or sometimes
between any two devices or units of your computer system. To transfer a data from one
unit to another one should be sure that both units have proper connection and at the time
of data transfer the receiving unit is not busy. This data transfer with the computer is
Internal Operation.

All the internal operations in a digital system are synchronized by means of clock
pulses supplied by a common clock pulse Generator. The data transfer can be

i. Synchronous or

ii. Asynchronous

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When both the transmitting and receiving units use same clock pulse then such a data
transfer is called Synchronous process. On the other hand, if the there is not concept of
clock pulses

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and the sender operates at different moment than the receiver then such a data
transfer is called Asynchronous data transfer.

The data transfer can be handled by various modes. some of the modes use CPU as an
intermediate path, others transfer the data directly to and from the memory unit and this
can be handled by 3 following ways:

i. Programmed I/O

ii. Interrupt-Initiated I/O

iii. Direct Memory Access (DMA)

Programmed I/O Mode:

In this mode of data transfer the operations are the results in I/O instructions which is
a part of computer program. Each data transfer is initiated by a instruction in the
program. Normally the transfer is from a CPU register to peripheral device or vice-versa.

Once the data is initiated the CPU starts monitoring the interface to see when next
transfer can made. The instructions of the program keep close tabs on everything that
takes place in the interface unit and the I/O devices.

 The transfer of data requires three instructions:

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10 CHARAN’S DEGREE COLLEGE
 In this technique CPU is responsible for executing data from the memory for
output and storing data in memory for executing of Programmed I/O as shown in
Flowchart-:

Drawback of the Programmed I/O :

The main drawback of the Program Initiated I/O was that the CPU has to monitor the units
all the times when the program is executing. Thus the CPU stays in a program loop until the
I/O unit indicates that it is ready for data transfer. This is a time consuming process and the
CPU time is wasted a lot in keeping an eye to the executing of program.

To remove this problem an Interrupt facility and special commands are used.

Interrupt-Initiated I/O :

In this method an interrupt facility an interrupt command is used to inform the device about
the start and end of transfer. In the meantime the CPU executes other program. When the
interface determines that the device is ready for data transfer it generates an Interrupt
Request and sends it to the computer.

When the CPU receives such an signal, it temporarily stops the execution of the program and
branches to a service program to process the I/O transfer and after completing it returns

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back to task, what it was originally performing.

 In this type of IO, computer does not check the flag. It continue to perform its task.

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  Whenever any device wants the attention, it sends the interrupt signal to the CPU.

 CPU then deviates from what it was doing, store the return address from PC
and branch to the address of the subroutine.

 There are two ways of choosing the branch address:

 Vectored Interrupt

 Non-vectored Interrupt

 In vectored interrupt the source that interrupt the CPU provides the
branch information. This information is called interrupt vectored.

 In non-vectored interrupt, the branch address is assigned to the fixed address in

the memory.

Priority Interrupt:

 There are number of IO devices attached to the computer.

 They are all capable of generating the interrupt.

 When the interrupt is generated from more than one device, priority interrupt
system is used to determine which device is to be serviced first.

 Devices with high speed transfer are given higher priority and slow devices are
given lower priority.

 Establishing the priority can be done in two ways:

 Using Software

 Using Hardware

 A pooling procedure is used to identify highest priority in software means.

Polling Procedure :

 There is one common branch address for all interrupts.

 Branch address contain the code that polls the interrupt sources in sequence.
The highest priority is tested first.

 The particular service routine of the highest priority device is served.

 The disadvantage is that time required to poll them can exceed the time to serve
them in large number of IO devices.

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Using Hardware:

 Hardware priority system function as an overall manager.

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  It accepts interrupt request and determine the priorities.

 To speed up the operation each interrupting devices has its own interrupt vector.

 No polling is required, all decision are established by hardware priority interrupt unit.

 It can be established by serial or parallel connection of interrupt lines.

Serial or Daisy Chaining Priority:

 Device with highest priority is placed first.

 Device that wants the attention send the interrupt request to the CPU.

 CPU then sends the INTACK signal which is applied to PI(priority in) of the first
device.

 If it had requested the attention, it place its VAD(vector address) on the bus. And
it block the signal by placing 0 in PO(priority out)

 If not it pass the signal to next device through PO(priority out) by placing 1.

 This process is continued until appropriate device is found.

 The device whose PI is 1 and PO is 0 is the device that send the interrupt request.

Parallel Priority Interrupt :

 It consist of interrupt register whose bits are set separately by the interrupting devices.

 Priority is established according to the position of the bits in the register.

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  Mask register is used to provide facility for the higher priority devices to
interrupt when lower priority device is being serviced or disable all lower
priority devices when higher is being serviced.

 Corresponding interrupt bit and mask bit are ANDed and applied to priority encoder.

 Priority encoder generates two bits of vector address.

 Another output from it sets IST(interrupt status flip flop).

The Execution process of Interrupt–Initiated I/O is represented in the flowchart:

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 Direct Memory Access (DMA):

In the Direct Memory Access (DMA) the interface transfer the data into and out of the
memory unit through the memory bus. The transfer of data between a fast storage device
such as magnetic disk and memory is often limited by the speed of the CPU. Removing the
CPU from the path and letting the peripheral device manage the memory buses directly
would improve the speed of transfer. This transfer technique is called Direct Memory Access
(DMA).

During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA
Controller takes over the buses to manage the transfer directly between the I/O device
and memory.

The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals such as:

◼ Bus Request (BR)

◼ Bus Grant (BG)

These two control signals in the CPU that facilitates the DMA transfer. The Bus Request

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(BR) input is used by the DMA controller to request the CPU. When this input is active, the
CPU terminates the execution of the current instruction and places the address bus, data
bus

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and read write lines into a high Impedance state. High Impedance state means that the
output is disconnected.

The CPU activates the Bus Grant (BG) output to inform the external DMA that the Bus
Request (BR) can now take control of the buses to conduct memory transfer without
processor.

When the DMA terminates the transfer, it disables the Bus Request (BR) line. The CPU
disables the Bus Grant (BG), takes control of the buses and return to its normal
operation.

The transfer can be made in several ways that are:

i. DMA Burst

ii. Cycle Stealing

i) DMA Burst :- In DMA Burst transfer, a block sequence consisting of a number of

memory words is transferred in continuous burst while the DMA controller is
master of the memory buses.

ii) Cycle Stealing :- Cycle stealing allows the DMA controller to transfer one data word
at a time, after which it must returns control of the buses to the CPU.

DMA Controller:

The DMA controller needs the usual circuits of an interface to communicate with
the CPU and I/O device. The DMA controller has three registers:

i. Address Register

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 ii. Word Count Register

iii. Control Register

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 i. Address Register :- Address Register contains an address to specify the
desired location in memory.

ii. Word Count Register :- WC holds the number of words to be transferred. The
register is incre/decre by one after each word transfer and internally tested for
zero.

i. Control Register :- Control Register specifies the mode of transfer

The unit communicates with the CPU via the data bus and control lines. The
registers in the DMA are selected by the CPU through the address bus by enabling
the DS (DMA select) and RS (Register select) inputs. The RD (read) and WR (write)
inputs are bidirectional.
When the BG (Bus Grant) input is 0, the CPU can communicate
with the DMA registers through the data bus to read from or write to the DMA
registers. When BG =1, the DMA can communicate directly with the memory by
specifying an address in the address bus and activating the RD or WR control.

DMA Transfer:

The CPU communicates with the DMA through the address and data buses as with
any interface unit. The DMA has its own address, which activates the DS and RS
lines. The CPU initializes the DMA through the data bus. Once the DMA receives the
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 start control command, it can transfer between the peripheral and the memory.

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 When BG = 0 the RD and WR are input lines allowing the CPU to
communicate with the internal DMA registers. When BG=1, the RD and WR are
output lines from the DMA controller to the random access memory to specify
the read or write operation of data.
Summary :
◼ Interface is the point where a connection is made between two different parts
of a system.
◼ The strobe control method of Asynchronous data transfer employs a single
control line to time each transfer.
◼ The handshaking method solves the problem of strobe method by introducing
a second control signal that provides a reply to the unit that initiates the
transfer.
◼ Programmed I/O mode of data transfer the operations are the results in
I/O instructions which is a part of computer program.
◼ In the Interrupt Initiated I/O method an interrupt facility an interrupt command is
used to inform the device about the start and end of transfer.
◼ In the Direct Memory Access (DMA) the interface transfer the data into and out of
the memory unit through the memory bus.

Input-Output Processor:

 It is a processor with direct memory access capability that communicates with

IO devices.

 IOP is similar to CPU except that it is designed to handle the details of IO operation.

 Unlike DMA which is initialized by CPU, IOP can fetch and execute its own
instructions.

 IOP instruction are specially designed to handle IO operation.

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24 CHARAN’S DEGREE COLLEGE
  Memory occupies the central position and can communicate with each processor by
DMA.

 CPU is responsible for processing data.

 IOP provides the path for transfer of data between various peripheral devices and
memory.

 Data formats of peripherals differ from CPU and memory. IOP maintain such
problems.

 Data are transfer from IOP to memory by stealing one memory cycle.

 Instructions that are read from memory by IOP are called commands to distinguish
them from instructions that are read by the CPU.

Instruction that are read from memory by an IOP

» Distinguish from instructions that are read by the CPU

» Commands are prepared by experienced programmers and are

stored in memory

» Command word = IOP program

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