DIGTAL LOGIC & COMPUTER

ORGANIZATION
DL&CO(23IT01)
 COURSE OUTCOME

Co1 Evaluate Digital Number Systems And Use Boolean Algebra

Theorems, Properties And Canonical Forms For Digital Logic
Circuit Design.
Co2 Design Sequential Logic Circuits And Understand Basic Functional
Blocks A Computer System
Co3 Understand Computer Architecture And Data Representation To
Perform Computer Arithmetic Operations And Processor
Organization.
Co4 Analyze The Memory Hierarchy In A Computer System.
Co5 Understand The I/O Operations And The Interfaces.
Textbooks:
1. Computer Organization, Carl Hamacher, Zvonko Vranesic,
SafwatZaky, 6th edition, Mc Graw Hill
2. Digital Design, 6 th Edition, M. Morris Mano, Pearson
Education. 3. Computer Organization and Architecture, William
Stallings,11th Edition, Pearson.
Reference Books:
2. Computer Systems Architecture, M. Moris Mano, 3 rd Edition,
Pearson
3. Computer Organization and Design, David A. Paterson, John
L. Hennessy, Elsevier
3. Fundamentals of Logic Design, Roth, 5 th Edition, Thomso
 UNIT-1

Data Representation: Binary Numbers, Fixed Point

Representation. Floating Point Representation. Number base
conversions, Octal and Hexadecimal Numbers, components, Signed
binary numbers, Binary codes
Digital Logic Circuits-I: Basic Logic Functions, Logic gates,
universal logic gates, Minimization of Logic expressions. K-Map
Simplification, Combinational Circuits, Decoders, Multiplexers
DATA RPRESENTATION:

 Data representation in computer organization refers to how data is stored,

processed and transmitted.

 Digital computers store and process information in binary form as digital

logic has only two values “1” & “0” (T/F), (ON/OFF).

 Binary information in digital computers is stored in memory or processor

registers. Registers can contain either data or control information.

 Control information is a bit or group of bits used to specify the sequence of

command signals needed for manipulation of the data in other registers.
 Information

Instructions Data

Non- Single
Numerical Numerical precision

Fixed point Floating point

representation representation
Double
precision
Unsigned Signed
representation representation

Only Signed
magnitude 1’s com 2’s com
(+ve)
Number system:
For representing the values in digital systems
we use these number systems.

4 Types:
1: BINARY NUMBER SYSTEM,
2: OCTAL NUMBER SYSTEM,
3:DECIMAL NUMBER SYSTEM,
4:HEXA DECIMAL NUMBER SYSTEM.
Binary number system:
1. Binary number system is a positional weighted system.
2. The ‘base’ or ‘radix’ of this number system is “2”.
3. This num system has two independent symbols that are “0” & “1”.
4. The binary digit is called a “Bit”.
5. The binary point separates the “integer part” and the “fractional part”.
6. Each digit (bit) carries a weight based on its position relative to the binary point.
7. The binary num system is used in digital computers because the switching circuits used in
these computers use two devices such as “transistors” and “diodes” etc….
8. A transistor or the switch or the diode can be “ON/OFF”.
9. These diodes have to be exists in one of the two possible states. So these states can be
represented by the symbols ‘’0” & “1”.
REPRESENTATON OF NUMBERS – POSITIONAL NUMBERS
BINARY DECIMAL OCTAL HEXA
DECIMAL
0000 00 00 0
0001 01 01 1
0010 02 02 2
0011 03 03 3
0100 04 04 4
0101 05 05 5
0110 06 06 6
0111 07 07 7
1000 08 10 8
1001 09 11 9
1010 10 12 A
1011 11 13 B
1100 12 14 C
1101 13 15 D
1110 14 16 E
1111 15 17 F
NUMBER BASE CONVERSION:
if we want to convert decimal number system to any number
system(octal, binary, hexadecimal) use division methods
Any number system (octal, binary, hexadecimal) to decimal number
system use multiplication number
3 TYPES:
1. Decimal to non-decimal
2. Any non-decimal to decimal
3. Any base to any base

1.Decimal to non-decimal:

successive division of integer part

2 cases
successive multiplication of fractional part
Case-1:- successive division of integer part
1.Divide the number with base.
2.Divide the quotient obtained in step-1 respectively until the quotient is zero
3.collect the remainders from downloads to upwards.

ex:- 1. (34) - ( )
10 2

2. (48) - ( )
10 2
Case-2:- successive multiplication of the fractional part
1. successively multiply the fractional part with the required base to get result.
2.take the fractional part of the result obtained from step-1 and perform
multiplication until the fractional part becomes zero .

ex:- decimal to binary conversion

1) (0.8125) = ( )
10 2
Ans:-
0.8125 * 2
= 1.625
again multiply the fractional part with the base
= 0.625 * 2 = 1.25
= 0.25 * 2 = 0.5
= 0.5 * 2 = 1.0
(0.8125) = (1101)
10 2
2) Decimal to octal number
ex:- (34) = ( )
10 8

3) Decimal to hexadecimal
Ex:- (34) =( )
10 16

--- If both integer and fractional part is present then

Ex:- (24.8) =( )
10 2

successive division successive multiplication

Any non-decimal to decimal base:

1)B----D
2)HD--D
3)O---D

Other base system to decimals:

step-1: Determine the column value of each digit

step-2: Multiply the obtained column values(in step-1) by the digits in the corresponding
columns
step-3: Sum the products calculated in (step-2)
step-4: The sum total is equivalent value in decimal
EX:-
1) B -- D
(1101.1) =( )
2 10

3 2 1 0 -1
Ans: 1*2 + 1*2 + 0*2 + 1*2 + 1*2

= 8+4+0+1+1 / 2
= 13+1/2
= 13+0.5
= (13.5)
10

Conversion from octal to decimal: conversion of hexadecimal to

decimal:

2) (475.25) = ( ) 2) (21) = ( )
8 10 16 10
Any base to any base:
1) convert any base to decimal
2)convert decimal to required base

Ex:-

a) (25) = ( )
8 2

1 0
ANS:) 2 * 8 + 5 * 8
= 16+5
= (21)
10

now convert to the binary form by doing (Lcm)

with the base “2”.
b) Binary to hexadecimal:

(0100) = ( )
2 16

c) Hexadecimal to decimal:

(D A D) = ( )
16 8
Shortcut methods:

1) Binary to octal:

Group the given binary numbers into 3-bits starting from LSB

EX:- (1 0 1 0 1) = ( )
2 8

2) Octal to binary:

( 3 5 7) = ( )
8 2
3) Binary to hexadecimal:

Group the given binary number into 4 digits

Replace the 4 digit binary code by its hexadecimal digit

(10101) = ( )
2 16
Practice examples:
Decimal to any other number:
1) decimal --- Binary

Ex:- a) (27) = ( ) b) (27.315) = ( )

10 2 10 2

Decimal to octal:

Ex:- a) (275) = ( ) b) (275.4) = ( )

10 8 10 8

Decimal to Hexadecimal:

EX:- a) (382) =( ) b) (382.525) = ( )

10 16 10 16
Binary to any base:
Binary to decimal:

a) ( 1 1 0 1 0 ) = ( ) b) ( 1 1 0 1 0 . 1 1) = ( )
2 10 2 10

Binary to octal:
a) (1 1 1 0 1 1) = ( ) b) ( 1 1 1 0 1 1 . 0 1) = ( )
2 8 2 8

Binary to hexadecimal:
b) ( 0 0 1 1 1 1 1 1 0 0 1 ) = ( ) b) ( 0 0 1 1 1 1 1 0 0 1 1 . 0 1 1 ) = ( )
2 16 2 16
Octal to any base:
1)Octal to binary:

EX:- a) ( 5 7 ) = ( ) b) ( 7 2 . 4 5 ) = ( )
8 2 8 2

2)Octal to decimal:

a) ( 1 2 7 ) = ( ) b) ( 2 6 . 2 4 ) = ( )
8 10 8 10

3)Octal to hexadecimal:

( 1 2 6 7 .3 4 ) = ( )
8 16
Hexadecimal to any base:

1) Hexadecimal to binary:

a) ( B 6 5 F ) = ( ) b) (D A B . C ) = ()
16 2 16 2

2)Hexadecimal to octal:

( FAC E ) = ( )
16 8
 Fixed point
representation

Unsigned Signed
representation representation

Signed 1’s
(+ ve) magnitude
2’s com
values comp
Complement of number system:
1) For finding the subtraction of a number base system the complements are used

2) We can also say complements are used in digital computers to simplify the subtraction operation and
for logical manipulation.

3)Simplifying operations leads to simpler, less expensive circuits to implement the operations

There are 2 types of complements : n

Formula= (r -
N)
1) Radix complement (or) r’s complement
n
Formula=(r - 1) - N
2) Diminished Radix complement (or) (r-1)’s complement

Where
Let ‘N’ be the number
‘r’ be the base/radix
‘n’ is the number of digits
 2’s complement (r)
Binary, r=2
1‘s complement (r-1)

8‘s com
Octal, r=8
7’s com

10’s com
Decimal, r=10
9’s com

16’s com
Hexadecimal r=16
15’s com
(r-1)’s complement for Decimal system:

r = 10
(r – 1 )’s 9’s complement.
n
(r – 1) – N
n
(10 - 1) – N

2
n=2 (10 - 1)= 99

3
n=3 ( 10 - 1 )=999

subtracting each digit of N from 9 digit

1) Signed magnitude representation:

b b -------------------- 1 0
( sign n-2 n-1
bit)
MSB LSB

magnitude ( n-1 )

it is in the form of both (+ve) signed magnitude ( 0 --- +ve)

and (-ve) 1’s complment (1 ----- -ve)

(0 1)

(1 0)
The representation of sign magnitude,1’s com , 2’s com in binary form

range = (-7 to +7)

-n - 1 n -1
-2 - 1 to 2
- 1

1) -5

2) +4

-4
1)Find 9’s and 10’s complement of (432)
10
The given number is subtracted from the 999
because it is a 9’s complement and the number of digits are (3)

9’s com ------ 9 9 9

432
----------
567
----------

n
By using the formula: (r - 1 ) – N

3
= (10 - 1 ) – 4 3 2
= (1000 – 1 – 4 3 2
= 999–432
= 567
10’s complement:
9’s comp + 1
567+1
= 568
n
by using the formula: (r - N)
3
= (10 - 432)

= 1000 - 432

= 568
Find 1’s and 2’s complement of (1 0 1 0 1 0 )
2

1’s comp ---- 101010

IN 1’S COMPLEMENT ‘0’ BECOMES ‘1’

‘1’ BECOMES ‘0’

101010
010101

2’S Complement--- 1’s comp + 1

010101
+1
1
-------------------
010110
--------------------
TABLE FOR THE BINARY FORM;

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
1)Find 7’s comp & 8’s comp of ( 4 6 1 )
8

2)Find 15’s & 16’s comp of ( 4 B 9 )

16

2 Ans:) 15’s comp -------- 15 15 15

4 B 9
11
……………
9 4 6
……………
16’s comp----- 15’s com +1
9 4 6
+ 1
………….
9 4 7
..………..
Find 91 of 1’s and 2’s complement ?
Step 1: Convert 91 to binary

To find the 1's and 2's complement, we first need to represent 91 in binary.
the binary representation of 91 is

(1011011).

Step 2: Find the 1's complement

The 1's complement of a binary number is obtained by flipping every bit (changing 1 to 0 and 0 to
1).

1's complement of 91 (1011011)

( 0100100).
Step 3:
Find the 2's complement
The 2's complement is obtained by adding 1 to the 1's complement.

0100100
+1
…………..
= 0100101
Unsigned fixed point

1) Represent the fixed point representation of unsigned binary number ( 0 1 1 0 1 1 0)

using 4 integer bits and 3 fractional bits

Ans) 0 1 1 0 1 1 0

divide the part number in 3 parts

1) signed part 2) integer part 3) fractional part

( 0 1 1 0 . 1 1 0) = ( )
2 10

now convert it into decimal form

Ans:) (6.75)
10
Floating point representation: The way of representing a floating point
number in a given computer is called floating point representation.

1) This representation does not reserve a specific number of bits for the integer part or the
fractional part.
2) Instead it reserves a certain number of bits for the number (called the mantissa or
significand) .
3) certain number of bits to say where within that number the decimal place sits (called the
exponent).
4) The fixed point mantissa may be fraction or an integer. Floating -point is always
interpreted to represent a number in the following form:( +/- M*BE )
tion as following diagram.
In floating point number the position of the Decimal or binary point is fluctuating (floating).

Ex:- 1) +1.234 2) -1.0100 3) 3.14

+12.34 -10.100 - 12.5
+ 123.4 -101.00 -10101.101

+/-e
Formula:- +/- M * r
where M - mantissa (it can contain both integer and floating point)
r - base
e - exponent

+e --- (+ve)-- large numbers (Left ------ Right )

-e ---- (-ve)-- small numbers (Left ------ Right)

+4
Ex:- +1000.110 = + 0.1000110 * 2
+6
- 101011 = - 0.101011 * 2
-4
1.2345 = 12345 * 10
-3
215 . 37 = 21537 * 10
Normalization:

The floating point number is said to be normalized when we force the integer part of its
mantissa to be ‘1’ and allow its fractional point to be anything.

ex:- 13.25 = 1101.01

+3
= 1.10101 * 2

Ex:- 1) 436 2) 1.25 3)0.66 4) 0. 1011

IEEE 7 5 4 Standards:

To represent floating point number an organization called as (IEEE)

proposed a standard (7 5 4 ) for representing floating point number

2 types:
1) Single precision ( 32 bits)
2) Double precision ( 64 bits)

According to IEEE 754 standard, the floating-point number is represented in following ways:
Half Precision (16 bit): 1 sign bit, 5 bit exponent, and 10 bit mantissa

Single Precision (32 bit): 1 sign bit, 8 bit exponent, and 23 bit mantissa

Double Precision (64 bit): 1 sign bit, 11 bit exponent, and 52 bit mantissa

Quadruple Precision (128 bit): 1 sign bit, 15 bit exponent, and 112 bit mantissa
Special Value Representation −

There are some special values depended upon different values of the exponent and mantissa
in the IEEE 754 standard.

•All the exponent bits 0 with all mantissa bits 0 represents 0. If sign bit is 0, then +0, else -0.

•All the exponent bits 1 with all mantissa bits 0 represents infinity. If sign bit is 0, then +∞,
else -∞.

•All the exponent bits 0 and mantissa bits non-zero represents denormalized number.

•All the exponent bits 1 and mantissa bits non-zero represents error.
1) Consider a 32 bit register which stores floating point num in IEEE 7 5 4 single precision format. Find
the
decimal values of the following 32 bits?
0 10000011 1100…..0

Ans) step-1:- S=0

step-2:- 10000011
( ) ---bias exponent

true exponent = bias exponent – bias value

n -1
bias value = 2 -1
=( )
step-3 :- mantissa m= 0.1100…..0

s E- Bias
decimal equivalent = ( -1 ) * 1 . M * 2

131 – 127
=( -1) *1. 11* 2
4
Represent + ( 28) in IEEE 7 5 4 single precision format using implicit normalization
10
Ans:) step:- s=0
step:- (28) = ( )
2
4
11100 = 1.1100 *2
E – Bias
= 1. M * 2
M = 0.1100
E – Bias = 4
E= 4 + bias == 4+ 127 = 131
n-1
bias = 2 - 1
8 -1
=2 -1
7
=2 -1
= 128 -1
= 127

=== 4+ 127 = 131

8 7 6 5 4 3 2 1 0
2 2 2 2 2 2 2 2 2 0
 10000011 == 10000011
1 1 1 11000000000
1) Represent (32.75 ) in IEEE 7 5 4 single precision format using implicit normalization
10
2) Represent (- 29 .5 ) in IEEE 7 5 4 single precision format using implicit normalization
10
3) Represent +(116 ) in IEEE 7 5 4 double precision format using implicit normalization
10
4) Represent (- 29 .5 ) in IEEE 7 5 4 double precision format using implicit normalization
10
5)Consider a 64 bit register which stores floating point num in IEEE 7 5 4 double precision
format. Find the decimal values of the following 64 bits?

1 10000000011 1101100…….0
BINARY CODES AND CLASSIFICATION OF BINARY CODES

BINARY CODE:
Binary code is a computer code that uses the binary
number system. The instructions, text, and data are translated into a binary
code. Binary code uses two digits ( 0 & 1 ). This code can easily understand by
computer.
CLASSIFICATION OF BINARY CODE:
NUMERIC CODES:
Numeric codes are the codes which represent numerical information i.e.., only numbers
as a series of 0’s & 1’s.
Numeric code are also used to represent the decimal digits ( 0 – 9 )
ex:- 8421, xs-3, gray, 2421, 5211 codes are numerical cods.

1) Weighted codes:-
weighted codes are the codes , which obey the position- weighting principle. Each
position of the number represents a specific weight.
ex:- 8421, 2421 codes

2) Non- weighted codes:-

Non- weighted codes are the codes which does not obey the position –weighting
principle for each position of the principle for each position of the number. We cannot assign any weights
ex:- excess-3 code, gray code

3) Sequential code:-
In sequential code, each successive code word is one binary number greater than its
preceding code word.
ex:- 8421 code, excess -3 code
4)Self complementing code (or) reflective code)
A code is said to be self- complementing code, if the code word of the 9’s
complement of “N” i.e.. [9-N] can be obtained from the code word of N by interchanging all the 0’s and 1’s
ex:- excess-3, 2421 code
Decimal BCD EXCESS-3 2421
0 0000 0+3(0000+001 0000
1)
1 0001 0100 0001
2 0010 0101 0010
3 0011 0110 0011
4 0100 0111 0100
5 0101 1000 1011
6 0110 1001 1100
7 0111 1010 1101
8 1000 1011 1110
9 1001 1100 1111
Excess-3: 0--- 0011 1’s com of ‘0’- 1100 9’s com of ‘0’ - 9
0
5) Gray code:
1) It is a non-weighted code. It is not suitable for arithmetic operations
2) It is also known as unit distance code.
Rules: 1) MSB will not change
2) Apply the EX-OR operation
A B XOR
0 0 0
0 1 1
1 0 1
1 1 0

Cyclic code:
It is a code in which each successive code word differ from the preceding code word
in only one bit position. It is also called as “unit distance code”

ex:- gray code

2- 0011 4- 0110
3- 0010 5- 0111
Error detection and error correction code:
The binary information is transformed from one location to another through some communication
media
sender receiver
data

Transmission media

The external noise can change bits from ‘1 to 0’s (or) ‘0 to 1’.This change in values are
called “error”
types of errors:
1) single bit error
2) multiple bit error
3) burst error
to overcome this error we use the following codes:
1) error detection ex:- parity a) even parity b) odd parity

2) error correction ex:- Hamming codes

Hamming code:
hamming code is an error detecting code.it is used to detect and correct single bit error in
data transmission. Message can be represented by ‘m”, any number of bits.
sender sends the message along with the parity bits to the receiver.
p
2 >= m + p + 1

m= size of the message.

Ex:- generate hamming code for the given message 1011 with even parity. The message receivevd as
1000101. find out the error and correct it.
Ans:) given data = 1011
num of bits in given data m = 4 p
num of parity bits that can be required to the given msg :- 2 >= m + p + 1
num of parity bits = 3
total num of bits = m + p
4 + 3 7

P1 -------- 1, 3, 5, 7
P2 -------- 2, 3, 6, 7
P3-------- 4, 5, 6, 7
 p3 p2 p1
m4 m3 m2 p3 m1 p2 p1 0 0 0
1 0 1 1 0 0 1
0 1 0
0 1 1
P1- 3, 5, 7
1 0 0
1 1 1 ( there is a odd parity)
p1-1 1 0 1
P2-- 2, 3, 6 , 7 1 1 0
1 0 1 ( two 1’s even parity) 1 1 1
P2- 0

P3--- 4, 5, 6, 7
101
p3- 0

the actual msg : 1 0 1 0 1 0 1

received msg : 1 0 0 0 1 0 1
‘0’ occurred at 5th position
after correcting the error, the received msg is 1 0 1 0 1 0
What is a Combinational Circuit?
A combinational circuit is a type of digital logic circuit whose output depends on the present input values only and does not
depend on past input and output values
Block Diagram of Combinational Circuit
The following figure depicts the block diagram of a combinational logic circuit.

Here, we can see that there are only three key elements in the circuit diagram of a combinational circuit, they are −
•Input Lines − The input lines are used to enter the input values into the combinational circuit.
•Processing Unit − It is the main element that processes the input values depending on the type of the circuit. For
example, a full adder adds three binary bits.
•Output Lines − The output lines are used to take results generated by the circuit.
Consider a four input functions that output a ‘1’ whenever an odd number of its input are ‘0’. C on struct
the truth table and draw the logic diagram .
Decim Input output
al num A B C
D
0 0 0 0 0
0
1 0 0 0 1
1
2 0 0 1 1
0
3 0 0 1 0
1

4 0 1 0 1
0
5 0 1 0 0
1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 1
0
K map for the output ‘0’

1 1
1 1
1 1
1 1

0= A’B’C’D+ A’B’CD’+ A’BC’D’ + A’BCD +ABC’D +ABCD’+ AB’C’D’+ AB’CD

SELECT THE COMMON TERMS
A’B’(C’D+CD’) + A’B(C’D’+CD) + AB(C’D+CD’)+AB’(C’D’+CD)
=A’B’(C’D+CD’)+AB(C’D+CD’)+A’B(C’D’+CD)+AB’(C’D’+CD)
=(C’D+CD’)(A’B’+AB)+( C’D’+CD)(A’B+AB’)
(C ⊕ D)(AʘB)+ (CʘD)(A ⊕B )

0=(C ⊕ D)(AʘB)+ (CʘD)(A ⊕B )

LOGIC DIAGRAM:
Half Adder

A half adder is a digital logic circuit that performs binary addition of two single-bit binary numbers. It has two
inputs, A and B, and two outputs, SUM and CARRY. The SUM output is the least significant bit (LSB) of the result, while the
CARRY output is the most significant bit (MSB) of the result, indicating whether there was a carry-over from the addition of
the two inputs. The half adder can be implemented using basic gates such as XOR and AND gates.

Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit that adds two
numbers and produces a sum bit (s) and carry bit (c) both as output. The addition of 2 bits is done using a combination circuit
called a Half adder. The input variables are augend and addend bits and output variables are sum & carry bits. A and B are the
two input bits.
Application of Half Adder in Digital Logic
•Arithmetic circuits: Half adders are utilized in number-crunching circuits to add double numbers. At the point
when different half adders are associated in a chain, they can add multi-bit double numbers.
•Data handling: Half adders are utilized in information handling applications like computerized signal handling,
information encryption, and blunder adjustment.
•Address unraveling: In memory tending to, half adders are utilized in address deciphering circuits to produce
the location of a particular memory area.
•Encoder and decoder circuits: Half adders are utilized in encoder and decoder circuits for computerized
correspondence frameworks.
•Multiplexers and demultiplexers: Half adders are utilized in multiplexers and demultiplexers to choose and
course information.
•Counters: Half adders are utilized in counters to augment the count by one.
Half Subtractor
Half subtractor is a combination circuit with two inputs and two outputs that are different and borrow. It
produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate
if a 1 has been borrowed. In the subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend bit.

Truth table
implementation
Application of Half Subtractor in Digital Logic:
1.Calculators: Most mini-computers utilize advanced rationale circuits to perform numerical tasks. A Half Subtractor can be
utilized in a number cruncher to deduct two parallel digits from one another.

2.Alarm Frameworks: Many caution frameworks utilize computerized rationale circuits to identify and answer interlopers. A
Half Subtractor can be utilized in these frameworks to look at the upsides of two parallel pieces and trigger a caution in the
event that they are unique.

3.Automotive Frameworks: Numerous advanced vehicles utilize computerized rationale circuits to control different
capabilities, like the motor administration framework, stopping mechanism, and theater setup. A Half Subtractor can be
utilized in these frameworks to perform computations and examinations.

4.Security Frameworks: Advanced rationale circuits are usually utilized in security frameworks to identify and answer
dangers. A Half Subtractor can be utilized in these frameworks to look at two double qualities and trigger a caution in the
event that they are unique.

5.Computer Frameworks: Advanced rationale circuits are utilized broadly in PC frameworks to perform estimations and
examinations. A Half Subtractor can be utilized in a PC framework to deduct two paired values from one another.
Half Subtractor Using NAND Gates
We may implement the logic circuit of half subtractor using NAND gates.

From this logic circuit diagram, we can see that 9 NAND gates are required for realization of the half
subtractor.
 What is a Full Adder?
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as
output is known as a full-adder.
In other words, a combinational circuit which is designed to add three binary digits and produces two outputs (sum and carry) is
known as a full adder. Thus, a full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded
from the previous addition.
The block diagram and circuit diagram of the full adder

Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates and one OR gate, which are connected together

ull Adder Truth Table:

K-Map for Full Adder
K-Map (Karnaugh Map) is a tool for simplifying binary complex Boolean algebraic expressions

Application of Full Adder in Digital Logic:

1.Arithmetic circuits: Full adders are utilized in math circuits to add twofold numbers. At the point when different full
adders are associated in a chain, they can add multi-bit paired numbers.
2.Data handling: Full adders are utilized in information handling applications like advanced signal handling, information
encryption, and mistake rectification.
3.Counters: Full adders are utilized in counters to addition or decrement the count by one.
4.Multiplexers and demultiplexers: Full adders are utilized in multiplexers and demultiplexers to choose and course
information.
5.Memory tending to: Full adders are utilized in memory addressing circuits to produce the location of a particular
memory area.
6.ALUs: Full adders are a fundamental part of Number juggling Rationale Units (ALUs) utilized in chip and computerized
signal processors.
What is a NAND Gate?
A NAND gate is one of the type of Universal Gates in which the two basic logic gates are combined as the NAND gate can
implement any Boolean function without the use of basic gates and also find the results of logical inputs without the use of any
other logic gates.
The NAND gate or “NotAND” gate is the combination of two basic logic gates are connected in series i.e. the AND gate and
the NOT gate. NAND gate output is high when one of the two inputs is high or if both inputs are low. It means the output is
always high and when both the inputs are high then the output is low.
What is a Full-Subtractor?
A full-subtractor is a combinational circuit that has three inputs A, B, bin and two outputs d and b. Where, A is the minuend, B
is subtrahend, bin is borrow Produced by the previous stage, d is the difference output and b is the borrow output.
As we know that the half-subtractor can only be used for subtraction of LSB (least significant bit) of binary numbers. If there is
any borrow during the subtraction of the LSBs of two binary numbers, then it will affect the subtraction of next stages.
Therefore, the subtraction with borrow are performed bya full subtractor.

The block diagram and circuit diagram

4×1 Multiplexer
The 4×1 Multiplexer which is also known as the 4-to-1 multiplexer. It is a multiplexer that has 4 inputs and a single output.
The Output is selected as one of the 4 inputs which is based on the selection inputs. The number of the Selection lines will
depend on the number of the input which is determined by the equation log2nlog2​n ,In 4×1 Mux the selection lines can be
determined as log4=2log4​=2 ,slo two selections are needed.