Summary

Counting in Binary
As you know, the binary count sequence follows a
familiar pattern of 0’s and 1’s as described in
Section 2-2 of the text.
000 LSB changes on every
001 number.
010
The next bit changes
011
on every other number.
100
The next bit changes on
101
every fourth number.
110
111

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Counting in Binary
A counter can form the same pattern of 0’s and 1’s with
logic levels. The first stage in the counter represents the
least significant bit – notice that these waveforms
follow the same pattern as counting in binary.

LSB 0 1 0 1 0 1 0 1 0

0 0 1 1 0 0 1 1 0

MSB 0 0 0 0 1 1 1 1 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Three bit Asynchronous Counter
In an asynchronous counter, the clock is applied only to
the first stage. Subsequent stages derive the clock from
the previous stage.
The three-bit asynchronous counter shown is typical. It uses J-K
flip-flops in the toggle mode.

HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

Waveforms are on the following slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Three bit Asynchronous Counter
Notice that the Q0 output is triggered on the leading edge of
the clock signal. The following stage is triggered from Q0.
The leading edge of Q0 is equivalent to the trailing edge of
Q0. The resulting sequence is that of an 3-bit binary up
counter. 1 2 3 4 5 6 7 8
CLK

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Asynchronous Decade Counter

This counter uses partial decoding to recycle the count

sequence to zero after the 1001 state. The flip-flops are trailing-
edge triggered, so clocks are derived from the Q outputs. Other
truncated sequences can be obtained using a similar technique.
CLR
HIGH
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

Waveforms are on the following slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Asynchronous Decade Counter
When Q1 and Q3 are HIGH together, the counter is
cleared by a “glitch” on the CLR line.
1 2 3 4 5 6 7 8 9 10
CLK
Q0

Q1 Glitch
Glitch

Q2

Q3

CLR
Glitch
Glitch

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 74LS93A Asynchronous Counter
The 74LS93A has one independent toggle J-K flip-flop
driven by CLK A and three toggle J-K flip-flops that form
an asynchronous counter driven by CLK B.
The counter can be extended to form a 4-bit counter by connecting
Q0 to the CLK B input. Two inputs are provided that clear the count.
(1)
CLK B

J0 J1 J2 J3
(14)
CLK A C C C C

K0 K1 K2 K3

(2)
All J and K inputs RO (1)
(3)
are connected RO (2)
(12) (9) (8) (11)
internally HIGH
Q0 Q1 Q2 Q3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counters
In a synchronous counter all flip-flops are clocked
together with a common clock pulse. Synchronous
counters overcome the disadvantage of accumulated
propagation delays, but generally they require more
circuitry to control states changes.
HIGH Q0
This 3-bit binary
Q0Q1
synchronous counter Q0 Q1 Q2
J0 J1 J2
has the same count
sequence as the 3-bit C C C

asynchronous counter K0 K1 K2

shown previously. CLK

The next slide shows how to analyze this counter by writing the logic
equations for each input. Notice the inputs to each flip-flop…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Analysis of Synchronous Counters
A tabular technique for analysis is illustrated for the counter on the
previous slide. Start by setting up the outputs as shown, then write
the logic equation for each input. This has been done for the counter.
1. Put the counter in an 2. Use the new inputs to 3. Set up the next
arbitrary state; then determine determine the next state: Q2 and group of inputs from
the inputs for this state. Q1 will latch and Q0 will toggle. the current output.

Outputs Logic for inputs

Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1

0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0
4. Q2 will latch again but both Q1 and Q0 will toggle.

Continue like this, to complete the table.

The next slide shows the completed table…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Analysis of Synchronous Counters
Outputs Logic for inputs
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1

1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1
0 0 0
At this points all states have been accounted
for and the counter is ready to recycle…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
A 4-bit Synchronous Binary Counter
Q1Q0
G1 Q2Q1Q0
G2
FF0 FF1 FF2 FF3

HIGH J0 Q0 J1 Q1 J2 Q2 J3 Q3

CLK C C C C

K0 Q0 K1 Q1 K2 Q2 K3 Q3

The 4-bit binary counter

has one more AND gate Q0
than the 3-bit counter just
described. The shaded Q1
areas show where the
Q2
AND gate outputs are
HIGH causing the next
Q3
FF to toggle.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counter Design
Most requirements for synchronous counters can be met
with available ICs. In cases where a special sequence is
needed, you can apply a step-by-step design process.
The steps in design are described in detail in the text and lab manual.
Start with the desired sequence and draw a state diagram and next-
state table. The gray code sequence from the text is illustrated:
State diagram: Next state table:
000 Present State Next State
100 001 Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
101 011 0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
111 010 1 1 0 1 1 1
1 1 1 1 0 1
110 1 0 1 1 0 0
1 0 0 0 0 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Inputs Outputs

Summary J

0
K
0
CLK Q
Q0
Q
Q0
Comments
No change
0 1 0 1 RESET
1 0 1 0 SET
Synchronous Counter Design 1 1 Q0 Q0 Toggle

The J-K transition table lists all combinations of present

output (QN) and next output (QN+1) on the left. The inputs
that produce that transition are listed on the right.
Each time a flip-flop is clocked, the Output Flip-Flop
J and K inputs required for that Transitions Inputs
QN Q N+1 J K
transition are mapped onto a K-map.
Q0
0 0 0 X
Q2Q1 0 1 0 1 1 X
An example of 1 0 X 1
00 1 X Q2Q1 1 1 X 0
the J0 map is:
01 0 X

11 1 X Q2Q1 The logic for each input is read

10 0 X and the circuit is constructed.
J0 map The next slide shows the circuit
for the gray code counter…
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Synchronous Counter Design

FF0 FF1 FF2

Q2
J0 J1 J2
Q0 Q1
C C C
Q0 Q1 Q2
K0 K1 K2

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Counter Decoding
Decoding is the detection of a binary number and can be
done with an AND gate.
HIGH

Q2
J0 Q0 J1 Q1 J2 Q2

C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

What number is decoded by

this gate?
Decoded 4
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Counter Decoding

Show how to decode state 5 with an active LOW output.

HIGH

Q0 Q2
J0 Q0 J1 Q1 J2 Q2

C C C

Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

Notice that a NAND gate

was used to give the active
Decoded 5
LOW output.
Q2Q1Q0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Selected Key Terms

Asynchronous Not occurring at the same time.

Modulus The number of unique states through which a
counter will sequence.
Synchronous Occurring at the same time.
Terminal count The final state in a counter’s sequence.
State machine A logic system exhibiting a sequence of states or
values.
Cascade To connect “end-to-end” as when several counters
are connected from the terminal count output of
one to the enable input of the next counter.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved