Date: 7-8-2012

Reg No: 12mvd0031

Experiment No: 1

Exp.No.1 Design and Implementation of Combinational Circuits

Aim:
To design and implement the following combinational circuit.
a. Basic Gates Using Dataflow, Structural Modeling

b. Half-Adder and Full-Adder using structural Modeling

c. Half-Subtractor and Full-Subtractor using dataflow modeling.
d. Decoder and Encoder generators using Dataflow, Structural Modeling.
e. Code Convertor & parity generators using Dataflow, Structural Modeling
f. Multiplexer and De-multiplexer using Dataflow, Structural Modeling

Software Details:
For design Functional Simulation: ModelSim
For design Synthesis: Quartus II
For design Implementation: Quartus II
Hardware Details:
Family: Cyclone II
Device: EP2C
Package: FBGA
Pin count: 484

a.Basic Gates Using Dataflow, Structural Modeling:

AND GATE:
Data Flow Modeling:
module andgate(a,b,y);
input a,b;
output y;
wire y;
assign y=a&b;
endmodule
Structural Modeling:
Module andgate(a,b,y);
input a,b;

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Reg No: 12mvd0031
output y;
wire y;
and(y,a,b);
endmodule

Test Bench for AND gate:

module and_gate_tst();
reg a,b;
wire y;
and_gate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#50;
a=1'b0;
b=1'b1;
#50;
a=1'b1;
b=1'b0;
#50;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of AND gate:

Experiment No: 1

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OR GATE:
Data Flow Modeling:
module orgate(a,b,y);
input a,b;
output y;
wire y;
assign y=a|b;
endmodule
Structural Modeling:
module orgate(a,b,y);
input a,b;
output y;
wire y;
or(y,a,b);
endmodule
Test Bench for OR gate:
module or_gate_tst();
reg a,b;
wire y;

Experiment No: 1

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orgate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#100;
a=1'b0;
b=1'b1;
#100;
a=1'b1;
b=1'b0;
#100;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of OR gate:

Experiment No: 1

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NOT GATE:
Data Flow Modeling
module notgate(a,y);
input a;
output y;
wire y;
assign y=(~a);
endmodule
Structural Modeling:
module notgate(a,y);
input a;
output y;
wire y;
not(y,a);
endmodule
Test Bench for NOT gate:
module notgate_tst();
reg a;
wire y;
notgate a1(a,y);
initial
begin
a=1'b0;
#100;
a=1'b1;
end
endmodule

Experiment No: 1

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Functional Simulation of NOT gate:

XOR GATE:
Data Flow Modeling
module xorgate(a,b,y);
input a,b;
output y;
wire y;
assign y=(a^b);
endmodule
Structural Modeling:
module xorgate(a,b,y);
input a,b;
output y;
wire y;
xor(y,a,b);
endmodule

Experiment No: 1

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Reg No: 12mvd0031

Test Bench for XOR gate:

module xorgate_tst();
reg a,b;
wire y;
xorgate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#120;
a=1'b0;
b=1'b1;
#120;
a=1'b1;
b=1'b0;
#120;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of XOR gate:

Experiment No: 1

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Data Flow Modeling For Nand Gate:

module nandgate(a,b,y);
input a,b;
output y;
wire y;
assign y=~(a&b);
endmodule
Structural Modeling:
module nandgate(a,b,y);
input a,b;
output y;
wire y;
nand(y,a,b);
endmodule

Test Bench for NAND gate:

module nandgate_tst();
reg a,b;
wire y;
nandgate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#140;
a=1'b0;
b=1'b1;
#140;
a=1'b1;
b=1'b0;
#140;
a=1'b1;
b=1'b1;
end
endmodule

Experiment No: 1

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Functional Simulation of NAND gate:

NOR GATE:
Data Flow Modeling:
module norgate(a,b,y);
input a,b;
output y;
wire y;
assign y=~(a|b);
endmodule
Structural Modeling:
module norgate(a,b,y);
input a,b;
output y;
wire y;
nor(y,a,b);
endmodule

Test Bench for NOR gate:

module norgate_tst();

Experiment No: 1

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reg a,b;
wire y;
norgate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#100;
a=1'b0;
b=1'b1;
#100;
a=1'b1;
b=1'b0;
#100;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of NOR gate:

Experiment No: 1

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Reg No: 12mvd0031

XNOR GATE:
Data Flow Modeling:
module xnorgate(a,b,y);
input a,b;
output y;
wire y;
assign y=~(a^b);
endmodule
Structural Modeling:
module xnorgate(a,b,y);
input a,b;
output y;
wire y;
xnor(y,a,b);
endmodule
Test Bench for XNOR gate:
module xnorgate_tst();
reg a,b;

Experiment No: 1

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wire y;
xnorgate a1(a,b,y);
initial
begin
a=1'b0;
b=1'b0;
#100;
a=1'b0;
b=1'b1;
#100;
a=1'b1;
b=1'b0;
#100;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of XNOR gate:

Experiment No: 1

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Reg No: 12mvd0031

Experiment No: 1

b.Half-Adder and Full-Adder using structural Modeling:

Half-Adder :
Dataflow level modeling:
module halfadder(a,b,s,c);
input a,b;
output s,c;
wire s,c;
assign s=a^b;
assign c=a&b;
endmodule
Structural modeling:
module halfadder(a,b,s,c);
input a,b;
output s,c;
wire s,c;
xor (s,a,b);
and (c,a,b);
endmodule
Test Bench for Half Adder :
module ha_tst();
reg a,b;
wire s,c;
halfadder ha (a,b,s,c);
initial
begin
a=1'b0;
b=1'b0;
#100;
a=1'b0;
b=1'b1;
#100;
a=1'b1;
b=1'b0;
#100;
a=1'b1;
b=1'b1;
end

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endmodule

Functional Simulation of Half Adder:

Full-Adder:
Structural Modeling:
module fulladdr(a,b,ci,s,c);
input a,b,ci;
output s,c;
wire w,s,c;
xor (w,a,b);
xor (s,w,ci);
and (c,w,ci);
endmodule
Data flow modeling:

module fulladder(a,b,ci,s,c);
input a,b,ci;
output s,c;

Experiment No: 1

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wire s,c;
assign s=a^b^ci;
assign c=((a&b)|(b&ci)|(ci&a));
endmodule
Test Bench for Full Adder :
module fo_tst();
reg a,b,ci;
wire s,c;
fulladder fa (a,b,ci,s,c);
initial
begin
a=1'b0;
b=1'b0;
ci=1'b0;
#100;
a=1'b0;
b=1'b0;
ci=1'b1;
#100;
a=1'b0;
b=1'b1;
ci=1'b0;
#100;
a=1'b0;
b=1'b1;
ci=1'b1;
#100;
a=1'b1;
b=1'b0;
ci=1'b0;
#100;
a=1'b1;
b=1'b0;
ci=1'b1;
#100;
a=1'b1;
b=1'b1;
ci=1'b0;
#100;
a=1'b1;
b=1'b1;
ci=1'b1;
end
endmodule

Experiment No: 1

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Experiment No: 1

Functional Simulation of Full Adder:

c.Half-Subtractor and Full-Subtractor using Dataflow modeling:

Half-Subtractor:
Structure Modeling:
module halfsubtractor(a,b,d,c);
input a,b,;
output d,c;
wire w,d,c;
xor (d,a,b);
not (w,a);
and (c,w,b);
endmodule

Dataflow Modeling:
module halfsubtractor(a,b,d,c);

input a,b;
output d,c;

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Experiment No: 1

wire d,c;
assign d=a^b;
assign c=(~a)&b;
endmodule
Test Bench for Half Subtractor:
module hs_tst();
reg a,b;
wire d,c;
halfsubtractor hs (a,b,d,c);
initial
begin
a=1'b0;
b=1'b0;
#100;
a=1'b0;
b=1'b1;
#100;
a=1'b1;
b=1'b0;
#100;
a=1'b1;
b=1'b1;
end
endmodule

Functional Simulation of Half subtractor:

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Reg No: 12mvd0031

Full-Subtractor:
Structural modeling:
module fullsubtrac(a,b,c,d,b0);
input a,b,c;
output d,b0;
wire d,b0,w1,w2,w3,w4,w5;
xor(w1,a,b);
xor(d,w1,c);
not(w2,a);
not(w3,w1);
and(w4,w2,c);
and(w5,w3,c);
or(b0,w5,w4);
endmodule
Dataflow modeling:
module fullsubtrac(a,b,c,d,b0);
input a,b,c;
output d,b0;
assign d=a^b^c;
assign b0=(~a&b)|(~a&c)|(b&c);
endmodule

Experiment No: 1

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Reg No: 12mvd0031

Test Bench for Full Subtractor:

module fs_tst();
reg a,b,c;
wire d,b0;
fullsubtrac out(a,b,c,d,b0);
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#50;
a=1'b0;b=1'b0;c=1'b1;
#50;
a=1'b0;b=1'b1;c=1'b0;
#50;
a=1'b0;b=1'b1;c=1'b1;
#50;
a=1'b1;b=1'b0;c=1'b0;
#50;
a=1'b1;b=1'b0;c=1'b1;
#50;
a=1'b1;b=1'b1;c=1'b0;
#50;
a=1'b1;b=1'b1;c=1'b1;
end
endmodule
Functional Simulation of Full subtractor:

Experiment No: 1

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Reg No: 12mvd0031

Experiment No: 1

d.Decoder and Encoder using case, casex and casez statements:

Decoder:
Structural modeling of decoder:
module dec(a,b,d);
input a,b;
output [3:0]d;
wire w1,w2;
not(w1,a);
not(w2,b);
and(d[0],w1,w2);
and(d[1],w1,b);
and(d[2],a,w2);
and(d[3],a,b);
endmodule
Dataflow modelling of decoder:
module deco(a,b,d);
input a,b;
output [3:0]d;
wire [3:0]d,w1,w2;
assign w1=~a;
assign w2=~b;
assign d[0]=w1&w2;
assign d[1]=w1&b;
assign d[0]=a&w2;
assign d[0]=a&b;
endmodule

Test Bench for DECODER:

module dec24_test();
reg a,b;
wire[3:0]d;
deco d1(a,b,d);
initial
begin
a=1'b0;b=1'b0;
#100;
a=1'b1;b=1'b0;

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#100;
a=1'b0;b=1'b1;
#100;
a=1'b1;b=1'b1;
end
endmodule

Functional Simulation of Decoder:

Experiment No: 1

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ENCODER:
Structural modeling of encoder:
module encoder (x,y,z,d);
input [7:0] d;
output x,y,z;
wire x,y,z;
or(x,d[4]|d[5]|d[6]|d[7]);
or(y,d[2]|d[3]|d[6]|d[7]);
or(z,d[1]|d[3]|d[5]|d[7]);
endmodule
Dataflow modelling of encoder:
module encoder(x,y,z,d);
input [7:0]d;
output x,y,z;
wire x,y,z;
assign x=d[4]|d[5]|d[6]|d[7];
assign y=d[2]|d[3]|d[6]|d[7];
assign z=d[1]|d[3]|d[5]|d[7];
endmodule
Test Bench for encoder:

Experiment No: 1

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Experiment No: 1

module enc_tst();
reg [7:0]d;
wire x,y,z;
encoder p(x,y,z,d);
initial
begin
d[0]=1'b1;d[1]=1'b0;d[2]=1'b0;d[3]=1'b0;d[4]=1'b0;d[5]=1'b0;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=0'b1;d[1]=1'b1;d[2]=1'b0;d[3]=1'b0;d[4]=1'b0;d[5]=1'b0;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b1;d[3]=1'b0;d[4]=1'b0;d[5]=1'b0;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b0;d[3]=1'b1;d[4]=1'b0;d[5]=1'b0;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b0;d[3]=1'b0;d[4]=1'b1;d[5]=1'b0;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b0;d[3]=1'b0;d[4]=1'b0;d[5]=1'b1;d[6]=1'b0;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b0;d[3]=1'b0;d[4]=1'b0;d[5]=1'b0;d[6]=1'b1;d[7]=1'b0;
#20;
d[0]=1'b0;d[1]=1'b0;d[2]=1'b0;d[3]=1'b0;d[4]=1'b0;d[5]=1'b0;d[6]=1'b0;d[7]=1'b1;
end
endmodule

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Reg No: 12mvd0031

Experiment No: 1

Functional Verification:

e.Code Convertor & Parity generators using reduction operators:

Binary to Grey Converter:

Data flow modeling of binary to gray converter:
module bg(a,b,c,d,w,x,y,z);

Date: 7-8-2012
Reg No: 12mvd0031

Experiment No: 1

input a,b,c,d;
output w,x,y,z;
wire w,x,y,z;
assign w=a;
assign x=a^b;
assign y=c^b;
assign z=c^d;
endmodule

Structural modeling of binary to grey converter:

module bg(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire w,x,y,z;
or (w,a);
xor (x,a,b);
xor (y,b,c);
xor (z,c,d);
endmodule
TeSt Bench for binary to gray converter:
module bg_tst();
reg a,b,c,d;
wire w,x,y,z;
bg b1(a,b,c,d,w,x,y,z);
initial
begin
a=1'b0;b=1'b0;c=1'b1;d=1'b0;
#25
a=1'b0;b=1'b0;c=1'b0;d=1'b0;
#25
a=1'b0;b=1'b1;c=1'b1;d=1'b0;
end
endmodule

Functional simulation of binary to grey converter:

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Reg No: 12mvd0031

Grey to Binary converter:

Dataflow modeling of grey to binary:
module gb(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire w,x,y,z;
assign w=a;
assign x=w^b;
assign y=x^c;
assign z=y^d;

Experiment No: 1

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endmodule
Structural modeling of grey to binary:
module gb(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire w,x,y,z;
or (w,a);
xor (x,w,b);
xor (y,x,c);
xor (z,y,d);
endmodule
Test Bench of grey to binary:
module gb_tst();
reg a,b,c,d;
wire w,x,y,z;
gb b1(a,b,c,d,w,x,y,z);
initial
begin
a=1'b0;b=1'b0;c=1'b1;d=1'b0;
#50;
a=1'b0;b=1'b0;c=1'b0;d=1'b0;
#50;
a=1'b0;b=1'b1;c=1'b1;d=1'b0;
end
endmodule
Functional simulation of grey to binary:

Experiment No: 1

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Parity Generator:
Structural modeling of parity generator:
module pgen(x,y,z,p);
input x,y,z;
output p;
wire p,w1,w2;
xor(w1,x,y);
xor(w2,w1,z);
not (p,w2);
endmodule

Dataflow modeling of parity generator:

module pg(a,b,c,y);
input a,b,c;

Experiment No: 1

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output y;
wire y;
assign y=a^(b^c);
endmodule

Test Bench of parity generator :

module pg_tst();
reg a,b,c;
wire y;
pg g1(a,b,c,y);
initial
begin
a=1'b0;b=1'b0;c=1'b0;
#50;
a=1'b1;b=1'b1;c=1'b0;
#50;
a=1'b0;b=1'b1;c=1'b1;
#50;
a=1'b1;b=1'b0;c=1'b0;
#50;
a=1'b1;b=1'b1;c=1'b1;

Experiment No: 1

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#50;
a=1'b1;b=1'b0;c=1'b1;
end
endmodule

Functional simulation of parity generators:

Experiment No: 1

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Reg No: 12mvd0031

Experiment No: 1

f.Multiplexer and De-multiplexer using nested if-else construct:

Demultiplexer:
Data modeling of demultiplexer:
module demux14(en,s1,s2,d);
input en,s1,s2;
output [3:0]d;
wire [3:0]d;
assign d[0]=~s1&~s2&en;
assign d[1]=~s1&s2&en;
assign d[2]=s1&~s2&en;
assign d[3]=s1&s2&en;
endmodule
Structural modeling of demultiplexer:
module demux(en,s1,s0,a);
input en,s1,s0;
output [3:0]a;
wire w1,w2;
wire [3:0]a;
not(w1,s1);
not(w2,s0);
and(a[0],w1,w2,en);
and(a[1],s0,w1,en);
and(a[2],w2,s1,en);
and(a[3],s1,s0,en);
endmodule

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Reg No: 12mvd0031

Experiment No: 1

Test Bench for Demultiplexer:

module demux_test();
reg en,s1,s0;
wire [3:0]a;
demux d1(en,s1,s0,a);
initial
begin
s1=1'b0;s0=1'b0;
en=1'b1;
#50;
s1=1'b0;s0=1'b1;
en=1'b1;
#50;
s1=1'b1;s0=1'b0;
en=1'b1;
#50;
s1=1'b1;s0=1'b1;
en=1'b1;
end
endmodule

Functional Simulation of De-multiplexer:

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Reg No: 12mvd0031

Multiplexer:

Experiment No: 1

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Reg No: 12mvd0031

Experiment No: 1

Structural modeling of multiplexer:

module mux41(i,s,y);
input[3:0]i;
input [1:0]s;
output y;
wire y,w1,w2,w3,w4,w5,w6;
not (w1,s[0]);
not (w2,s[1]);
and(w3,i[0],w1,w2);
and(w4,i[1],s[0],w2);
and(w5,i[2],w1,s[1]);
and(w6,i[3],s[0],s[1]);
or (y,w3,w4,w5,w6);
endmodule

Data flow modeling of multiplexer:

module mux41(i,s,y);
input[3:0]i;
input [1:0]s;
output y;
wire y;

assign y=(~s[1]&~s[0]&i[0]) | (~s[1]&s[0]&i[1]) |(s[1]&~s[0]&i[2]) | (s[1]&s[0]&i[3]);

endmodule
Test bench Code for 4:1 Multiplexer:
module mux_tst();
reg s1,s0,a,b,c,d;

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Reg No: 12mvd0031

Experiment No: 1

wire y,w1,w2,w3,w4;
mux4_1 mo(s1,s0,a,b,c,d,y);
initial
begin
a=1'b1;b=1'b1;c=1'b0;d=1'b1;s1=1'b0;s0=1'b0;
#100;
a=1'b1;b=1'b1;c=1'b1;d=1'b0;
s1=1'b0;s0=1'b1;
#100;
a=1'b1;b=1'b1;c=1'b1;d=1'b0;
s1=1'b1;s0=1'b0;
#100;
a=1'b1;b=1'b1;c=1'b1;d=1'b0;
s1=1'b1;s0=1'b1;
end
endmodule

Date: 7-8-2012
Reg No: 12mvd0031

Functional Simulation of Multiplexer:

Experiment No: 1