MT 2012/2013

Joo Vaz
1
Prof. Joo Vaz


Wireless Integrated Circuits and Systems Group
Instituto de Telecomunicaes


Instituto Superior Tcnico
Technical University of Lisbon
RADIO-FREQUENCY TUNED
LOW-NOISE AMPLIFIERS
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2
Basic notions about electric noise
Definition: Electric noise is the random fluctuation that affects
el ectri c quanti ti es (vol tage and current) and whose
instantaneous value can not be precisely predicted.
The studied noise is generated by the circuit active and
passive components.
Won't be considered perturbations due to bad electrical
contacts, electrical switching, proximity to electrical
machinery, natural phenomenon, etc.
Noise consideration is important in circuits where signals
and noise have the same order of magnitude.
Electric noise always exits in all electric circuits.
Introduction
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Noise characterization
In electric circuits noise exists in voltage and current form.
Noise signals are always random perturbations added to the
deterministic signals.
Because instantaneous value is random impossible to write
down an equation for v(t) or i(t).
If the random process v(t) is ergodic (which implies
stationary), it can be characterized by its time averages.
Mean-square value (V
2
)
( )
2 2
0
1
lim

=

T
T
v v t dt
T
2
v v =
Root mean-square (rms) (V)
Noise
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Noise spectral density
Deterministic signals Spectrum
Random signals Power spectral density (PSD) S(f)

S f
( )
= lim
T
V
T
f ,T
( )
2
T
( )
2
0
v S f df

=

(V
2
/Hz)
(V
2
)
V
T
(f) is the Fourier transform of v
T
(t) which is one of a
truncated sample of v(t).
Noise
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Noise bandwidth Zf
Consider a circuit with A
V
(f) voltage gain and S
i
(f) constant with f.
( ) ( ) ( )
2
0 V i
S f A f S f =
( ) ( )
2 2
2
0 0
0 0 0
V i i V
v S df A f S df S A f df

= = =



( )
2
2
0
1
V
m
f A f df
A

=

( )
2
2
2
0 0
0 0
V i i m
v S df A f S df S A f

= = =

Real filter
Equivalent rectangular filter
that produces the same noise
Noise
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Noise types
N kT f =
Thermal or Johnson noise
Origin Random motion of electrons in a lossy resistor will
produce a noise voltage at its terminals even with a null average
current.
Available noise power
k=1.38x10-23 J/K is the Boltzmann constant, T is the absolute
temperature in Kelvin (16.8C290K) and Zf is the noise
bandwidth.
Resistance case
Knowing the available power at its terminals it is possible to
obtain a Thevenin or a Norton noise equivalent model
Noise
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Available power definition
Available power from a source, P
SAV
, is the power it delivers to a
matched load. Assuming a generator with resistive internal impedance
R
S
and a matched load R
L
=R
S
( )
2
2 2
2
1 1 1
2 2 8
s
s L
L SAV
L L S
V
V V
P P
R R R
= = =
V
s
V
L
R
S
R
L
( )
2
2 2
2
1 1 1
2 2 8
s
s L
L SAV
L L s
I
I I
P P
G G G
= = =
i) Thevenin equivalent
ii) Norton equivalent
I
s G
S
G
L
I
L
Note: For rms values use 1/4 instead of 1/8.
Noise
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2
4
n
v kTR f =
2
4
n
i kTG f =
Because thermal noise is white noise

Voltage and current power spectral densities are cte with

frequency and given by S
v
(f)=4kTR and S
i
(f)=4kTG
Example: R=100k!, T=293K, Zf=1MHz rms value v
n
=40.3V.
R
ideal
v
n
R
real
G
real G
ideal
i
n
Noise
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Flicker or 1/f noise
Origin Cause mainly by traps due to contamination and crystal
defects. These traps capture and release carriers in a random
fashion. Found in all active devices and in some passives like
carbon resistors.
2
1
a
n b
I
i K f
f
=
Noise current square-mean value
I is direct current, K
1
is a device dependent constant, a is a cte
between 0.5 and 2, b is a close to unity cte, and Zf is the noise
bandwidth.
Usually b=1 so PSD proportional to 1/f

Named 1/f noise
Noise
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Shot noise
Origin Caused mainly by the individual crossing of a carrier
through a junction which is a random process. It is always
present in a forward biased junction.
2
2
n D
i qI f =
Noise current square-mean value
I
D
is direct current, q is the electron charge (1.6x10
-19
C), and Zf
is the noise bandwidth.
Noise
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Signal to noise ratio (SNR)
{ }

= =
in
2
noise _ in in
in
2
in
in
in *
in in
*
in in
Z
1
Re V
2
1
N
Z
1
Re V
2
1
Z
V
V Re
2
1
I V Re
2
1
S
Input signal to noise ratio

2
noise _ in
2
in
in
in
in V
V
N
S
N
S
= =

=
in
2
2
sn in
in
2 2
s in
Z
1
Re V
2
1
N
Z
1
Re V
2
1
S
If =V
in
/V
s
(matching =0.5 )
2
sn
2
s
in V
V
N
S
=

Ex: Input of a noiseless circuit

V
s
Z
in
V
in
I
in
R
S
Noiseless
circuit
Noise
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Because in the SNR parameter + does not appear SNR
does not depend on mismatch level

SNR can be calculated with the input power or with
the input available power
sav in sav
sav
in
in
N
S
N
S
N
S
N
S

=
Notes
The impedances cut in SNR.
In microwaves SNR is usually evaluated with power values.
In RF the SNR is usually evaluated with squared voltage values.
Noise
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F =
S
N

in
S
N

out
=
S
N

sav
S
N

out
Noise factor (F)
F>1 input to output SNR maintains (if the two-port is noiseless) or reduces
(if the two-port is noisy)
Definition (IEE):
It is the relation between the two-port input and output SNR obtained with
an input thermal noise source at T
0
=290K (16.8C).
Noise
F =
S
sav
N
sav
S
out
N
out
=
S
sav
S
out
N
out
N
sav
=
1
G
A
N
qav
+ G
A
N
sav
N
sav
= 1 +
N
qav
G
A
N
sav
Note: F in decibels is called noise figure NF=10log(F)
where N
qav
is the internal generated 2-port output available noise
and G
A
the available power gain.

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Cascade stages F (Friis equation)
V
s
V
in
R
S
NF
1
G
P1
NF
2
G
P2
NF
m
G
Pm
V
out
R
out1 R
out2

F
tot
=F
1
+
F
2
1
G
A1
+ +
F
m
1
G
A1
G
A2
G
A m1
( )
Notes
G
Ai
is the i stage available power gain.
F
i
is the i stage F calculated with i-1 stage source impedance.
First stage F and G
A
are determinant.
Noise
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Input referred noise
A noi sy two-port can be
modeled with two input noise
sources. Usually they are
correlated.

V
n
is calculated with the real circuit input short-circuited, and I
n
with the
input open-circuited.

Noise sources V
n
and I
n
are correlated because the depend on the same
transistor internal noise sources.

Noiseless
circuit
i
n
2
v
n
2
Noisy
circuit
Noise
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S
N

sav
=
V
s
2
V
ns
2
S
N

out
=
V
s
2
A
VT
2
V
ns
2
A
VT
2
+ V
n
+ I
n
R
S
( )
2
A
VT
2
F = 1 +
V
n
+ I
n
R
S
( )
2
V
ns
2
F =
V
nout
2
A
VT
2

1
V
ns
2
onde V
nout
2
= V
ns
2
+ V
n
+ I
n
R
S
( )
2
( )
A
VT
2
The result is
Another way for F calculation can be obtained from the previous equation
where V
nout
is the total output noise voltage
Noise
V
s
R
S
Noiseless
circuit
i
n
2
v
n
2 v
ns
2
V
in
V
out
Two-port noise matching
A
VT
=
V
out
V
s
Where voltage gain:
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Next step is to obtain the relation between F and the source
admittance Y
s
=G
s
+jB
s
. The following circuit is used:
It can be shown that
( )
2
IT
2
n S n
2
IT
2
ns
2
IT
2
s
out
2
ns
2
s
sav A I Y V A I
A I
N
S
I
I
N
S
+ +

=

where A
IT
is the current gain given by
s
out
IT
I
I
A =
I
s
Y
S
Noiseless
circuit
i
n
2
v
n
2
i
ns
2
V
in
V
out
Y
L
I
out
Noise
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Noise factor is given by
In this case it is assumed that I
n
decomposed in two components: I
u
and I
c
. The former (I
u
) is uncorrelated with V
n
, the second (I
c
) is totally
correlated with V
n
and its correlating admittance is Y
c
=G
c
+jB
c
defined
by I
c
=Y
c
V
n
.
F = 1 +
V
n
Y
S
+ I
n
( )
2
I
ns
2
The expression cannot be simplified
because V
n
and I
n
are correlated
So F is obtained with I
n
=I
u
+Y
c
V
n

F = 1 +
I
u
2
I
ns
2
+
V
n
2
Y
c
+ Y
S
2
I
ns
2
Noise
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f kT 4
I
G
f kT 4
I
G
f kT 4
V
R
2
ns
s
2
u
u
2
n
n

Defining the following quantities

The F equation is
F = 1 +
G
u
G
s
+
R
n
G
s
G
c
+ G
S
( )
2
+ B
c
+ B
S
( )
2

F value depends on Y
S
. The admittance Y
SOPT
that minimizes F
can be calculated solving the equations:
F
G
S
= 0
F
B
S
= 0
Noise
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F = F
min
+
R
n
G
s
G
s
G
sopt
( )
2
+ B
s
B
sopt
( )
2

obtaining Y
SOPT
=G
SOPT
+jB
SOPT
where
c sopt
2
c
n
u
sopt
B B G
R
G
G = + =
F
min
= 1 + 2R
n
G
u
R
n
+ G
c
2
+ G
c

Minimum F value is given by

Finally F can be written as
Noise
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G
s
= G
sopt
B
s
= B
sopt
F = F
min
Note that for a given transistor, bias point and frequency value,
G
sopt
, B
sopt
parameters, noise resistance R
n
and F
min
, can be obtained
by simulation or analytically if a transistor noise model exists. An
alternate way is to obtain the parameters through experimental
measurements.
In this conditions Y
s
choice leads to the F value.
Usually Y
sopt
value doesn't correspond to the Ys value that
conjugate matches the input and also maximizes available gain

gain-noise trade-off
Resume
Noise
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Circuit example: resistive network
V
s
R
S
R
1
R
2
V
out
F =
V
nout
2
V
ns
2

1
A
VT
2
=
V
ns
2
A
VT
2
+ V
n1
2
A
VT1
2
+ V
n2
2
A
VT2
2
V
ns
2
A
VT
2
where
S 2 1
S 1
2 n
out
2 VT
S 2 1
2
s
out
1 VT VT
R R R
R R
V
V
A ;
R R R
R
V
V
A A
+ +
+
= =
+ +
= = =
If
2
2
2 n 1
2
1 n S
2
ns
R f kT 4 V R f kT 4 V R f kT 4 V = = =
obtains
F = 1 +
R
1
R
S
+
R
1
+ R
S
( )
2
R
2
R
S
Noise
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Series resistance
R
2
= F = 1 +
R
1
R
S
Parallel resistance
R
1
= 0 F = 1 +
R
S
R
2
V
s
R
S
R
1
V
out
V
s
R
S
R
2
V
out
Particular cases
Noise
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Large signal model
Almost all MOSFET models use the same circuit topology.
The differences are is the components equations.

Topology of the MOSFET large-signal model for low
frequency simulations:
I
D
I
BS
I
BD
C
BS
C
BD
C
GS
C
GD
B
D
G
C
GB
S
R
S
R
D
MOSFET
MOSFET noise model
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Small signal model
Topology of the MOSFET small-signal model for low
frequency simulations obtained by linearization of the large-
signal one (neglecting I
BS
e I
BD
):
B
D S
R
S
R
D
s
i
d
i
C
sb
C
db
g
m
.v
gsi
C
gs
C
gd
G
C
gb
g
ds
g
mb
.v
bsi
MOSFET
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Small-signal high-frequency model with noise sources
B
D S
R
D
g
i
s
i
d
i
C
sb
g
m
g
mb
C
gs
C
gd
G
R
G
C
gb
g
ds
R
S
i
R
D
2
i
R
S
2
R
DBS
i
R
DSB
2 R
SB
i
R
SB
2
i
R
DB
2
R
DB
C
db
i
d
2
b
i
v
R
G
2
i
gind
2
MOSFET
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Thermal noise in resistances R
D
, R
S
, R
G
, R
SB
, R
DB
and R
DSB
:

[ ]
[ ]
2
DSB
2
R
DB
2
R
SB
2
R
2
G
2
R
S
2
R
D
2
R
A
R
kT 4
i
R
kT 4
i
R
kT 4
i
V R kT 4 v
R
kT 4
i
R
kT 4
i
DSB DB SB
G S D
= = =
= = =
[ ]
2
eff eff OX
2
m
0 ds
2
d
A
f L W C
K g
g kT 4 i


+ =
All the expressions present mean-square values forZf=1Hz
Channel noise: thermal and flicker (1/f) [van der Ziel]:

g
ds0
is the output conductance for V
DS
=0. Depending on the
working region and for long-channel devices 2/3<_<1, being 2/3 in
saturation and 1 with V
DS
=0.
Noise sources equations
MOSFET
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Notes
- With constant I
DS
1/f noise decreases for higher L bigger
devices have lower noise.
- NMOS K parameter is much higher (50 times) PMOS PMOS
has less 1/f noise than NMOS.
[ ]
2 2
d
2
g
*
d g
0 ds
gs
2
2
gind
A i i c i i
g 5
C
kT 4 i =

=
Noise in the gate is induced by channel thermal noise it is
correlated with it. Important for RFCMOS (increases with +
2
).
For long-channel and saturation =4/3, c=j0.395 and _=0.2. For
L<1.7m an increase in and _ is produced but this fact is not yet
explained and is still research subject.
Gate induced noise:

MOSFET
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Shot noise:

This kind of noise is important in sub-threshold regime.
Many simulators do not include it.
MOSFET
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Main characteristics

The input impedance of a low noise amplifier (LNA) should be
matched to the antenna impedance. Usually its value is 50!.

Because the LNA is always the first block in a receiver chain, it is
important that the LNA added noise be low. This can be seen with the
Friis relation because it is the first block that has the major influence
on the total noise factor of the chain.

The dynamic range should be high, that is, be able to amplify very
weak and very strong signals keeping the system specifications
Care with bias points and transistors size.

The following stages analysis is simplified because it assumes the
transistor model has only two elements C
gs
and g
m
, and that channel
thermal noise is the only one that exists. However the simple results
are very useful because they can lead to quantitative comparisons
between different topologies and be the starting point for the
components design.
LNA
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Topologies
LNA topologies are chosen with the purpose of achieving a
50! input match with a low noise factor.
Used topologies can be divided into four groups:
Resistive termination (RT)
Series and/or parallel feedback (SPF)
Inductive degeneration (ID)
Common source (CS) or common gate (CG) stages
Circuits can also have single ended or differential accesses.

LNA
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V
in
V
out
R
1
Z
in
R
2
V
DD
V
GG
V
out
I
SS Z
in
V
DD
V
in
V
in
L
S
V
DD
V
out
Z
in
V
in
V
DD
V
out
R
1
Z
in
High F
Low
gain

Low F
Medium
gain

High F
Medium
gain

RT
SPF
CG ID
Medium F
and gain

LNA
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Input impedance
G
in
in
in
R
I
V
Z = =
Voltage gain
L m
in
out
V
L in m L gs m out
Z g
V
V
A
Z V g Z V g V
= =
= =
AC schematic

L
m
s
out
VT
Z
2
g
V
V
A = =
If matched
R
G
=R
S
R
S
C
gs
V
s
g
m
.v
gs
L
G
Z
in
V
gs
Z
L
V
out
V
in
R
G
Assuming that L
G
and C
gs
are in
resonance:
Common source with R
G
LNA
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Noise factor

F = 2 +
4
R
S
g
m
where =
g
m
g
dso

F =
V
nout
2
V
ns
2

1
A
VT
2
=
I
nd
2
Z
L
2
+ V
ns
2
A
VT
2
+ V
ng
2
A
VT
2
V
ns
2
A
VT
2
because V
ns
2
= V
ng
2
Note that the circuit impedance in
parallel with I
nd
is only Z
L
.

Assuming input matching and tuning, F
can be calculated:
F = 2 +
I
nd
2
Z
L
2
V
ns
2
A
VT
2
= 2 +
4kT g
dso
( ) Z
L
2
4
4kTR
S
( ) g
m
Z
L
( )
2
= 2 +
4 g
dso
R
S
g
m
2
= 2 +
4
R
S
g
m
AC schematic

R
S
C
gs
V
s
L
G
Z
in
V
gs
V
in
R
G
g
m
.v
gs
Z
L
V
out
i
nd
2
In saturation +1
and i f l ong-channel
_=2/3 NF>>2=3dB
LNA
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Degenerated common source topology
(DCS) uses inductive feedback to create a
resi st i ve part i n Z
i n
wi t hout any
resistance, so it does not increase noise.

Is one of the most popular solutions for
the first stage.

V
in
L
S
L
G
V
DD
V
out
M
1
Z
L
A good gain-noise trade off is achieved with this topology.

Low NF values are obtained.

Inductive source degeneration
Topology
LNA
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36
Input impedance
( )
gs
S G
gs
S m
in
C S
1
L L S
C
L g
Z + + + =
( )
gs m in S
gs
in
G in in
V g I L S
C S
I
L I S V + + + =
gs
in
gs
C S
I
V =
For matching and tuning

( )
gs
S m
S
gs S G
2
0
C
L g
R
C L L
1
=
+
=
( )
S T
gs
S m
0 in
L
C
L g
Z =
Note that

AC schematic

R
S
C
gs
V
s
L
G
g
m
.v
gs
L
S
Z
in
V
gs
Z
L
V
out
V
in
LNA
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Voltage gain
in in out m L
out m gs L gs in V
gs in in gs in
I V V g Z
V g V Z V I A
SC Z V SC Z
= = = = =
( )
2
1
m L
V
gs S G gs S
g Z
A
S C L L SC L
=
+ + +
Under matching and tuning conditions at +
0
voltage gain is
V meff L meff
0 S
whe
1
A G Z r
L
e G

= =
L
meff
s
out
VT
Z
2
G
V
V
A = =
LNA
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38
Noise factor
F = 1 +

1 +
L
G
L
S
F =
V
nout
2
V
ns
2

1
A
VT
2
=
I
nout
2
Z
L
2
+ V
ns
2
A
VT
2
V
ns
2
A
VT
2
Under matching and tuning conditions
it can be shown that I
nout
=I
nd
/2. F can
be described:
F = 1 +
I
nd
2
Z
L
2
4 V
ns
2
A
VT
2
= 1 +
4kT g
dso
( ) Z
L
2
4 4kTR
S
( )
Z
L
2
0
L
S

2
AC schematic

F = 1 + g
ds0
R
S

2
In saturation g
m
=g
ds0
R
S
C
gs
V
s
L
G
g
m
.v
gs
L
S
Z
in
V
gs
Z
L
V
out
V
in
i
nd
2
LNA
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39
Topology
Advantages:
Higher voltage gain than DCS because M
2
reduces
Miller effect. Should be used as first stage in the
chain.
Less instable because feedback is low.
Easier minimum noise matching and higher gain
than DCS.
Less DC power consumption than 2 cascaded
stages.
Disadvantages:
V
DD
higher than DCS (1 MOS more).
P
C
(-1dB) and IP3 lower than DCS.
V
in
L
S
L
G
V
G
L
D
V
DD
V
out
M
1
M
2
Inductive source degenerated cascode
LNA
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40
Input impedance
m gs in
in
in
gs in
gs m gs gs in
g C S
1
I
V
Z
V V
V g C S V I
+
= =
=
=
Voltage gain
L m
in
out
V
L in m L gs m out
Z g
V
V
A
Z V g Z V g V
= =
= =
AC schematic

Without L
S
:
Assuming that L
S
and C
gs
are
tuned:
m
in
g
1
Z =
C
gs
g
m
.v
gs
L
S
Z
in
V
gs
Z
L
V
out
R
S
V
s
V
in
I
in
L
m
s
out
VT
Z
2
g
V
V
A = =
If matched
Z
in
=R
S
Common gate
LNA
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41
Noise factor

F = 1 +
4kTg
dso
( )
Z
L
2
4 4kTR
S
( )

g
m
2
Z
L

2
= 1 +
g
dso
g
m
F = 1 +

where =
g
m
g
dso
F =
V
nout
2
V
ns
2

1
A
VT
2
= 1 +
I
nout
2
Z
L
2
V
ns
2
A
VT
2
AC schematic

With matched input it can be
shown that I
nout
=I
nd
/2. F is given
by:
For long-channel MOS _=2/3 NF> 5/3=2.3dB
For short-channel MOS 2<_<3 NF> 3=4.8dB
In saturation +1
Z
L
V
out
i
nd
2
R
S
C
gs
V
s
L
S
Z
in
V
gs
V
in
g
m
.v
gs
LNA
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42
Differential
V
in+
L
G
L
D
V
DD
V
out
I
SS
M
2
P
L
G
C
G
C
G
V
in-
M
1
L
D
M
4
M
3
Simplified
schematic
Advantages:
A good ground point in the circuit is
difficult to obtain; several bondwire
in the same pad is difficult and
expensive to manufacture a
differential circuit is the solution
because nets in the symmetry axis
behaves as AC grounds (ex: P
point).
Common mode noi se has no
influence in differential output. The
same with V
DD
source.
Avoids instability due to feedback
through ground points.
More linear than DCS.
Disadvantages:
F o r t h e s a m e D C
consumption total NF and
voltage gain are worth than
DCS.
LNA
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43
Electrostatic discharge protection (ESD)
To avoid that static charges in the signal pads accidentally destroy
the circuits, protecting these pads with diodes is common in CMOS
technologies.
V
DD
pad
V
SS
bond wire
Although diodes are reverse biased, in
hi gh f requenci es, t hey present a
capacitance that attenuates the signal and
degrades NF.

ESD less used
Recent publications report LNA with NF<1dB and ESD.
Examples: Gramegna et al., JSS, pp. 1010, July, 2001.
Protection against pulses standard HBM (human body
model) ESD [-3kV, 2.3kV], 0.35m, 1.2dB NF, 900MHz.
Leroux et al., JSS, pp. 760, June 2002.
Protection against pulses [-1.4kV, -0.6kV], 0.35m,
0.8dB NF, 1.23GHz.

LNA
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44
Design strategy for the LNA second stage
Usually an LNA has a low noise first stage and a buffer or
gain second stage.

Buffer function is to present a high input impedance Z
in
to
the first stage, with a low load impedance at its output (for
example 50!). This way the first stage voltage gain will be
high. It is useful if the LNA load impedance is low and like
this transducer gain is maximized.

However, if the load impedance is high, with a buffer stage
the output mismatch is very high. Although this doesnt
reduce LNA NF (NF doesnt depend on output load) the LNA
and receiver transducer gains will decrease. In this case it is
better to improve available gain G
A
with a second gain stage,
and thus minimizing receiver total NF.
Design methodology
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45
In both cases the output is usually tuned at the LNA center
frequency. If possible, a conjugate matching is also desirable,
which means that impedances real parts must be equalized.
But for high load impedances and CMOS technologies, that is
difficult to achieve due to passives elements losses.

However, common for both cases is:

Study the 2
nd
stage in order to maximize its input impedance.
If an L//C circuit exists in its input it must be considered. The
input circuit quality factor will limit this maximum value.
.
After knowing Z
in
first stage should be studied with Z
in

impedance connected at its output.
Design methodology
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46
Study the amplifier in terms of NFmin, input and output
stability, input matching and power gain G
P
. Change the first
stage bias point and transistor dimensions in order to get the
best trade-off.
Now three things can append:
1) The objective is input matching and the NF is a
consequence.
2) The objective is NFmin and input matching (and gain) is a
consequence.
3) The objective is NF and input-matching trade-off
noise and G
A
circles.
After having Zs value that fulfils 1, 2 or 3, design input
matching network (generator is usually 50!).
Design methodology
Design strategy for the LNA first stage
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47
The trade-off input-matching and NF can be made using noise
circles and available gain circles plotted in a Smith chart. This
requires knowledge of some microwave design techniques.
Design methodology
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48
Check wideband input and output stability. Looking at
impedances resistive parts check if negative values exits at
some frequencies. Those negative values predict possible
instability situations.
Check also wideband transducer gain G
T,
available gain G
A
,
power gain G
P
, voltage gain, NF and input reflection factor.

Do not forget that passive components have losses. By that
reason transistor NFmin value is never reached. That is why
it is necessary to design the circuit using accurate models
for all the elements included in the LNA.

Inductive degeneration can be added to improve stability.
Cascode topology can also be used.
Design methodology
Final remarks
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49
Design example for a 3GHz LNA
Schematic used in simulation Z
in
and G
P
results
As a starting point an ideal bias source can be used

DC blocking 2.5pF capacitor

Capacitor included to
tune input impedance

Buffer design with CMOS 0.35m C35 AMS technology
Design example
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Joo Vaz
50
Common-source with buffer load
Schematic used in simulation
Next step is to include first stage transistor. An ideal bias choke
inductor was used in the gate terminal. But a real bias network can be
used having the advantage of being closer to the final design.
Design example
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51
For a V
GG
=1.5V, first stage mosfet finger number, NG, was varied from
10 to 20.
Input Zin has negative real
part below 3GHz

LNA can became unstable for
lower frequencies
How to solve this ?

- Decrease NG and,or VGG
lower gain and higher NF

- Load input with resistance
higher NF



Solution Inductive source degeneration
Re Z
in
Design example
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52
Schematic used
in simulation
The input
instability problem
is solved

The output
stability is
analyzed in the
end
L
S
=2nH was
chosen looking at
Re Zin,
NF_InputMatch and
G
P
.
For a V
GG
=1.2V and L
S
=2nH, NG is changed
Design example
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53
NG=18 was chosen, for 3GHz Zin52-j153

Simple input matching network
Design example
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54
NFmin
Difference between input matching for noise or for gain
NF_InputMatch
Design example
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Joo Vaz
55
Final schematic
The output
matching was not
intentional
but a small
adjustment in the
output improved it
NG=18
VGG=1.2V
I
D1
=13.2mA
I
D2
=5mA
Capacitor value
is changed to
improve tuning
Design example
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56
Low noise amplifier on AMS CMOS 0.35m CSI
IN
L
S
L
G
L
D
V
DD
M
1
M
2
V
GG1
C
D
OUT
V
GG2 M
3
L
G L
S
L
D
V
DD
V
GG1
V
GG2
out

in

Simulated results:
f
0
=1.9GHz, G
T
=17.9dB
NF=3.8dB, S
11
=-25dB
S
22
=-16dB, S
12
=-59dB
V
DD
=3V, P
DC
=24.1mW
total area 1mm
2

Author: Pedro Brs
Examples
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57
Low noise amplifier with active balun AMS CMOS 0.35m C35
S
i
m
u
l
a
t
e
d

r
e
s
u
l
t
s

Author: Fernando Azevedo
I
REF1
out + out -
I
REF2
gnd in vdd
gnd gnd gnd
gnd gnd
gnd
gnd gnd
gnd
gnd
gnd
gnd
gnd gnd gnd
gnd
gnd
gnd
gnd
Examples
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58
Dual-band low noise amplifier UMC CMOS 0.18um
Simulated and measured results
Author: Vitor Canosa
Examples
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59
Power gains


L
P
IN
P
G
P
=
Power gain
L
T
SAV
P
G
P
=
Transducer gain
*
IN S IN
IN IN
IN IN S
Z Z V
Z
I Z Z

= =
+
Input matching
OUTAV
A
SAV
P
G
P
=
Available gain
Appendix
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60
Nonlinear behaviour

2 3
OUT IN IN IN
i av bv cv = + +
( ) ( ) ( ) ( ) ( )
1 1 2 2
cos( ) cos( )
IN OUT OUTa OUTb OUTc
v t V t V t i t i t i t i t = + = + +
Frequency generation
Assuming that an amplifier behaves like a
voltage controlled current source i
OUT
(v
IN
)

With a two-tone excitation

New frequency tones at i
OUT
will appear
at +
m,n
where m, n = -2,-1,0,1,2,

, 1 2 m n
m n = +
New +
m,n
frequencies are called k-order mixing frequencies, where k=|m|+|n|.
The +
m,n
components (v or i) are called k-order mixing products.
Appendix
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61
( ) ( )
1 1 2 2
cos( ) cos( )
OUTa IN
i t av t aV t aV t = = +
( ) ( ) ( ) ( ) {
( ) ( ) ( ) ( )
}
2 2 2 2 2
1 2 1 1 2 2
1 2 1 2 1 2
1
cos 2 cos 2
2
2 cos cos
OUTb IN
i t bv t b V V V t V t
VV t t


= = + + +

+ + +

First order mixing products

( ) ( ) ( ) ( ) {
( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
}
3 3 3
1 1 2 2
2
1 2 1 2 1 2
2
1 2 2 1 2 1
3 2 3 2
1 1 2 1 2 1 2 2
1
cos 3 cos 3
4
3 cos 2 cos 2
3 cos 2 cos 2
3 2 cos 3 2 cos
OUTc IN
i t cv t c V t V t
V V t t
VV t t
V VV t V V V t




= = +

+ + +


+ + +

+ + + +
Second order mixing products

Third order mixing products

If only n (m) is equal to zero the component is a n(m)-order harmonic.
If m=n=0 the mixing product is a DC component
Appendix
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62
( )
3
1 1 1
3
cos( )
4
i t aV cV t

= +


i
OUT
components at w
1


Usually ac<0 Gain reduces P
SAV
increase
1dB compression point
The point where gain value reduction from linear gain is 1dB
defines the 1dB compression point
1dB compression point can be specified in terms of input or output power.
P
L
P
SAT
P
L
(1dB)
P
SAV
P
SAV
(1dB)
destruction
1dB
G
T
G
T
(1dB)
P
SAV
P
SAV
(1dB)
1dB
G
T0
Appendix
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63
( ) ( ) ( ) ( ) ( ) { }
2 2
1 2 1 2 1 2 2 1
3
cos 2 cos 2
4
i t c V V t VV t = +
( )
( )
1 2
3
1
2
L
L
P
IM
P

=
Also the definition of the 3
rd
-order intermodulation distortion (IM3) is given by
3
rd
-order power component
Third ordem intermodulation intercept point (IP3)
i
OUT
components at
2w
1
-w
2
and 2w
2
-w
1

fundamental power component
P
SAV
(dBm)
P
L
(dBm)
P
L
(IP3)
P
SAV
(IP3)
IM3
2w
1
-w
2
w
1
Appendix
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64
Razavi, B., RF Microelectronics, Prentice Hall, Inc., 1998.

Lee, T., The Design of CMOS Radio-Frequency Integrated
Circuits, Cambridge University Press, 1998.

Shaeffer, D., Lee, T., A 1.5-V, 1.5-GHz CMOS Low Noise
Amplifier, IEEE Journal of Solid-State Circuits, vol. 32, no. 5,
May 1997.

Goo, Ahn, Ladwig, Yu, Lee, and Dutton, A Noise Optimization
Technique for Integrated Low-Noise Amplifiers, IEEE Journal
of Solid-State Circuits, vol. 37, no. 8, August 2002.

Maas, Stephen A., Nonlinear Microwave and RF Circuits,
Second Edition, Artech House, Inc., 2003.




References