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CENG3151 BasicVHDL For Lab PDF

The document provides an overview of basic VHDL concepts including data types, operators, coding guidelines and the VHDL design flow. It describes the VHDL code model including libraries, entities, architectures and how to describe combinational logic functions in VHDL.

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mathhoang
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47 views21 pages

CENG3151 BasicVHDL For Lab PDF

The document provides an overview of basic VHDL concepts including data types, operators, coding guidelines and the VHDL design flow. It describes the VHDL code model including libraries, entities, architectures and how to describe combinational logic functions in VHDL.

Uploaded by

mathhoang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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University of Houston Clear Lake

Computer Engineering Department

CENG 3151: Lab For Computer Architecture


Basic VHDL Overview (Part 1)

Basic VHDL Overview


VHDL: Very high speed integrated circuit Hardware Description

Language
Enables hardware modeling from the gate to system level
Used to describe/design a digital circuit
Strongly typed and not case sensitive

Lab For Computer Architecture - Fall 2016

Basic VHDL Overview


This overview will provide you enough VHDL background to do most

of the lab assignments in this class.

If you already have a good VHDL background, then you can skip

this!

Advanced VHDL will be provided later in other labs

Lab For Computer Architecture - Fall 2016

Basic Design Flow


Specification (lab requirement)

Design (Output equations, Finite


state machine, diagrams, etc)

VHDL Code

Generate RTL Functional netlist

Functional Simulation
4

Lab For Computer Architecture - Fall 2016

Note: The following steps in full


design flow will be skips:
+ place and route
+ generate programming file
+ download to physical device

Code Model
Component

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Library

[library/packages]
Entity

Entity AND_2input is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end AND_2input;

[Interface I/O ports]


Architecture Behavioral of AND_2input is
begin

Architecture body
C <= A AND B;

[Function Circuits
function]
5

end Behavioral;

Lab For Computer Architecture - Fall 2016

Code Model Library


The most commonly used libraries: ieee, std, work
std, work: visible by default (not need to include into the project)
ieee: std_logic_1164, numeric_std, numeric_std_unsigned.
For all the lab assignments, the library std_logic_1164 and numeric_std

are enough!!
Your library could be as below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- numeric_std is optional:
-- depends on the lab requirement
USE ieee.numeric_std.ALL;
6

Lab For Computer Architecture - Fall 2016

Code Model Entity


The main part of an ENTITY is PORT
Specifies all input and output pins of circuit
Syntax:

ENTITY entity_name IS
PORT(
port_name: port_mode signal_type;
port_name: port_mode signal_type;
...);
END [ENTITY];
Entity_name, port_name: any word except VHDL reserved word
port_mode: IN, OUT
Signal_type: BIT, INTEGER, etc.
7

Lab For Computer Architecture - Fall 2016

Code Model Entity


Example
A
B

Circuits
Function

Lab For Computer Architecture - Fall 2016

Code Model Architecture


Describes how the circuit should function
Simplified Syntax:

ARCHITECTURE arch_name OF entity_name IS


[architecture declaration part]
BEGIN
architecture_statements_part
END [ARCHITECTURE] [arch_name]
arch_name: any word except VHDL reserved word
[architecture declaration part]: this is optional, declare internal signals
architecture_statements_part: main code to describe circuits function

Lab For Computer Architecture - Fall 2016

Code Model Architecture


Example:

Circuits Function: C = A AND B

10

Lab For Computer Architecture - Fall 2016

Code Model Complete look

11

Lab For Computer Architecture - Fall 2016

Basic Object Types


SIGNAL
To pass value in and out of the circuit and circuit interconnection
All ports of an entity are signals
Not updated its value immediately inside the PROCESS
Declaration syntax:

SIGNAL signal_name: signal_type [range] [:= initial_value];


Example:

Declare with initial value: SIGNAL enable: BIT := 0';


Assignment notation: <=
Example:
12

enable <= '1';


Lab For Computer Architecture - Fall 2016

Basic Object Types


VARIABLE
To present the local information
To be used inside the sequential code (inside the PROCESS)
Its value is updated immediately
Declaration syntax:

VARIABLE var_name: var_type [range] [:= initial_value];


Example:

Declare with initial value: VARIABLE temp: BIT := 0';


Assignment notation: :=
Example:
13

temp<= '1';
Lab For Computer Architecture - Fall 2016

Data Types
Basic data types for the labs:
Package standard: BIT, BIT_VECTOR, BOOLEAN, INTEGER, etc.
Package std_logic_1164: STD_LOGIC, STD_LOGIC_VECTOR
Package numeric_std: UNSIGNED, SIGNED

Examples of declaration:
SIGNAL a,b: BIT_VECTOR(7 downto 0); -- a, b are 8-bits
SIGNAL x,y: STD_LOGIC_VECTOR(15 downto 0); -- x,y are 16-bits
SIGNAL z: STD_LOGIC_VECTOR(1 to 16); -- 16-bits
SIGNAL c: UNSIGNED(7 downto 0 ); -- 8-bits
a <= "11111111"; --or, you can use the keywork "others"
a <= (OTHERS => '1'); -- a = "1111111"
14

Lab For Computer Architecture - Fall 2016

Operators
Assignment operators:
Operator <=: assign a value to a SIGNAL
Operator :=: assign a value to a VARIABLE/CONSTANT

Logical operators:
NOT, AND, NAND, OR, NOR, XOR, XNOR

Arithmetic operators:
Addition(+), Subtraction(-), Multiplication(*), Division(/), etc.
These operators are in the library numeric_std or std_logic_arith (or, the

library numeric_std_unsigned, std_logic_unsigned, std_logic_signed)


15

Lab For Computer Architecture - Fall 2016

Operators
Comparison operators
Equal to(=);not equal to(/=); less than(<);greater than(>);less than or

equal to(<=); greater than or equal to(>=)

Shift operators:
Shift left logic(SLL); shift right logic(SRL); shift left arithmetic(SLA);

shift right arithmetic(SRA); Rotate left(ROL); rotate right(ROR)

Concatenation operator:
Use for grouping objects and values
Notation: &

16

Example: y = x & 001 - if x = 00011, then y = 00011001


Lab For Computer Architecture - Fall 2016

Operators
Examples:
x <= NOT a AND B; --x='a.b
y <= x SLL 2;

-- if x = "0110", y = 1000

z <= x & "00";

-- if x = "0110", z = 011000

n = m;

-- m, n are unsigned,
-- if n = "10", m = "10" then "n=m" is true

Notations:
- : dont care
z : high impedance
17

Lab For Computer Architecture - Fall 2016

Coding Guidelines
No Specific coding guidelines for this lab; however, it is recommended

to follow below basic guidelines:


Meaningful signal/variable names
Each signal declaration in the entity should be in different line
STD_LOGIC/STD_LOGIC_VECTOR should be used in all ports
MSB is always on the left by using the keyword downto:

Example: SIGNAL Sel_Tmp: STD_LOGIC_VECTOR( 7 downto 0)

Using the same name for the project, main entity


Should not use mode BUFFER
Should not use more than one ENTITY-ARCHITECTURE pair in the same file

18

Lab For Computer Architecture - Fall 2016

Next VHDL Overview


Concurrent Code
Sequential Code
FSM template
Component instantiation
Level of abstraction (VHDL styles)
Behavioral style
Data flow style
Structural style

19

Lab For Computer Architecture - Fall 2016

Basic VHDL Overview


Questions?

20

Lab For Computer Architecture - Fall 2016

Warm-up
Using Xilinx ISE in your lab to implement below combinational circuit,

make the testbench and run the simulation


A

Y = (A AND B) OR C

B
C

Similar to the example in the Xilinx ISE Introduction

21

Lab For Computer Architecture - Fall 2016

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