6.

301 Solid State Circuits

With regards to high-frequency amplifiers, or high-speed circuits in general, capacitance is bad news.
One way to think about this is to realize that with high-speed circuits, were often talking about
how to make the voltage at a given node change rapidly:
R
v0
+
v C
!

dv0
That is, we want dt
to be large. What keeps this from happening? Writing KCL:

v ! v0 dv dv v ! v0
=c 0 " 0 =
R dt dt RC

Our options are:

1) Increase v ! v0
2) Decrease R
3) Decrease C

In general, we cant use (1) as a good design strategy because large v ! v0 all the time implies
significant attention between v and v0 . That leaves us often managing the RC product whichever
way we can.

How do we manage the RC product? Minimize R, minimize C, of course. But when there is gain
between various nodes in a circuit, managing capacitance also means that we make sure the Miller
effect doesnt hurt us.

CLASS EXERCISE: Miller Effect

1) Compute the input impedance for the following circuit:

A
6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

2) Simplify your result for the case of A = +1 .

(Workspace)

Theres a mechanical analog to the Miller effect. Suppose you came upon a large block sitting on a
frictionless surface. One way to figure out its mass would be to give it a well-defined push and then
observe its acceleration. I

F M A +
v R
!

F = M !A V = R!I

Now suppose that unbeknownst to you, someone on the other side knew, at all times, what force you
would apply, and used that information to apply a force himself. It would distort your perception of
the mass of the block! R
A

I
F M
F + !G
v
!
2F = M ! A

!1 $ " R %
(1 + G)V = RI ! V = $
# 1 + G '&
F = # M& A I
"2 %

Mass seems smaller! Resistance seems smaller!

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6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

R
A

F GF I
M
+ +G
v
!

(1 ! G ) F = MA
" R %
" M % V =$
# 1 ! G '&
I
F=$
# 1 ! G '&
A

Mass seems negative! Resistance seems negative!

In circuits, the Miller effect can have a significant impact on the bandwidth of our final designs. First,
lets specify our result for capacitors.

vIN (1 ! A )
i=
1
i Cs

A vIN 1
+ =
vIN i (1 ! A ) Cs
!

So if A is negative, our voltage source sees a capacitance that is much larger than C.

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6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

Where has this Miller effect shown up in our circuits?

1) Common Emitter Amplifier

RL C
RS
! RS
A B +
+ vO
VS + !
VS ! r! V! ! gmV! RL
!

Significant negative gain between nodes (A) and (B):

RS
!gm RL +
vO
!
vS +
RL
r!
!

Qualitatively, we can look at this diagram and sense trouble.

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6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

Analytically, the Miller effect shows up in the OCT Calculation:

Amplifier gain magnifies the OCT contribution

2) Cascode Amplifier Stage

The big drawback with the common emitter stage is that we have a capacitance, C , connected
across a large negative gain:

RL
C
RS
!gm RL vi

vS vi

How does a cascode help to mitigate this? By managing the Miller effect!

RL
C 2
C
Q2

C1 B
RS
Q1
+ A
vS
!

Lets find the gain between points (A) and (B)

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6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

Recall that the impedance looking into the emitter of Q2 is ~ 1

RS
C1
+
vS +
! v! r! ! gm v! 1
! gm

C1
RS
!1
+ 1
vS r! gm
!

" 1%
$# !gm i g '&
m

The reason the cascode is a speed improvement is that it separates the two nodes between which
there is significant negative gain. There is no single capacitor that bridges the two nodes.

We actually saw something like this with the A733 video amplifier. A differential half-circuit might
look something like the following (consider the case of no degeneration):
7k!
C
A B C
!100 +
vIN + vo
! !
r! ! gm v! 2.4k! r!

First Stage Second Stage

Page 6
6.301 Solid State Circuits
Recitation 5: Miller Effect
Prof. Joel L. Dawson

Node (A) is the input node, node (B) is the virtual ground, and node (C) is the output. Notice how
here, as with the cascode, we have managed to avoid having a C bridge two nodes between which
there is a high negative gain.

Summary:

1) Reduce Rs as much as possible.

R
+G

Little bit of negative capacitance! Use with care.

Page 7
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6.301 Solid-State Circuits

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