Hierarchical Design and Formal Verification: Experiment No. 04
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dragondignityHierarchical Design and Formal Verification: Experiment No. 04
Uploaded by
dragondignityExperiment No.
04:
Hierarchical Design and Formal Verification
By: Anh Nguyen
Instructor: Ken Choi
ECE 429
Lab Date: 10-11-2017
Due Date: 10-20-2017
Acknowledgment: I acknowledge all of the work (including figures and codes)
belongs to me and/or persons who are referenced.
Signature: Anh Nguyen
I. Introduction
When approaching chipset design, a huge amount of work are need to be done. It is impossible
for a single person to design every single part of the chip. The design need to be divided into many
approachable parts to be completed and put together. This type of design is called Hierarchy design.
II. Theory/Pre-Lab
A simple design using the results we had from the previous lab.
NAND then and INV we give us AND.
A simple 2 input NAND.
III. Implementation
NAND gate layout
I didnt know I also have to include LVS picture for NAND gate. I assured you I passed the LVS
for NAND since otherwise the hierarchy design using NAND for AND gate wont work.
AND gate layout design
LVS results
DRC also passed.
Equivalence checking report
As you can see for 3 different input I think I got the same output in the pictures above. I spend a huge
amount of time with the NETLIST but failed to find anything wrong whatsoever even with 2 different TAs
help.
Is there any other way to design an AND gate than combining an inverter with a NAND gate? Which
one will you prefer?
We can also use
But I will choose to use NAND and INV design, because INV use less transistor and has lower delay than a
NAND gate.
Do the input transitions leading to the propagation delays match your expectations? Why or why not?
No, it does not. For all 3 cases of input from lab 4, I got the same output for some reason. I spend 5
hours looking at the NETLIST try to find an error but failed in doing so. The max rising or falling delay in
the n-transistor should be closer to the output capacitor when it turned on and p-transistor is turned
off.
Is there any relationship between the propagation delays you measured in this lab for the AND gate
and those you measured in Lab 2 for the inverter and in Lab 4 for the NAND gate?
The propagation delay in this lab should be the sum of propagation delay for the INV and NAND gate we
made before. This is because of stage and path effort base on Elmore delay model.
Then AND is the combination of NAND and INV, so it naturally has the combined delay of them.
What is the difference between a schematic and a Verilog model?
A Verilog is code that only implemented the logic you want to implement, but the computer will decide
how to implement it. For example, in this lab, the computer can decide whethere it will use NAND and
INV, or NAND and NAND.
A schematic allows you to implement the logic the way you want it. But it only work for simple logic. For
very complicated logic, it is better to use Verilog.
IV. Conclusions
The lab objectives were completed. I learned how to create a hierarchy design and run stimulation of
the AND gate.