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A multiplexer (MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. It has several data input lines, select lines that are fewer than the number of inputs, and a single output line. The document describes MUX implementations using IC chips 74153 and 74151, including diagrams of 2:1, 4:1, and 8:1 MUXes. It also shows how MUXes can be combined in a tree structure and used to build half and full adders/subtractors as well as implement logic functions.

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71 views4 pages

Web Lab Manual

A multiplexer (MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. It has several data input lines, select lines that are fewer than the number of inputs, and a single output line. The document describes MUX implementations using IC chips 74153 and 74151, including diagrams of 2:1, 4:1, and 8:1 MUXes. It also shows how MUXes can be combined in a tree structure and used to build half and full adders/subtractors as well as implement logic functions.

Uploaded by

Mayank Saini
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIGITAL ELECTRONICS Multiplexer (MUX)

LAB Definition : A multiplexers (MUX) is a device that allows


(17ECL38) digital information from several sources to be routed onto a
single line for transmission over that line to a common
destination.

Lab Instructions 5 Several data input lines


5. Realize • Some select line (less than the no. of input lines)
• (a) Adder & Subtractor using IC 74153. (4:1 MUX) • Single output line
• (b) 3-variable function using IC 74151(8:1MUX). • If there are n data input lines and m select lines, then
2m = n

DE LI 5 MUX with 74151 & 74151 1 DE LI 5 MUX with 74151 & 74151 2

Multiplexer (MUX) Multiplexer (MUX)


Functional Diagram 2 : 1 Multiplexer

S Z
0 I0
1 I1

DE LI 5 MUX with 74151 & 74151 3 DE LI 5 MUX with 74151 & 74151 4
Multiplexer (MUX) Multiplexer (MUX)
4 : 1 Multiplexer 8 : 1 Multiplexer S0 S1 S3 Z

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

S0 S1 Z 1 0 0 I4
0 0 I0
0 1 I1 1 0 1 I5
1 0 I2
1 1 I3 1 1 0 I6

1 1 1 I7

DE LI 5 MUX with 74151 & 74151 5 DE LI 5 MUX with 74151 & 74151 6

Multiplexer (MUX)
Multiplexer Tree Multiplexer (MUX)
• The Multiplexers with more number of inputs can be
obtained by
cascading two or more multiplexers with less number of
inputs.
• Below is a design of 16:1 MUX using 4, 4:1 MUXs :-

DE LI 5 MUX with 74151 & 74151 7 DE LI 5 MUX with 74151 & 74151 8
Multiplexer (MUX) Multiplexer (MUX)

Full Adder Using 74153: -


Half Adder Using 74153
DE LI 5 MUX with 74151 & 74151 9 DE LI 5 MUX with 74151 & 74151 10

Multiplexer (MUX) Multiplexer (MUX)

Half Subtractor Using 74153

DE LI 5 MUX with 74151 & 74151 11 DE LI 5 MUX with 74151 & 74151 12
Multiplexer (MUX)
f(a, b, c, d) = F=A’B’C’D + A’B’CD + A’BC’D’ + AB’CD + ABC’D’ + ABC’D +
Multiplexer (MUX) ABCD’ +ABCD

Implementation Of Logic Functions using Multiplexer

1. F(a, b, c) = a’b’c + ab

A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

DE LI 5 MUX with 74151 & 74151 13 DE LI 5 MUX with 74151 & 74151 14

Multiplexer (MUX)

END

DE LI 5 MUX with 74151 & 74151 15

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