OBSOLET

E PRODUC
DATASHEET
RECOMM T
ENDED RE
PLACEME
ISL98602 NT PART
ISL97652 FN9287
4-Channel Integrated LCD Supply with Dual VCOM Amplifiers Rev 1.00
November 2, 2007

The ISL97652 represents a high power, integrated LCD Features

supply IC targeted at large panel LCD displays. The
ISL97652 integrates a high power, boost converter for AVDD • 8V to 15V input supply
generation, delay switch, regulated VON and VOFF charge • AVDD boost up to 19.5V (OVP threshold), with integrated
pumps, VON slicing circuitry, a buck regulator for logic supply 2.8APEAK FET
generation and dual high power VCOM amplifiers.
• Overvoltage protection (OVP)
Operating at 650kHz or 1.3MHz, the AVDD boost converter • 2A integrated AVDD delay FET, with short circuit protection
features a 2.8A boost FET. A short circuit protected AVDD
delay switch is integrated to provide sequencing of the AVDD • Dual charge pump controllers for VON and VOFF
output. Feedback is taken from the far side of the delay FET • VLOGIC buck with integrated 2.5APEAK FET
for improved regulation and an OVP circuit protects output
• VON slicing
side components. The boost features programmable
soft-start. • Dual high speed VCOM amplifiers
The asynchronous buck converter features an integrated • 650kHz/1.3MHz switching frequency
2.5A FET. It also operates from the 650kHz or 1.3MHz • Integrated sequencing
internal clock and features separate enable and soft-start
control. • UVLO and OTP protection

The dual charge pump controllers used for VON and VOFF • Thermally enhanced 7x7 QFN package
generation uses the full FOSC switching frequency to allow • Pb-free (RoHS compliant)
the use of small output components for board space
efficiency. VON is further processed through an integrated Applications
VON-SLICE circuit for reduced flicker.
• LCD-TVs (up to 40”)
The integrated amplifiers feature high slew-rate and high • Industrial/medical LCD displays
output current capability. They are permanently enabled
when AVIN is present. Pinout
Available in the 48 Ld 7mmx7mm QFN package, the ISL97652
ISL97652 is specified for ambient operation over the (48 LD QFN)
TOP VIEW
-40°C to +85°C temperature range.
47 OGND
48 NEG1

46 OUT2

44 NEG2
45 POS2

42 SWO
43 AVIN

38 SW2
37 SW1
Ordering Information
39 SWI
40 SUI
41 FB

TEMP.
PART NUMBER PART RANGE PACKAGE PKG. POS1 1 36 PGND3
(Note) MARKING (°C) (Pb-Free) DWG. # OUT1 2 35 PGND2
ISL97652IRZ ISL97652IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 VGL 3 34 PGND1
CE 4 33 EN1
ISL97652IRZ-T* ISL97652IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
VFLK 5 32 EN2
ISL97652IRZ-TK* ISL97652IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 VDPM 6 THERMAL 31 VC
PAD
*Please refer to TB347 for details on reel specifications. RE 7 30 SS
NOTE: These Intersil Pb-free plastic packaged products employ VGHM 8 29 DLY2
special Pb-free material sets; molding compounds/die attach materials VGH 9 28 FREQ
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which FBP 10 27 VDC
is RoHS compliant and compatible with both SnPb and Pb-free
GND 11 26 PVIN2
soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free DRVP 12 25 PVIN1
requirements of IPC/JEDEC J STD-020.
SUP 13
DRVN 14
AGND 15
FBN 16
REF 17
DLY1 18
SSB 19
VCB 20
FBB 21
CBOOT 22
SWB1 23
SWB2 24

FN9287 Rev 1.00 Page 1 of 25

November 2, 2007
ISL97652

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Maximum Pin Voltages, All Pins Except Below . . . . . . . -0.3 to 6.5V Thermal Resistance JA (°C/W) JC (°C/W)
SW, SUP, DRVP, DRVN, SUI, SWO, AVIN, POS1, NEG1, OUT1, 7x7 QFN Package (Notes 1, 2) . . . . . . 26 1.5
POS2, NEG2, OUT2, VGL . . . . . . . . . . . . . . . . . . -0.3 to 22V Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
SWI,SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 24V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
SUI . . . . . . . . . . . . . . . . . . . . . . . V(SWI) - 6.5V to V(SWI) +0.3V Power Dissipation
PVIN, SWB, VFLK, VDPM, EN1, EN2, FREQ . . . . . -0.3 to 15.5V TA 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.7W
VGH, VGHM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 36V TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W
TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W
Recommended Operating Conditions Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Input Voltage Range, VIN 8V to 15V
Boost Output Voltage, AVDD up to 19.5V
VON Output Range, VON +15V to +32V
VOFF Output Range, VOFF -15V to -5V
Logic Output Voltage Range, VLOGIC+1.5V to +3.3V
Input Capacitance, CIN2x10µF
Boost Inductor, L1 3.3µH-10µH
Output Capacitance, COUT2x22µF
Buck Inductor, L23.3µH-10µH
Operating Ambient Temperature Range -40°C to +85°C
Operating Junction Temperature Range -40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless
otherwise stated.

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY PINS

PVIN Supply Voltage 8 12 15 V

VSUP Charge Pumps Positive Supply 8 20 V

VGH VON-SLICE Positive Supply 8 30 V

AVIN Op-AmpV Positive Supply 4.5 20 V

PIVIN Quiescent Current into PVIN Enabled, no switching 3 6 mA

Disabled 0.5 5 µA

ISUP VSUP Supply Current Enabled, no switching and 0.5 mA

VPOUT = VSUP

Disabled 5 µA

IAVIN AVIN Supply Current For AVIN range 7 mA

VREF Reference Voltage TA = +25°C 1.252 1.265 1.278 V

1.240 1.265 1.290 V

FOSC Oscillator Frequency for Buck, Boost, VON FREQ = VIN 1100 1300 1500 kHz
and VOFF Functions
FREQ = GND 550 650 750 kHz

AVDD BOOST

IBOOST Boost Switch Peak Current Boost Peak Current limit 2.8 A
EFFBOOST Peak Efficiency See graphs and component 91 %
recommendations

rDS(ON) Switch On Resistance 125 200 m

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November 2, 2007
ISL97652

Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless
otherwise stated. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

VBOOST/VIN Line Regulation VIN = 8V to 12V at ILOAD = 200mA, 0.08 %

see “Typical Performance Curves”
on page 6

VBOOST/IOUT Load Regulation 100mA to 500mA, see “Typical 0.5 %

Performance Curves” on page 6

VFB Boost Feedback Voltage TA = +25°C 1.252 1.265 1.278 V

1.240 1.265 1.290 V

Dmax_boost Boost Maximum Duty Cycle FOSC = 650kHz 90 %

FOSC = 1.3MHz 85 %

Dmin_boost Boost Minimum Duty Cycle FOSC = 650kHz 10 %

FOSC = 1.3MHz 20 %

AVDD DELAY SWITCH

RPD RDS(ON) 180 240 m

SWIMAX Maximum SWI Voltage 21 V

IdelayFET Delay FET RMS Current Limit 1.5 2 A

FETtimeout Delay FET Fault Timeout I(SWO) > IdelayFET 100 µs

Ipull-Down Pull-down Current Applied to FET Gate and 65 µA

SUI

VGATE SUI Voltage When Switch is Fully Switched V(SWI) - 5 V

On

SWILEAK SWI Leakage Current When Disabled VIN = 15V, SWI = 21V, SWO = 0V, 1 µA
EN1 = EN2 = 0V

VDSOK Drain Source Voltage When Boost is Enabled SWI =16.5V 15.7 V
VDSHYS Hysteresis on VDSOK Spec SWI =16.5V 1.4 V

VLOGIC BUCK

IBUCK Buck Switch Current Current limit 2.5 A

EFFBUCK Peak Efficiency See graphs and component 85 %
recommendations

RDS(ON) BK Switch On Resistance 170 250 m

VBUCK/VIN Line Regulation VIN = 8V to 12V at ILOAD = 200mA, 0.05 %

see “Typical Performance Curves”
on page 6

VBUCK/IOUT Load Regulation 200mA to 1000mA, see “Typical 0.1 %

Performance Curves” on page 6

VFBB FBL Regulation Voltage TA = +25°C 1.252 1.265 1.278 V

1.240 1.265 1.290 V

Dmax_buck Buck Maximum Duty Cycle FOSC = 650kHz 90 %

FOSC = 1.3MHz 85 %

Dmin_buck Buck Minimum Duty Cycle FOSC = 650kHz 10 %

FOSC = 1.3MHz 20 %

NEGATIVE (VOFF) CHARGE PUMP

VOFF VOFF Output Voltage Range 1X Charge Pump VSUP + 1.4V 0 V

ILoad_NCP_min External Load Driving Capability VSUP >5V 30 mA

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November 2, 2007
ISL97652

Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless
otherwise stated. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

Ron(DRVN)H High-Side Driver ON Resistance at DRVN I(DRVN) = +60mA 11 

RON(DRVN)L Low-Side Driver ON Resistance at DRVN I(DRVN) = -60mA 10 

Ipu(DRVN)lim Pull-Up Current Limit in DRVN V(DRVN) = 0V to V(SUP) - 0.5V 60 270 mA

Ipd(DRVN)lim Pull-Down Current Limit in DRVN V(DRVN) = 0.36V to V(VSUP) -200 -60 mA

I(DRVN)leak Leakage Current in DRVN V(FBN) < 0 or EN1 = LOW -2 2 µA

VFBN FBN Regulation Voltage TA = +25°C 0.48 0.5 0.52 V

0.47 0.5 0.53 V

D_NCP_max Max Duty Cycle of the Negative Charge 50 %

Pump

Rpd(FBN)off Pull-Down Resistance, Not Active I(FBN) = 500µA 2.5 3.5 4.5 k

POSITIVE (VON) CHARGE PUMP

VON VON Output Voltage Range 2X or 3X charge pump VSUP + 2V 34 V

ILoad_PCP_min External Load Driving Capability 30 mA

Ron(DRVP)H High-Side Driver ON Resistance at DRVP I(DRVP) = +60mA 11 

Ron(DRVP)L Low-Side Driver ON Resistance at DRVP I(DRVP) = -60mA 10 

Ipu(DRVP)lim Pull-Up Current Limit in DRVP V(DRVP) = 0V to V(SUP) - 0.5V 60 270 mA

Ipd(DRVP)lim Pull-Down Current Limit in DRVP V(DRVP) = 0.36V to V(VSUP) -200 -60 mA

I(DRVP)leak Leakage Current in DRVP VFBP > VREF or EN1 or EN2 = low -2 2 µA

VFBP FBP Regulation Voltage TA = +25°C 1.225 1.25 1.275 V

1.22 1.25 1.28 V

D_PCP_max Max Duty Cycle of the Positive Charge Pump 50 %

LOGIC INPUTS

VHI Logic “HIGH” EN1, EN2, VFLK, VDPM 2.0 V

VLO Logic “LOW” EN1, EN2, VFLK, VDPM 0.8 V

IL_pd Logic Pin Pull-Down Current VLOGIC > VLO 25 µA

VON SLICE

VGH VGH Voltage 8 30 V

IVGH VGH Input Current VFLK = 0, RE=33K 300 µA

VFLK = 5V, RE=33K 40 µA

VGL VGL Voltage 3 VGH - 2 V

IVGL VGL Input Current -2 0.1 2 µA

RONVGH VGH to VGH_M On Resistance 15 30 

TDEL DELAY Time CE = 470pF 10 µs

VCOM AMPLIFIERS

Icont Maximum Continuous Current Per Amplifier 50 mA

VSAMP Supply Voltage 4.5 20 V

ISAMP Supply Current per amplifier 3 mA

VOS Offset Voltage 3 20 mV

IB Noninverting Input Bias Current per amplifier 0 150 nA

CMIR Common Mode Input Voltage Range 0 AVIN V

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November 2, 2007
ISL97652

Electrical Specifications VIN = 12V, VBOOST = VSUP = 15V, VON = 25V, VOFF = -8V, over temperature from -40°C to +85°C, unless
otherwise stated. (Continued)

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT

CMRR Common-Mode Rejection Ratio 50 70 dB

PSRR Power Supply Rejection Ratio 70 85 dB

VOH Output Voltage Swing High IOUT(SOURCE) = 5mA AVIN - 50 mV

VOH Output Voltage Swing High IOUT(SOURCE) = 50mA AVIN - 450 mV

VOL Output Voltage Swing Low IOUT(SINK) = 5mA 50 mV

VOL Output Voltage Swing Low IOUT(SINK) = 50mA 450 mV

ISC Output Short Circuit Current per amplifier 300 400 mA

SR Slew Rate 50 V/µs

BW Gain Bandwidth -3dB gain point 30 MHz

FAULT DETECTION THRESHOLDS

OVP Overvoltage Protection Threshold AVDD rising 18.8 19.5 20 V

OVPHYS Overvoltage Protection Threshold Hysteresis 0.8 V

VLOR Undervoltage Lockout Threshold PVIN rising 7.8 8.0 V

VLOF Undervoltage Lockout Threshold PVIN falling 7.4 7.6 V

TOFF Thermal Shut-Down Temperature rising 150 °C

TON Reset after Thermal Shut-Down Temperature falling 100 °C

Vth_AVDD(FB) AVDD Boost Short Detection V(FBFBB) falling less than 1.14 V
Vth_VLOGIC(FB VLOGIC Buck Short Detection V(FBB) falling less than 1.14 V
B)

Vth_POUT(FBP) POUT Charge Pump Short Detection V(FBP) falling less than 1.14 V
Vth_NOUT(FBN) NOUT Charge Pump Short Detection V(FBN) rising more than 0.525 V

TFD Fault Delay Time to Chip Turns Off 64 µs

START-UP SEQUENCING

ISS SS, SSB Current SS, SSB 1.5V 6 µA

IDLY DLY1, DLY2 Current DLY1, DLY2 <1.5V 6 µA

SSTH1 SS, SSB Voltage to Give Max Current Limit 1.27 V

SSTH2 SS, SSB Voltage to Enable Fault Checking 2.05 V

DELTH1 DEL1, DEL2 Voltage to Give Max Current 1.27 V

Limit
DELTH2 DEL1, DEL2 Voltage to Enable Fault 2.05 V
Checking

FN9287 Rev 1.00 Page 5 of 25

November 2, 2007
ISL97652

Typical Performance Curves

100 95

95 90

90 85
EFFICIENCY (%)

EFFICIENCY (%)
80 8V VIN TO 14V VOUT
85 13V VIN TO 14V VOUT
75 13V VIN TO 14V VOUT
80 8V VIN TO 14V VOUT 12V VIN TO 14V VOUT
70
75 12V VIN TO 14V VOUT
65
70
60
65 55
60 50
0 500 1000 1500 2000 0 500 1000 1500
IOUT (mA) IOUT (mA)

FIGURE 1. BOOST EFFICIENCY @ 650kHz FIGURE 2. BOOST EFFICIENCY @ 1.3MHz

0.20 0.20

BOOST LOAD REGULATION (%)

BOOST LOAD REGULATION (%)

0.15 12V VIN TO 14V VOUT 8V VIN TO 14V VOUT

0.15

0.10
0.10
0.05
0.05
0.00
0.00
-0.05
13V VIN TO 14V VOUT 13V VIN TO 14V VOUT
-0.10 -0.05
8V VIN TO 14V VOUT 12V VIN TO 14V VOUT
-0.15 -0.10
0 500 1000 1500 2000 0 500 1000 1500 2000
IOUT (mA) IOUT (mA)

FIGURE 3. BOOST LOAD REGULATION @ 650kHz FIGURE 4. BOOST LOAD REGULATION @ 1.3MHz

0.09
0.08 CH3 = IOUT
BOOST LINE REGULATION (%)

0.07
0.06
0.05
0.04
0.03 fs = 1.3MHz

0.02 fs = 650kHz

0.01 CH4 = AVDD (AC COUPLED)

0.00
8 9 10 11 12 13 14 15 16
VIN (V)

FIGURE 5. BOOST LINE REGULATION FIGURE 6. BOOST TRANSIENT RESPONSE @ 650kHz

FN9287 Rev 1.00 Page 6 of 25

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ISL97652

Typical Performance Curves (Continued)

100
90
CH3 = IOUT
80 8V VIN TO 3.3V VOUT

BUCK EFFICIENCY (%)

70
60 12V VIN TO 3.3V VOUT 13V VIN TO 3.3V VOUT
50
40
30
20
10
CH4 = AVDD (AC COUPLED)
0
0 500 1000 1500 2000
IOUT (mA)
FIGURE 7. BOOST TRANSIENT RESPONSE @ 1.3MHz FIGURE 8. BUCK EFFICIENCY @ 650kHz

90 0

BUCK LOAD REGULATION (%)

85 -0.05 8V VIN TO 3.3V VOUT
BUCK EFFICIENCY (%)

80
-0.1
75
12V VIN TO 3.3V VOUT 8V VIN TO 3.3V VOUT -0.15
70
-0.2
65 12V VIN TO 3.3V VOUT
-0.25
60

55 13V VIN TO 3.3V VOUT -0.3 13V VIN TO 3.3V VOUT

50 -0.35
0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500
IOUT (mA) IOUT (mA)

FIGURE 9. BUCK EFFICIENCY @ 1.3MHz FIGURE 10. BUCK LOAD REGULATION @ 650kHz

-0.05 CH3 = IOUT

BUCK LOAD REGULATION (%)

8V VIN TO 3.3V VOUT

-0.1

-0.15

-0.2
12V VIN TO 3.3V VOUT
-0.25

-0.3

-0.35 13V VIN TO 3.3V VOUT

-0.4 CH4 = VLOGIC (AC COUPLED)

0 500 1000 1500 2000 2500
IOUT (mA)
FIGURE 11. BUCK LOAD REGULATION @ 1.3MHz FIGURE 12. BUCK TRANSIENT RESPONSE @ 650kHz

FN9287 Rev 1.00 Page 7 of 25

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ISL97652

Typical Performance Curves (Continued)

0
CH3 = IOUT
-0.1

VON LOAD REGULATION (%)

-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
CH4 = VLOGIC (AC COUPLED)
-1
0 10 20 30 40 50 60 70
IOUT (mA)

FIGURE 13. BUCK TRANSIENT RESPONSE @ 1.3MHz FIGURE 14. VON LOAD REGULATION

0.2

0.15 CH3 = VFLK

VOFF LOAD REGULATION (%)

0.1

0.05

-0.05
CH4 = Vgh_M
-0.1

-0.15

-0.2
0 5 10 15 20 25 30 35
IOUT (mA)

FIGURE 15. VOFF LOAD REGULATION FIGURE 16. GPM WAVEFORM

INPUT SIGNAL

OUTPUT SIGNAL

FIGURE 17. VCOM RISING SLEW RATE

FN9287 Rev 1.00 Page 8 of 25

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ISL97652

Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1 POS1 Op-amp 1 non-inverting input
2 OUT1 Op-amp 1 output
3 VGL GPM lower supply pin
4 CE GPM delay pin
5 VFLK GPM control pin
6 VDPM GPM enable pin
7 RE GPM output voltage slope adjust pin
8 VGHM GPM output voltage
9 VGH GPM higher supply pin
10 FBP Positive charge pump feedback voltage
11 GND Positive and negative charge pump Ground connection
12 DRVP Positive charge pump driver output pin
13 SUP Positive and negative charge pump supply
14 DRVN Negative charge pump driver output pin
15 AGND Device analog Ground
16 FBN Negative charge pump feedback voltage
17 REF Reference voltage for all internal functions and external VOFF feedback
18 DLY1 Buck and negative charge pump delay pin
19 SSB Buck soft-start pin
20 VCB Buck compensation pin
21 FBB Buck feedback voltage
22 CBOOT Buck boot-strap capacitor
23, 24 SWB1, SWB2 Buck FET source connection
25, 26 PVIN1, PVIN2 Input supply
27 VDC Internal regulated 5V supply - attach external decoupling capacitor
28 FREQ Switching frequency select pin
29 DLY2 Boost and positive charge pump delay pin
30 SS Boost soft-start pin
31 VC Boost compensation pin
32 EN2 Boost and positive charge pump enable
33 EN1 Buck and negative charge pump enable
34 PGND1 Device power GND
35, 36 PGND2, PGND3 Boost FET source connection
37, 38 SW1, SW2 Boost FET drain connection
39 SWI AVDD delay switch source connection
40 SUI AVDD start-up in-rush control
41 FB Boost feedback voltage
42 SWO AVDD delay switch drain connection
43 AVIN VCOM amplifier positive supply pin
44 NEG2 Op-amp 2 inverting input
45 POS2 Op-amp 2 non-inverting input
46 OUT2 Op-amp 2 output
47 OGND Op-amp ground
48 NEG1 Op-amp 1 inverting input

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ISL97652

Block Diagram
SSB VCB FBB FB VC FREQ SS

CBOOT
SW1
- - F/F
+ + SW2
PVIN1 REF OSC S

F/F Q
PVIN2 -
S OSC R
SLOPE
 +
Q COMPENSATION
+
-
R -
+  BOOST CONVERTER PGND2

SWB1 PGND3
FOSC
SUI
SWB2
BUCK CONVERTER
SWI
GATE
CONTROL
PGND1 SWO

UVLO AND THERMAL

AVIN PROTECTION AVIN

POS1 + + POS2
NEG1 - - NEG2

OGND

OUT2
OUT1

DLY1
BIAS AND EN1
DLY2 SEQUENCE
EN2
CONTROL
REF
SUP
VOFF
CHARGE
FOSC DRVN
5V PUMP
PVIN2 CONTROL
REGULATOR GND

+ 0.5V
VDC - FBN
SUP
RE
VON
VON
CE CHARGE
DRVP
SLICE CIRCUIT FOSC PUMP
VDPM CONTROL

+ 1.265V
- FBP

VGH VGHM VGHL VFLK AGND

FN9287 Rev 1.00 Page 10 of 25

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ISL97652

Typical Application Diagram

L1 D1 VMAIN AVDD
VIN C11
CIN 6.8µH COUT
100nF
3 x 10µF 3x
R1
* R3
PVIN1 PVIN2 SW1 10µF
0
FREQ SW2 1x100nF 226k
FB CAVDD
VIN SUP VGL C12 4 x 10µF
CVIN
REF SWI * R2
0.1µF 20k R4 *
R5 CREF SUI
C2* 220nF CSUI
40.2k
0.1µF
SWO
FBN RC
VC
C3* R6
453k 10k
CN SS CSS CC
AVDD VOFF D4 0.1µF 0.1µF 4.7nF
DLY1 CD1
DRVN
0.1µF
R9 COFF DLY2 CD2
D3
100k 4.7µF 0.1µF
CE CE
POS1 10nF

NEG1
R10 COMMON
100k OUT1 RE
BACK-PLANE
VGHM GATE DRIVER
POS2 SUPPLY RE
VON 10k
NEG2 VGH
COMMON
BACK-PLANE OUT2 R7 CON
C4* 232k
AVDD AVIN 4.7µF
CAVIN
FBP
0.1µF 470nF CBOOT
PGND3 R8
TCON BIAS L2 CB SWB1 C5*
C21 PGND2 10k
SWB2 PGND1 D7
6.8µH
D5 CP D6
CB R11
2x10µF * 340 DRVP
0.1µF
AVDD
FBB VFLK
C22 SSB VDPM
EN2
* R12
200
CSSB VCB
0.1µF VDC GND OGND AGND EN1
RCB
10k
CDC
4.7nF CCB 4.7µF

*Optional components.
NOTE: Separate PGND and SGND planes must be used, see PCB layout procedure section.

Applications Information Boost Converter

The ISL97652 provides a complete power solution for TFT The boost converter is a current mode PWM converter
LCD applications. The system consists of one boost converter operating at either 650kHz or 1.3MHz. 650kHz operation
to generate AVDD voltage for column drivers, one buck allows operation down to lower duty cycles. It can operate in
converter to provide voltage to logic circuit in the LCD panel, both discontinuous conduction mode (DCM) at light load or
integrated VON and VOFF charge pump controllers, AVDD when operating duty cycle is lower than the minimum duty
delay FET, VON-SLICE and dual high speed VCOM amplifiers. cycle and continuous mode (CCM). In continuous current
With the high output current capability, this part is ideal for big mode, current flows continuously in the inductor during the
screen LCD TV and monitor panel application. entire switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by:
The integrated boost converter and buck converter operate at
either 650kHz or 1.3MHz which allow the use of multilayer V BOOST 1
------------------------ = ------------- (EQ. 1)
ceramic capacitors and low profile inductor which result in low V IN 1–D
cost, compact and reliable system.
Where D is the duty cycle of the switching MOSFET.

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ISL97652

The boost converter uses a summing amplifier architecture option is selected. The minimum boost duty cycle of the
consisting of gm stages for voltage feedback, current feedback ISL97652 is ~10% for 650kHz and ~20% for 1.3MHz. When
and slope compensation. A comparator looks at the peak the operating duty cycle is lower than the minimum duty cycle,
inductor current cycle by cycle and terminates the PWM cycle the part will not switch in some cycles randomly, which will
if the current limit is reached. cause some LX pulses to be skipped. In this cas, LX pulses are
not consistent any more, but the output voltage (AVDD) is still
An external resistor divider is required to divide the output
regulated by the ratio of R1 and R2. Because some LX pulses
voltage down to the nominal reference voltage. Current drawn
are skipped, the ripple current in the inductor will become
by the resistor network should be limited to maintain the overall
bigger. Under the worst case, the ripple current will be from 0
converter efficiency. The maximum value of the resistor
to the threshold of the current limit. In turn, the bigger ripple
network is limited by the feedback input bias current and the
current will increase the output voltage ripple. Hence, it will
potential for noise being coupled into the feedback pin. A
need more output capacitors to keep the output ripple at the
resistor network in the order of 60k is recommended. The
same level. When the input voltage equals, or is larger than,
boost converter output voltage is determined by the following
the output voltage, the boost converter will stop switching. The
equation:
boost converter is not regulated any more, but the part will still
R1 + R2 be on and other channels are still regulated.
V BOOST = ---------------------  V FB (EQ. 2)
R2
Boost Converter Input Capacitor
The current through the MOSFET is limited to 2.8Apeak. This An input capacitor is used to suppress the voltage ripple
restricts the maximum output current (average) based on the injected into the boost converter. A ceramic capacitor with
following equation: capacitance larger than 10µF is recommended. The voltage
I L V IN rating of input capacitor should be larger than the maximum
I OMAX =  I LMT – --------  --------- (EQ. 3)
input voltage. Some capacitors are recommended in Table 2
 2  VO
for input capacitor.
Where IL is peak to peak inductor ripple current, and is set by:
TABLE 2. BOOST CONVERTER INPUT CAPACITOR
V IN D RECOMMENDATION
I L = ---------  ----- (EQ. 4)
L fS
CAPACITOR SIZE VENDOR PART NUMBER
where fs is the switching frequency 10µF/25V 1210 TDK C3225X7R1E106M
The following table gives typical values (margins are 10µF/25V 1210 Murata GRM32DR61E106K
considered 10%, 3%, 20%, 10% and 15% on VIN, VO, L, fS
and IOMAX):
Boost Inductor
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION The boost inductor is a critical part which influences the output
VIN (V) VO (V) L (µH) fs (MHz) IOMAX (mA) voltage ripple, transient response, and efficiency. Values of
3.3µH to 10µH should be selected to match the internal slope
12 15 6.8 0.65 1890
compensation. The inductor must be able to handle the
12 15 6.8 1.3 1955 following average and peak current:
12 18 6.8 0.65 1500 IO (EQ. 5)
I LAVG = -------------
12 18 6.8 1.3 1590 1–D

8 15 6.8 0.65 1200 I L

I LPK = I LAVG + -------- (EQ. 6)
8 15 6.8 1.3 1275 2

8 18 6.8 0.65 950 Some inductors are recommended in Table 3.

8 18 6.8 1.3 1050 TABLE 3. BOOST INDUCTOR RECOMMENDATION

DIMENSIONS
When operating at the lower frequency option, 650kHz, the INDUCTOR (mm) VENDOR PART NUMBER
potential increase in ripple current in the inductor can be 6.8µH/ 7.3x6.8x3.2 TDK RLF7030T-6R8N3R0
avoided by increasing the inductor by the same factor. This 3APEAK
allows the slope compensation in the boost feedback to remain 6.8µH/ 7.6X7.6X3.0 Sumida CDR7D28MNNP-6R8NC
the same as the 1.3MHz case and this will maintain stability of 2.9APEAK
the converter over the widest operating range. Operation at
5.2µH/ 10x10.1x3.8 Cooper CD1-5R2
650kHz allows boost operation down to lower minimum duty 4.55APEAK Bussmann
cycles, where the output voltage required is closer to the input
voltage than can be achieved when the higher frequency

FN9287 Rev 1.00 Page 12 of 25

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ISL97652

Rectifier Diode (Boost Converter) ringing observed when the load current changes. Reduce
A high-speed diode is necessary due to the high switching excessive ringing by reducing the value of the resistor in series
frequency. Schottky diodes are recommended because of their with the VC pin capacitor.
fast recovery time and low forward voltage. The reverse AVDD Delay Switch
voltage rating of this diode should be higher than the maximum
The ISL97652 integrates a PMOS disconnect switch for the
output voltage. The rectifier diode must meet the output current
AVDD boost output to disconnect VIN from AVDD when the EN2
and peak inductor current requirements. The following table is
input is not selected. When EN2 is taken high, the PMOS FET
some recommendations for boost converter diode.
is turned on to connect power to the display. The CSUI
TABLE 4. BOOST CONVERTER RECTIFIER DIODE capacitor provide soft-start control for the connection of this
RECOMMENDATION switch.
VR/IAVG
The operation of the AVDD delay switch is controlled by
DIODE RATING PACKAGE VENDOR
internal VDSOK and VDSHYS control signals which operate as
SS23 30V/2A SMB Fairchild Semiconductor follows:
SL23 30V/2A SMB Vishay Semiconductor During start-up (or during fault conditions):
VDSOK goes to 1 when V(SWI - SWO) becomes less than
Output Capacitor ~0.5V. This will turn-on the boost function.
The output capacitor supplies the load directly and reduces the VDSOK goes to 0 when VDS_pfet becomes greater than
ripple voltage at the output. Output ripple voltage consists of two ~1.1V. This will turn-off the boost function.
components: the voltage drop due to the inductor ripple current
The threshold voltages have a Vin dependence such that:
flowing through the ESR of output capacitor, and the charging
and discharging of the output capacitor. For Vin1 = 8V: VDSOK goes to 1 occurs at ~0.5V and VDSOK
goes to 0 occurs at ~1.1V.
V O – V IN IO 1 (EQ. 7)
V RIPPLE = I LPK  ESR + ------------------------  --------------------  ---- For Vin1 =18.5V: VDSOK goes to1 occurs at ~1.13V and
V O C AVDD f s VDSOK goes to 0 occurs at ~2.65V.
For low ESR ceramic capacitors, the output ripple is dominated V(SWI - SWO) is the VDS voltage across the internal PFET
by the charging and discharging of the output capacitor. The protection switch. If this voltage exceeds 1.1V for some reason
voltage rating of the output capacitor should be greater than (e.g. under fault conditions or during start-up if VMAIN rises
the maximum output voltage. faster than AVDD) the boost is turned-off to allow the AVDD
(SWO) potential to catch-up with VMAIN (SWI).
Note: Capacitors have a voltage coefficient that makes their
VDSHYS is the VDS hysteresis level;
effective capacitance drop as the voltage across then
increases. COUT in Equation 7 above assumes the effective Once VDSOK goes to 1 the voltage V(SWI - SWO) then needs
value of the capacitor at a particular voltage and not the to exceed 1.1V for VDSOK goes to 0.
manufacturer's stated value, measured at zero volts. During normal operation VDS will be ~Ron_PFET * Iload
(~ 0.18x2 = 0.36V for max AVDD load).
The following table shows some selections of output
If a fault develops on AVDD, which causes VDS to exceed
capacitors.
1.1V, then the boost operation is interrupted by the internal
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION VDSOK goes to 0 signal and fault timers will start to operate
CAPACITOR SIZE VENDOR PART NUMBER while the rising/falling character of AVDD is monitored.
10µF/25V 1210 TDK C3225X7R1E106M AVDD Delay Switch Fault Operation
10µF/25V 1210 Murata GRM32DR61E106K When enabled, the gate of the PFET is pulled down with a
30µA current, turning on the FET switch. The speed of this
Loop Compensation (Boost Converter) turn-on can be controlled by placing a capacitor from SWI to
The boost converter of ISL97652 can be compensated by a SUI. In normal operation the gate (and SUI pin) are pulled
RC network connected from VC pin to ground. CC = 4.7nF and down to 5V below SWI. The AVDD delay switch circuitry
RC = 10k RC network is used in the demo board. A higher constantly monitors both the current in the switch and the
resistor value can be used to lower the transient load change voltage at SWO. If the current exceeds the current limit of 2A,
AVDD overshoot - however, this may be at the expense of the gate of the FET (and also the SUI pin) will be pulled up to
stability to the loop. the correct level to limit the current to 2A. In this mode the
switch acts like a 2A current source. this current cannot be
The stability can be examined by repeatedly changing the load maintained indefinitely due to the power dissipation on chip.
between 100mA and a max level that is likely to be used in the Therefore, three separate fault mechanisms are operated.
system being used. The AVDD voltage should be examined
with an oscilloscope set to AC 100mV/div and the amount of

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ISL97652

1. The SWO output range is constantly monitored and Feedback Resistors

expected to rise if the PFET is in current limit. The rate of The buck converter output voltage is determined by the
rise at SWO can be calculated from the current limit and the
following equation:
capacitance on SWO by using the equation
dV/dt = Ilimit/Cavdd. The SWO voltage range is split into R 11 + R 12
(EQ. 11)
sections of approximately 0.7V such that every time the V LOGIC = ---------------------------  V FBB
R 12
output rises by this amount the circuit detects that the
voltage is rising. Should the circuit remain in current limit for Where R11 and R12 are the feedback resistors of buck
more than 100µs with no such rise taking place the circuit
converter to set the output voltage. Current drawn by the
will fault out. In this scenario, the PFET will immediately
resistor network should be limited to maintain the overall
switch itself off and the rest of the ISL97652 will later fault
out due to the boost voltage at AVDD falling away. converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
2. As well as monitoring any rise in the voltage at SWO, the
potential for noise being coupled into the feedback pin. A
circuit also monitors any falls in this level. If the output falls
by more than a certain amount while it is in current limit the resistor network in the order of 1k is recommended.
circuit will fault out immediately. This amount varies from Buck Converter Input Capacitor
about 1V to about 1.4V depending on the output level
before the fall. In this scenario, the PFET will immediately The capacitor should support the maximum AC RMS current
switch itself off and the rest of the ISL97652 will later fault which happens when D = 0.5 and maximum output current.
out due to the boost voltage falling away.
(EQ. 12)
I ACRMS  C IN  = D   1 – D   IO
3. Once the ISL97652 has successfully sequenced the boost
on and the boost soft-start capacitor has charged up, a third
fault check is also added. After this point if the PFET enters Where Io is the output current of the buck converter. The
current limit for greater than the global timeout of 40µs then following table shows some recommendations for input
the chip will fault out. In this scenario the whole chip will be capacitor.
disabled with the PFET immediately switched off.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION
Buck Converter
CAPACITOR SIZE VENDOR PART NUMBER
The buck converter is the step down converter, which supplies
the current to the logic circuit of the LCD system. The 10µF/16V 1206 TDK C3216X7R1C106M
ISL97652 integrates an 20V N-Channel MOSFET to save cost 10µF/10V 0805 Murata GRM21BR61A106K
and reduce external component count. In the continuous
22µF/16V 1210 Murata C3225X7R1C226M
current mode, the relationship between input voltage and
output voltage is as follows:
Buck Inductor
V LOGIC
---------------------- = D (EQ. 8) A 3.3µH to 10µH inductor is the good choice for the buck
V IN
converter. Besides the inductance, the DC resistance and the
Where D is the duty cycle of the switching MOSFET. Because saturation current are also the factor needed to be considered
D is always less than 1, the output voltage of buck converter is when choosing buck inductor. Low DC resistance can help
lower than input voltage. maintain high efficiency, and the saturation current rating
should be 2.5A. Here are some recommendations for buck
The peak current limit of buck converter is set to 2.5A, which
inductor.
restricts the maximum output current (average) based on the
following equation: TABLE 7. BUCK INDUCTOR RECOMMENDATION

I OMAX = 2.5A – I PP (EQ. 9) DIMENSIONS

INDUCTOR (mm) VENDOR PART NUMBER
Where IPP is the ripple current in the buck inductor as the 4.7µH/ 5.7x5.0x4.7 Murata LQH55DN4R7M01K
following equation: 2.7APEAK
V LOGIC 6.8µH/ 7.3x6.8x3.2 TDK RLF7030T-6R8M2R8
I PP = ----------------------   1 – D  (EQ. 10)
L  fs 3APEAK

10µH/ 12.95x9.4x3.0 Coilcraft DO3308P-103

Where L is the buck inductor, fs is the switching frequency.
2.4APEAK

Rectifier Diode (Buck Converter)

A Schottky diode is recommended due to fast recovery and low
forward voltage. The reverse voltage rating should be higher than

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ISL97652

the maximum input voltage. The peak current rating is 2A, and the Regulated Charge Pump Controllers (VON and VOFF)
average current should be as the following equation, The ISL97652 includes 2 independent charge pumps (see
I AVG =  1 – D *I o (EQ. 13) charge pump block and connection diagram). The negative
charge pump inverters the VSUP voltage and provides a
Where Io is the output current of buck converter. The following regulated negative output voltage. The positive charge pump
table shows some diode recommended. doubles or triples the VSUP voltage and provided a regulated
positive output voltage. The regulation of both the negative and
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
positive charge pumps is generated by internal comparator
VR/IAVG that senses the output voltage and compares it with the
DIODE RATING PACKAGE VENDOR
internal reference.
PMEG2020EJ 20V/2A SOD323F Philips
Semiconductors The pumps use pulse width modulation to adjust the pump
SS22 20V/2A SMB Fairchild period, depending on the load present. The pumps can provide
Semiconductor 30mA for VOFF and 20mA for VON.

Positive Charge Pump Design Consideration

Output Capacitor (Buck Converter)
The positive charge pump can drive multiple stages for 2X/ 3X
Four 10µF or two 22µF ceramic capacitors are recommended step up ratios, or higher. Internal switches (M1 and M2) drive
for this part. The overshoot and undershoot will be reduced with external steering diodes via the pump capacitor CP. Figure 18A
more capacitance, but the recovery time will be longer. shows 2X configuration and Figure 18B shows 3X
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION configuration. The output voltage is divided by feedback
resistors R7 and R8, which is then compared to the internal
CAPACITOR SIZE VENDOR PART NUMBER
reference via comparator A1. The maximum VON charge pump
10µF/6.3V 0805 TDK C2012X5R0J106M current can be estimated from the following equations
10µF/6.3V 0805 Murata GRM21BR60J106K assuming a 50% switching duty:

22µF/6.3V 1210 TDK C3216X5R0J226M I MAX  2x   min of 50mA or

100µF/6.3V 1206 Murata GRM31CR60J107M 2  V SUP – 2  V DIODE  2  I MAX  – V  V ON 

----------------------------------------------------------------------------------------------------------------------  0.95A
 2   R ONH + R ONL  
PI Loop Compensation (Buck Converter) (EQ. 14)
The buck converter of ISL97652 can be compensated by a RC I MAX  3x   min of 50mA or
network connected from VCB pin to ground. CCB = 4.7nF and
3  V SUP – 4  V DIODE  2  I MAX  – V  V ON 
RCB = 10k RC network is used in the demo board. The larger ----------------------------------------------------------------------------------------------------------------------  0.95A
4   R ONH + R ONL 
value resistor can lower the transient overshoot, however, at
the expense of stability of the loop.

The stability can be optimized in a similar manner to that

described in the section on "PI Loop Compensation (Boost
Converter)”.

Bootstrap Capacitor (CB)

This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is formed
by an internal diode and capacitor combination. A 470nF is
recommended for ISL97652. A low value capacitor can lead to
overcharging and in turn damage the part.

If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if VIN-VBUCK <1.5V, the internal MOSFET pull-up
device may be unable to turn-on until VLOGIC falls. Hence,
there is a minimum load requirement in this case. The
minimum load can be adjusted by the feedback resistors
to FBB.

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ISL97652

C4
VDC VSUP 100pF
A2
FAULT
C5 R8
1.14V 2.2nF 10k
FBP

A1 R7
1.265V 232k

FOSC
STOP
M2 VSUP

CLK CP
D6 D7
0.1µF
DRVP
VON (30V)
CON
1µF
PWM
EN CONTROL M1

GND

FIGURE 18A. VON FUNCTION DIAGRAM (VOLTAGE DOUBLER)

VSUP

CP
D6 D7 D6’ D7’
0.1µF
DRVP VON (30V)
CON
1µF CON’
CP’
1µF
0.1µF

FIGURE 18B. VOLTAGE TRIPLER

FIGURE 18.

In voltage doubler configuration, the maximum VON is as given by the following equation:
V ON_MAX(2x) = 2   V SUP – V DIODE  – 2  I OUT   R ONH + R ONL 
(EQ. 15)

For Voltage Tripler using additional external diodes and capacitors (Figure 18B):
VON_MAX(3x) = 3  V SUP – 4  V DIODE – 2  I OUT   R ONH + RONL  (EQ. 16)

VON output voltage is determined by the following equation:

R7
V ON = V FBP   1 + -------- (EQ. 17)
 R8

Negative Charge Pump Design Consideration

The negative charge pump consists of an internal switcher M1,
M2 which drives external steering diodes Dx and Dx via a
pump capacitor (CN) to generate the negative VOFF supply. An
internal comparator (A1) senses the feedback voltage on FBN
and turns on M1 for a period up to half a CLK period to
maintain V(FBN) in regulated operation at 0.5V. External
feedback resistor R5 is referenced to VREF.

FN9287 Rev 1.00 Page 16 of 25

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ISL97652

VREF C3
VDC VSUP 100pF
A2
FAULT
C2 R5
0.53V 820pF 40.2k
FBN

A1 R6
0.5V 453k

FOSC
STOP
M2
CLK CN
0.1µF D4
DRVN
VOFF (-8V)

D3 COFF
1µF
PWM
EN CONTROL M1

GND

FIGURE 19. NEGATIVE CHARGE PUMP BLOCK DIAGRAM

The maximum VOFF output voltage of a single stage charge pump is:
V OFF_MAX  2x  = – V SUP + V DIODE + 2  I OUT   R ON  NOUT H + R ON  NOUT L  (EQ. 18)

R5 and R6 in the Typical Application Diagram determine VOFF Vmain (without the boost running) is large enough to satisfy the
output voltage. regulated VOFF supply.
R6 R6
V OFF = V FBN   1 + -------- – V REF   -------- (EQ. 19) Improving Charge Pump Noise Immunity
 R5  R5
Depending on PCB layout and environment, noise pick-up at
Charge Pump Supply the FBP and FBN inputs, which may degrade load regulation
The magnitude of the SUP supply will determine the charge performance, can be reduced by the inclusion of capacitors
pump diode configuration; whether x2 or x3 for the positive across the feedback resistors (e.g. in the Application Diagram,
charge pump or x1 or x2 for the negative charge pump. C4 and C5 for the positive charge pump).
Set R7 • C4 = R8 • C5 with C4 ~ 100pF.
An independent charge pump supply pin 13 (SUP) is provided
and this may be connected to Vin, Vmain, AVDD or some other VON-SLICE Circuit Operation
suitable supply. The Von slice circuit functions as a three way multiplexer,
switching VGHM between ground, VGL and VGH (typ 15-30V).
Note that if AVDD is chosen for the SUP supply, then a
Voltage selection is provided by digital inputs VDPM (enable)
potential fault-like interaction with the supply sequencing and
and VFLK (control). HIGH to LOW delay and slew control is
fault checking is present; when EN1 goes high (with EN2 low),
provided by external components on pins CE and RE
fault checking on the VOFF charge pump is started by the
respectively. The block diagram of the VON-SLICE circuit is
voltage ramp on DEL1. If this pin reaches ~1.9V before VOFF
shown in Figure 3.
is within 90% of it's regulation voltage then the buck converter
(Tcon bias) and Voff will be continually re-started. This When VDPM is LOW, the block is disabled and VGHM is
condition will arise if the SUP supply has not been activated by grounded.
EN2 going high before DEL1 has reached 1.9V. One solution
When VDPM is HIGH, VGHM is determined by VFLK; when
would be to increase the capacitance on DEL1 to overlap
VFLK goes LOW, there is a delay controlled by the capacitor
enough in time with the EN2 going high. This does have the
attached to the CE pin, following which VGHM is driven to
disadvantage of lengthening the fault detection time of the
VGL, with a slew rate controlled by the resistor attached to the
VOFF charge pump under true fault conditions and it also
RE pin. Note that VGL is used only as a reference voltage for
lengthens the initial VOFF turn-on time. Another solution would
an amplifier, thus does not have to source or sink a significant
be to supply SUP from Vmain as long as the magnitude of
DC current. When VFLK goes HIGH, VGHM is driven HIGH at

FN9287 Rev 1.00 Page 17 of 25

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ISL97652

a rate primarily controlled by the P1 switch resistance capacitor to VREF. This creates a delay, equal to CE*21300.
(RONVGH) and the external capacitive load. For example, the delay time is ~10µs for 470pF CE capacitor.
At this point, VGHM begins to slew down from VGH to VGL.
VGHM HIGH to LOW transitions are more complex; take the
The slew current is equal to Isl = 300/(RE+5k), and the dv/dt
case where the block is already enabled (VDPM is HIGH).
slew rate is Isl/Cload.
When VFLK is HIGH, pin CE is grounded. On the falling edge
of VFLK, a current is passed into pin CE to charge an external where Cload is the load capacitance applied to VGHM.

VGH

VGHM

VDPM

VGL VGL

x248
x248
VREF

RE

60µA

CE

CONTROL
VFLK AND TIMING

FIGURE 20. VON-SLICE BLOCK DIAGRAM

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ISL97652

VGH

VGHM

SLOPE CONTROLLED
VGL BY RE AND LOAD
CAPACITANCE

0 t

VFLK

0 t

TCE DELAY TIME CONTROLLED BY CE

~1.94V

CE
~1.265V

0 t

FIGURE 21. VON-SLICE TIMING WAVEFORM

High Performance VCOM Amplifiers reached, the negative charge pump will begin. Removing the
The integrated high performance amplifiers are designed to DLY1 capacitor will cause the negative charge pump to start
drive the VCOM plane in TFT-LCD displays. Under normal immediately once the buck regulator reaches 90% of the target
operational conditions, the amplifiers are permanently enabled value. The delay time and soft-start times are determined using
when the AVIN supply is present. Under fault conditions and the following equations:
with EN1 active, the temperature shut-down (TOFF exceeded) V DL1
T DLY1 = C DL1  -------------- (EQ. 20)
will disable the amplifiers until the temperature drops to TON. I DL1
Temperature shut-down of the amplifiers is disabled if EN1 is
V SSB
disabled. T SSB = C SSB  --------------- (EQ. 21)
I SSB
The amplifiers integrated in to the ISL97652 feature high
output current of 50mA minimum and high slew rate of 50V/µs. The EN2 pin is used to control the boost and positive charge
Both inputs and outputs have rail-to-rail capability. pump circuits.Note that EN2 is ignored until the buck converter
Start-Up Sequence Control has reached 90% of it's target value. When taken high, the
internal PFET is turned on to connect the input to the AVDD
The ISL97652 features extensive start-up sequence control
output. A capacitor connected to SUI provides control over the
options. Two enable pins and two delay control pins are used
soft connect to limit inrush current. Next, the boost converter
to set the start-up sequence.
starts to operate. The soft-start time for the boost is set using
The EN1 enable pin controls the buck regulator and negative the capacitor tied to the SS pin. Once the output reaches 90%
charge pump controller. When EN1 goes H, the internal 5.3V of the target value, the DLY2 timer starts. Once completed, the
regulator starts up. Once the regulator output on pin 27 (VDC) positive VON charge pump starts to operate. If CDL2 is not
exceeds it's UVLO threshold, the REF pin starts to charge up present, the VON charge pump will start immediately once the
to the normal output level. Once REF is within 15% of it's final boost is in regulation. The delay time is determined using the
value, the buck regulator will start to operate. Note that if VREF following equation:
moves more than 15% from it's target value, all major functions V DL2
will be disabled until REF returns to it's normal range. This T DLY2 = C DL2  -------------- (EQ. 22)
I DL2
involves the chip going through the normal start-up sequence
from buck start-up onwards, depending on the state of the V SS
enable signals EN1, EN2. The soft-start time is set using the T SS = C SS  ----------- (EQ. 23)
I SS
capacitor connected to SSB. Once the output reaches 90% the
DLY1 capacitor begins to charge. Once the threshold is

FN9287 Rev 1.00 Page 19 of 25

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ISL97652

Variations on the start-up sequence can be seen in Figures 22, The Gate pulse modulator is enabled when both of the
23 and 24. following conditions are met:

• VDPM is H
• VON is over 90% of it's target value.

TSSB DLY2

EN1

DLY1

EN2

VTCON
TSS

VOFF

VMAIN VIN - DIODE

VIN - 2 x DIODE VMAIN - 2 x DIODE

VON

VIN - DIODE
AVDD

FIGURE 22. TIMING DIAGRAM 1

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ISL97652

TSSB

DLY2
EN1
DLY1

EN2
TSS

VTCON

VOFF

VIN - DIODE

VMAIN
VMAIN - 2 x DIODE
VIN - 2 x DIODE
VON

VIN - DIODE
AVDD

FIGURE 23. TIMING DIAGRAM 2

FN9287 Rev 1.00 Page 21 of 25

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ISL97652

EN2

DLY2
VDPM

VIN - DIODE

VMAIN VIN - DIODE OR

VMAIN DIODE

VON

AVDD

VFLK

VGHM

FIGURE 24. TIMING DIAGRAM 3

Switching Frequency Control Fault Detection

The ISL97652 can operate at either 650kHz or 1.3MHz The ISL97652 includes extensive fault handling circuitry, which
depending on the state of the FREQ pin. When connected to interacts with the start-up sequence circuitry if a fault is
GND, 650kHz is selected. When connected to VIN, 1.3MHz is detected.
selected. Higher frequencies enable the selection of smaller
During normal operation, if EN1 goes L, all major functions are
inductors and capacitors. Lower frequencies allow closer
disabled immediately, including the 5V regulator. If EN2 goes
input/output ratios to be supported. The charge pump circuits
L, but EN1 remains H, boost, VON and GPM are disabled
switch at half the frequency selected.
immediately. When EN1 and/or EN2 return H, the start-up
Undervoltage Lockout sequence restarts from the appropriate point.
The integrated undervoltage lockout circuit is designed to If the over-temperature threshold (+150°C nominal) is
power down the TFT-LCD if the input voltage falls below a exceeded, or if VIN drops below the specified lower UVLO limit,
preset threshold. The ISL97652 will not start if the input voltage all major functions are disabled immediately, excluding the
is below the UVLO threshold. 5.3V regulator. If/when the temperature drops below +100°C,
Over-Temperature Protection or VIN returns to a level above the upper UVLO threshold the
start-up sequence will re-commence by enabling REF.
An internal temperature sensor continuously monitors the die
temperature. In the event that the die temperature exceeds the Timed “Faults”
thermal trip point of +150°C, the device will shut down. The four ramp voltages, SSB, SS, DEL1 and DEL2 all ramp
Operation with die temperatures between +125°C and 150°C linearly from 0V to approximately 2.7V, where they are
can be tolerated for short periods of time, however, in order to soft-clamped. The 2V thresholds of each are used to enable
maximize the operating life of the IC, it is recommended that timed fault checking on related blocks. Therefore, external
the effective continuous operating junction temperature of the capacitor values should be chosen such that all major outputs
die should not exceed +125°C. are in regulation by the time this threshold is reached. For

FN9287 Rev 1.00 Page 22 of 25

November 2, 2007
ISL97652

example, SSB controls step-down regulator fault checking, SW1,2 [a single wide track] to L1/D1, SWB1,2 [a single wide
DEL1 controls VOFF fault checking, SS controls step-up track] to L2/D5.)
regulator and PFET fault checking, DEL2 controls VON and
Reserve the bottom (or an intermediate layer) for the signal
GPM fault checking. If a fault on any of the major blocks is
ground plane (SGND) and signal routing. It is recommended
detected continuously for a predetermined time interval
that all feedback inputs and any other sensitive tracks are
(currently set to 63µs), when fault checking is enabled for that
routed to the SGND layer using a VIAs as close to the chip as
function, the fault latch will be set. This causes all major
possible. This prevents unwanted interference pick-up and
functions to be disabled immediately, including the 5.3V
allows the supply smoothing capacitors to be places as close
regulator. Once VDC falls below its internal UVLO limit
to the chip as possible.
(typically 3.6V), the FAULT latch is reset. This will initiate an
automatic restart. If the fault has been cleared, the restart will (Route the following tracks on the SGND (bottom or
be successful; if the fault persists, the FAULT latch will again intermediate) metal layer: FB, FBB, FBP, FBN, POS1,2, )
be set, and the cycle will repeat itself.
Star Ground
Buck, boost and VON circuits have fault thresholds at 90% of A star ground system is where a number of different grounds
target values. (e.g. PGND, SGND) come together at a single location which
The VOFF fault threshold is set at 125mV above the 0.5V then becomes the reference ground point for the system as a
regulation point. whole. Star grounding ensures minimum interference between
different functions in a system.
GPM fault detection is designed to detect a short circuit on the
output, by monitoring whether VGHM fails to pull up to VGH on Practically, it is difficult to achieve an ideal (single location)
two consecutive FOSC clock periods. ground point due to the physical dimensions of the chip,
smoothing capacitors and track routing, however, the exposed
The AVDD PFET also has fault checking, which will protect the die plate and the area immediately next to the PGND1,2,3 pins
FET in the event of an output short circuit. is defined as the star ground for this chip.
Note that the VCOM amplifiers are independently biased, and The negative smoothing capacitor terminals of: Cout, CB and
are enabled at all times, except if an over-temperature fault is CIN must be located as close as possible to the PGND1,2,3
detected. If this behavior is not desired, then there is an option pins. The smoothing capacitors for VIN, Cout and CB come as
to power the VCOM amplifiers from AVDD, which will keep them a block of three or four capacitors with (usually) one small
disabled until the boost is enabled. capacitor whose role is to reduce the total effective ESR of the
Note also that it is possible to prevent timed fault checking on capacitors. It is recommended that the small capacitor and at
any or all of the major functions, simply by externally clamping least one of the large capacitors from each capacitor block is
SSB, SS, DEL1 and/or DEL2 to a voltage between 1.3V and placed as physically close to the chip PGND pins as possible.
2V. The other capacitors from each block can be placed a little
further away, if necessary.
PCB Layout Procedure
Exposed Die plate connection
To ensure the user gets the best chip performance with
minimum amount of PCB rework in the development phase, The exposed die plate connection to the underside of the chip
the following PCB layout procedure is strongly recommended. must directly connect the PGNDs (pins 34, 35, 36) and AGND
(pin 15) with an equivalent area of metal. The other ground
PCB metal layers pins (amplifier OGND and charge pump GND pins may also be
Reserve the top PCB metal layer for direct power ground connected to the die plate.
(PGND) connections to the supply pins and switching outputs
The exposed die plate connection must have multiple VIAs
(buck/boost/charge-pumps). The goal is to ensure there are no
(use a 4x4 array) connecting the top metal PGND layer to the
VIAS in the boost and buck paths to the smoothing capacitors.
bottom SGND metal layer. The bottom SGND metal area
The top layer may also be used for general routing of non-
around the VIA array should be maximized in order to keep the
sensitive tracks as long as this does not compromise the
thermal resistance of the chip and PCB system as low as
supply track widths which should be as wide as possible.
possible. This will optimise operation at high currents or in high
Note that using VIAs in series with smoothing capacitors (even ambient temperature applications.
if implemented as multiply parallel VIAs) increases the effective
Order of component placement
high frequency ESR of the capacitors and WILL cause
degraded system operation. The order of component placement should be as follows. This
procedure minimizes the high current PGND and supply track
(Route the following tracks on the PGND (top) metal layer: impedance to the chip pins.
PGND1,2,3 [a single wide track] to CIN, Cout and CB, D5.

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November 2, 2007
ISL97652

1). Cout, Cin, CB: get these components as close to

PGND1,2,3 as possible and use wide tracks on the top
PGND layer with no vias.

2). L1, D1, L2, D5: get these components as close to the
chip pins as possible (having observed 1/) and use wide
tracks on the top PGND layer with no vias.

3). Feedback resistor networks connected to FB, FBB, FBP,

FBN, POS1,2: keep tracks as short as possible (having first
observed 1/ and 2/). Routing on the SGND layer should be
used. Avoid routing this tracks under switching tracks on the
top surface.

4). All other components: keep all switching output tracks

(SW1,2, SWB1,2, CBOOT, DRVP, DRVN, VGHM, VFLK) on
the PGND layer shielded from adjacent tracks.

Evaluation PCB
A two layer evaluation PCB is available which follows the
above procedure and may be useful as a reference to guide
the PCB layout engineer. For example, the smoothing
capacitor positive rail to PVin does contain vias in series;
however, a small capacitor has been used directly at the
PVin pins which overcomes the ESR objection.

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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN9287 Rev 1.00 Page 24 of 25

November 2, 2007
ISL97652

Package Outline Drawing

L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06

4X 5.5
7.00 A
B 44X 0.50 6
37 48 PIN #1 INDEX AREA
6
PIN 1 36 1
INDEX AREA

7.00
4. 30 ± 0 . 15

25 12
(4X) 0.15
24 13
0.10 M C A B
TOP VIEW 48X 0 . 40± 0 . 1
4 0.23 +0.07 / -0.05

BOTTOM VIEW

SEE DETAIL "X"

0.10 C C
0 . 90 ± 0 . 1 BASE PLANE
( 6 . 80 TYP )
SEATING PLANE
0.08 C
( 4 . 30 ) SIDE VIEW

( 44X 0 . 5 )

C 0 . 2 REF 5
( 48X 0 . 23 )
( 48X 0 . 60 ) 0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.

FN9287 Rev 1.00 Page 25 of 25

November 2, 2007