NOT RECOMMENDED FOR NEW DESIGNS DATASHEET

POSSIBLE SUBSTITUTE PRODUCT

ISL6423B
ISL6423 FN9191
Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Rev 2.00
Advanced Satellite Set-Top Box Designs DiSEqC 2.0 Compatible Dec 5, 2008

The ISL6423 is a highly integrated voltage regulator and Features

interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB) • Single Chip Power solution
modules to the low noise blocks (LNBs) of single antenna - Operation for 1-Tuner/1-Dish Applications
ports. The device consists of a current-mode boost PWM - Integrated DC/DC Converter and I2C Interface
and a low-noise linear regulator along with the circuitry • Switch-Mode Power Converter for Lowest Dissipation
required for 22kHz tone generation, modulation and I2C - Boost PWM with > 92% Efficiency
device interface. The device makes the total LNB supply - Selectable 13.3V or 18.3V Outputs
design simple, efficient and compact with low external - Digital Cable Length Compensation (1V)
component count. - I2C and Pin Controllable Output
The current mode boost converter provides the linear • Output Back Bias Capability of 28V
regulator with input voltage that is set to the final output
• I2C Compatible Interface for Remote Device Control
voltages, plus typically 0.8V to insure minimum power
dissipation across the linear regulator. This maintains • Registered Slave Address 0001 00XX
constant voltage drop across the linear pass element while • 2.5V/3.3V/5V Logic Compatible
permitting adequate voltage range for tone injection.
• External Pin to Toggle between V & H Polarization
The final regulated output voltage is available at output
• Built-In Tone Oscillator Factory Trimmed to 22kHz
terminals to support the operation of an antenna port for
- Facilitates DiSEqC (EUTELSAT) Encoding
single tuners. The outputs for each PWM can be controlled
- External Modulation Input
in two ways, full control from I2C using the VTOP and VBOT
bits or set the I2C to the lower range (i.e., 13.3V/14.3V) and • Internal Over-Temperature Protection and Diagnostics
switch to higher range (i.e., 18.3V/19.3V) with the SELVTOP
• Internal OV, UV, Overload and Overtemp Flags
pin. All the functions on this IC are controlled via the I2C bus (Visible on I2C)
by writing 8 bits words onto the System Registers (SR). The
same register can be read back, and five I2C bits will report • FLT signal
the diagnostic status. Separate enable command sent on the • LNB Short-Circuit Protection and Diagnostics
I2C bus provides for standby mode control for the PWM and
• QFN, HTSSOP Packages
linear combination, disabling the output and forcing a shutdown
mode. The output channel is capable of providing 750mA of • Pb-Free Plus Anneal Available (RoHS Compliant)
continuous current. The overcurrent limit can be digitally
programmed to four levels. Applications
The External modulation input EXTM can accept a • LNB Power Supply and Control for Satellite Set-Top Box
modulated DiSEqC command and transfer it symmetrically
to the output. Alternatively the EXTM pin can be used to Ordering Information
modulate the continuous internal tone. TEMP.
PART NUMBER PART RANGE PACKAGE PKG.
The FLT pin serves as an interrupt for the processor when (Note) MARKING (°C) (Pb-Free) DWG. #
an over temperature fault condition is detected by the LNB
controller. The nature of the fault can be read of the I2C ISL6423ERZ 6423ERZ -20 to +85 24 Ld 4x4 QFN L24.4x4D
registers. ISL6423ERZ-T 6423ERZ -20 to +85 24 Ld 4x4 QFN L24.4x4D
(Tape & Reel)

ISL6423EVEZ ISL6423EVEZ -20 to +85 28 Ld HTSSOP M28.173B

ISL6423EVEZ-T ISL6423EVEZ -20 to +85 28 Ld HTSSOP M28.173B

(Tape & Reel)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN9191 Rev 2.00 Page 1 of 16

Dec 5, 2008
ISL6423

Pinouts
ISL6423 (HTSSOP)
TOP VIEW

VCC 1 28 CPSWIN
NC 2 27 CPSWOUT
FLT 3 26 CPVOUT
NC 4 25 EXTM
SGND 5 24 SDA
TCAP 6 23 SCL
ADDR0 7 22 TDOUT
ADDR1 8 21 TDIN
BYPASS 9 20 VO
PGND 10 19 NC
GATE 11 18 NC
VSW 12 17 AGND
NC 13 16 SELVTOP
CS 14 15 TXT

ISL6423 (QFN)
TOP VIEW
CPSWOUT

CPVOUT
CPSWIN
VCC
FLT
NC

24 23 22 21 20 19

SGND 1 18 EXTM

TCAP 2 17 SDA

ADDR0 3 16 SCL

ADDR1 4 15 TDOUT

BYPASS 5 14 TDIN

PGND 6 13 VO

7 8 9 10 11 12
SELVTOP

AGND
GATE

VSW

TXT
CS

FN9191 Rev 2.00 Page 2 of 16

Dec 5, 2008
Dec 5, 2008
FN9191 Rev 2.00

Block Diagram

ISL6423
11 17 16 3 4 23

OLF/BCF
OVERCURRENT

ADDR1
ADDR0

FLT
SDA

SCL
COUNTER
PROTECTION

SELVTOP
LOGIC SCHEME 1 DCL

OUVF
PWM OC1
LOGIC
7 GATE
Q CLK1
S
SDA SCL ADDR0 OUVF
ADDR1
PGND ISELL&H THERMAL
6 OLF/BCF OTF SHUTDOWN
EN
I2C
ENT TTH
INTERFACE
CS ILIM1 - DCL

+
AMP VTOP VBOT
CS
9 
SLOPE CLK1
OSC.
COMPENSATION BAND GAP
REF VOLTAGE
TDOUT BGV
15 DIV &
WAVE SHAPING
TXT -
+
TONE REF
DECODER VOLTAGE
TTH ADJ1
VREF1 INT
TDIN
14 TONE
TONE
INJ
CKT
VSW
8

MSEL1
VO
13
+
-
AGND
12
EXT TONE CKT

VCC ON CHIP
22 LINEAR

UVLO
SGND POR ENT1
1 SOFT-START

CPSWOUT
INT 5V
BYPASS

CPSWIN
CHARGE PUMP
EXTM
Page 3 of 16

SOFT-START
TCAP
TXT

EN1/EN2 CPVOUT

NOTE: 5 10 2 18 20 21 19

1. Pinouts shown are for the QFN package.

Dec 5, 2008
FN9191 Rev 2.00

Typical Application Schematic QFN

ISL6423
VIN

RTN

0
FLT BAR

EXTM
C29 R11 100
1n C25 47n SDA
C24
R12 100
1µF 0 SCL
L4 220µH
1 2
0

24
23
22
21
20
19
C15 0.22µF
D6

CPVOUT
SGND
FLT
VCC
CPSWIN
CPSWOUT
CMS06 R7 15
VLNB
1 18 C28 R23
C27 0.22µF SGND EXTM 0.1µF 10k
2 17
TCAP SDA
3 16 M6
ADDR0 U2 SCL
4 15 NDS356AP
ADDR1 ISL6423ER TDOUT
C23 C26 1µF 5 14
0 BYPASS TDIN D8
R10 6 13 R24
56µF PGND VO 1.5KE24

SELVTOP
18 4.7k

AGND
GATE
0

VSW

TXT
R13 4.7k

CS
0 Q4
C16 RTN
1
2
3

10n 2N2222A

7
8
9
10

12
11
R22
2 TPC6002 47k
Q2 R9
L5 470
TXT
15µH
R8 C21 TDOUT
0.1 100pF
6
5
4

1
SELVTOP
D7 CMS06
0 0

D5 L6 4.7µH
1 2 NOTE : SDA and SCL require pull up to the required logic level.
CMS06 C22 C18 C19 C20
56µF
Page 4 of 16

10µF 10µF 10µF

0 0 0 0
ISL6423

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V Thermal Resistance (Typical, Notes 2, 3) JA (°C/W) JC (°C/W)
Logic Input Voltage Range QFN Package. . . . . . . . . . . . . . . . . . . . 38 4.5
(SDA, SCL, ENT, DSQIN 1 and 2, SEL18V 1 and 2) . . -0.5V to 7V TSSOP Package . . . . . . . . . . . . . . . . . 35 2.5
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -40°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . -20°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.

Electrical Specifications VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN = H, VTOP
VBOT = L, ENT = L, DCL = L, Iout = 12mA, unless otherwise noted. See software description section for I2C
access to the system.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range 8 12 14 V

Standby Supply Current EN = L - 1.5 3.0 mA

Supply Current IIN EN = VTOP = VBOT = ENT = H, No Load - 4.0 8.0 mA

UNDERVOLTAGE LOCKOUT

Start Threshold 7.5 - 7.95 V

Stop Threshold 7.0 - 7.6 V

Start to Stop Hysteresis 350 400 500 mV

SOFT-START

COMP Rise Time (Note 5) (Note 5) - 8196 - Cycles

Output Voltage (Note 5) VO1 (Refer to Table 1) 13.04 13.3 13.56 V

VO1 (Refer to Table 1) 14.02 14.3 14.58 V

VO1 (Refer to Table 1) 17.94 18.3 18.66 V

VO1 (Refer to Table 1) 19.00 19.3 19.68 V

Line Regulation DVO1, VIN = 8V to 14V; VO = 13.3V - 4.0 40.0 mV

DVO2
VIN = 8V to 14V; VO = 18.3V - 4.0 60.0 mV

Load Regulation DVO1, IO = 0mA to 350mA - 50 80 mV

DVO2
IO = 0mA to 750mA - 100 200 mV

Dynamic Output Current Limiting IMAX DCL = 0, ISEL H = 0, ISEL L = 0 (Note 8) 275 305 345 mA

DCL = 0, ISEL H = 0, ISEL L = 1 (Note 8) 515 570 630 mA

DCL = 0, ISEL H = 1, ISEL L = 0 (Note 8) 635 705 775 mA

DCL = 0, ISEL H = 1, ISEL L = 1 (Note 8) 800 890 980 mA

Dynamic Overload Protection Off Time TOFF DCL = 0, Output Shorted (Note 8) - 900 - ms

Dynamic Overload Protection On Time TON - 20 - ms

Static Output Current Limiting IMAX DCL = 1 (Note 8) - 990 - mA

Cable Fault CABF Threshold ICAB EN = 1, VO = 19V, No Tone 2 10 20 mA

FN9191 Rev 2.00 Page 5 of 16

Dec 5, 2008
ISL6423

Electrical Specifications VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN = H, VTOP
VBOT = L, ENT = L, DCL = L, Iout = 12mA, unless otherwise noted. See software description section for I2C
access to the system. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

TONE OSCILLATOR

Tone Frequency ftone ENT = H 20.0 22.0 24.0 kHz

Tone Amplitude Vtone ENT = H, IO = 5mA 500 680 800 mV

Tone Duty Cycle dctone ENT = H 40 50 60 %

Tone Rise or Fall Time Tr, Tf ENT = H 5 10 14 s

TONE DECODER

Input Amplitude Vtdin 200 - 1000 mV

Frequency Capture Range Ftdin 17.5 - 26.5 kHz

Input Impedance Zdet - 8.6 - k

Detector Output Voltage Vtdout_L Tone Present, Iload = 3mA - - 0.4 V

Detector Output Leakage Itdout_H Tone absent, VO = 6V - - 10 A

Tone Decoder Rx Threshold VRXth TXT = L & TTH = 0 (Note 9) 100 150 200 mV
Tone Decoder Tx Threshold VTXth TXT = H & TTH = 0 (Note 9) 400 450 500 mV

LINEAR REGULATOR

Drop-out Voltage Iout = 750mA - 0.80 1.05 V

Output Backward Leakage Current IOBK EN = 0; VOBK = 27V - 2.0 3.0 mA

Output Backward Leakage Current IOBK EN = 0; VOBK = 28V - 15 17 mA

Output Backward Current Threshold IOBKTH EN = 1; VOFAULT = 19V (Note 7) - 125 - mA

Output Backward Voltage IOBK EN = 0 - - 27 V

Output Undervoltage OUVF bit is asserted high, Measured from -6 - -2 %
(Asserted high during soft-start) the typical output set value

Output Overvoltage OUVF bit is asserted high, Measured from +2 - +6 %

(Asserted high during soft-start) the typical output set value

TXT, EXTM, SELVTOP AND ADDR 0/1 INPUT PINs (Note 8)

Asserted LOW - - 0.8 V

Asserted HIGH 1.7 - - V

Input Current - 25 - A

CURRENT SENSE (CS pin)

Input Bias Current IBIAS - 700 - nA

Overcurrent Threshold VCS Static current mode, DCL = H 325 450 500 mV

ERROR AMPLIFIER
Open Loop Voltage Gain AOL - 88 - dB

Gain Bandwidth Product GBP - 14 - MHz

PWM
Maximum Duty Cycle 90 93 - %

Minimum Pulse Width - 20 - ns

OSCILLATOR

Oscillator Frequency fo Fixed at (20)(ftone) 396 440 484 kHz

FN9191 Rev 2.00 Page 6 of 16

Dec 5, 2008
ISL6423

Electrical Specifications VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN = H, VTOP
VBOT = L, ENT = L, DCL = L, Iout = 12mA, unless otherwise noted. See software description section for I2C
access to the system. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

THERMAL SHUTDOWN

Temperature Shutdown Threshold - 150 - °C

Temperature Shutdown Hysteresis - 20 - °C

FLT

FLT (released) VO = 6V - - 10 A

FLT (asserted) ISINK = 3.2mA - - 0.4 V

NOTES:
5. Internal digital soft-start.
6. EXTM, TXT and SELVTOP and addr 0/1 pins have 200k internal pulldown resistors.
7. On exceeding this backward current limit threshold for a period of 100µs, the device enters the dynamic current limit mode and the BCF I2C bit
is set. The dynamic current limit duty ratio during a back current fault is ON = 100µs/OFF = 5ms.
8. In the Dynamic current limit mode the output is ON for 20ms and OFF for 900ms, but remains continuously ON in the Static mode. When tone
is ON, the minimum current limit is 50mA lower than the values indicated in the table. While in the dynamic mode of current limit the overload
trip level is momentarily increased to 990mA during the 20ms ON time to facilitate recovery from overload conditions.

Tone Waveform

ENT
I2C

MSEL
I2C

EXTM
PIN

VOUT
PIN
22kHz 22kHz 22kHz 22kHz 22kHz 22kHz

Internal Tone
Internal Tone Returns to nominal VOUT ~1 period
External Tone
Tr = 10µs typ after the last EXTM rising edge
Tr = 10µs typ
T > 55µs;

NOTES:
9. The signal pin TXT changes the decoder threshold during tone transmit and receive. TTH allows threshold control through I2C.
10. The tone rise and fall times are not shown due to resolution of graphics. It is 10µs typical for 22kHz.
11. The EXTM pins have input thresholds of Vil(max) = 0.8V and Vih(min) = 1.7V

FIGURE 1. TONE WAVEFORM

FN9191 Rev 2.00 Page 7 of 16

Dec 5, 2008
ISL6423

Typical Performance Curves

0.90 0.90

0.80 0.80

0.70 0.70
IOUT_max IOUT_max
0.60 0.60
IOUT_max (A)

IOUT_max (A)
0.50 0.50

0.40 0.40

0.30 0.30

0.20 0.20

0.10 0.10

0.00 0.00
0 20 40 60 80 0 20 40 60 80
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 2. OUTPUT CURRENT DERATING (HTSSOP) FIGURE 3. OUTPUT CURRENT DERATING (4x4 QFN)

Functional Pin Description

SYMBOL FUNCTION

SDA Bidirectional data from/to I2C bus.

SCL Clock from I2C bus.

VSW Input of the linear post-regulator.

PGND Dedicated ground for the output gate driver of respective PWM.

CS Current sense input; connect the sense resistor Rsc at this pin for desired peak overcurrent value for the boost FET. The
set peak limit is effective in the static mode current limit only (i.e., DCL = HIGH).

SGND Small signal ground for the IC.

TCAP Capacitor for setting rise and fall time of the output voltage. Typical value is 0.1µF.

BYPASS Bypass capacitor for internal 5V.

TXT TXT is the Tone Transmit signal input used to change the Tone Decoder Threshold from TXT = 0, 200mV maximum during
Receive to TXT = 1, 400mV minimum during transmit.

VCC Main power supply to the chip.

GATE This output drives the boost FET gate. The output is held low when VCC is below the UVLO threshold.

VO Output voltage for the LNB is available at VO pin.

ADDR0 and ADDR1 Logic combination at the ADDR0 and 1 can select four different chip select addresses.
EXTM This pin can be used in two ways:
1) As an input for externally modulated Diseqc tone signal which is transferred to the symmetrically onto Vout
2) Alternatively apply a Diseqc modulation envelope which modulates an internal tone and then transfers it symmetrically
onto Vout.

FLT This is an open drain output from the controller. when the flt goes low it indicates that an over temperature, over load fault,
back current fault, UVLO, or an I2C reset condition has occurred. The processor should then look at the I2C register to get
the actual cause of the error. A high on the FLT indicates that the device is functioning normally.

CPVOUT, CPSWIN A 47n charge pump decoupling capacitor is to be connected to CPVOUT. Connect a 1.5n capacitor between CPSWIN and
CPSWOUT CPSWOUT.

SELVTOP When this pin is low the Vout is in the 13V/14V range selected by the I2C bit VBOT.
When this pin is high the 18V/19V range selected by the I2C bit VTOP. The Voltage select pin enable VSPEN I2C bit must
be set low for the SELVTOP pins to be active. Setting VSPEN high disables this pins and voltage selection will be done
using the I2C bits VBOT and VTOP only.

TDIN, TDOUT TDIN is the tone decoder input and TDOUT is the tone detector output. TDOUT is an open drain output.

FN9191 Rev 2.00 Page 8 of 16

Dec 5, 2008
ISL6423

Functional Description Linear Regulator

The ISL6423 single output voltage regulator makes an ideal The output linear regulator will sink and source current. This
choice for advanced satellite set-top box and personal video feature allows full modulation capability into capacitive loads
recorder applications. The device utilizes built-in DC/DC step as high as 0.75F. In order to minimize the power dissipation,
up converters that, operates from a single supply source the output voltage of the internal step-up converter is adjusted
ranging from 8V to 14V, and generates the voltage needed to allow the linear regulator to work at minimum dropout.
to enable the linear post-regulator to work with a minimum of When the device is put in the shutdown mode (EN = LOW),
dissipated power. An undervoltage lockout circuit disables the PWM power block is disabled. When the regulator blocks
the device when VCC drops below a fixed threshold (7.5V are active (EN = HIGH and VSPEN = LOW), the output can
typical). be controlled via I2C logic to be 13V/14V or 18V/19V
DiSEqC Encoding (typical) by means of the VTOP and VBOT bits (voltage
select) for remote controlling of non-DiSEqC LNBs.
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards. When the regulator blocks are active (EN = HIGH and
No further adjustment is required. The tone oscillator can be VSPEN = HIGH), the VBOT and SELVTOP pin will control
controlled either by the I2C interface (ENT bit) or by a the output between 13V and 14V and the VTOP and
dedicated pin (EXTM) that allows immediate DiSEqC data SELVTOP pin will control the output between 18V and 19V.
encoding separately for each LNB. All the functions of this IC
are controlled via the I2C bus by writing to the system Output Timing
registers. The same registers can be read back, and four bits The output voltage rise and fall times can be set by an the
will report the diagnostic status. The internal oscillator external capacitor on the TCAP pin. The output voltage slew
operates the converters at twenty times the 22k tone rate for the rise is given by the equation:
frequency. The device offers full I2C compatibility, and V 270
SlewRatein -------- = ---------- (EQ. 1)
supports 2.5V, 3.3V or 5V logic, up to an operational speed of ms C
400kHz. Where C is the TCAP value in nF. For example, a 150nF
If the Tone Enable (ENT) bit is set LOW and the MSEL bits TCAP will provide for a slew rate of 1.8V/ms and thus a rise
set LOW through I2C, then the EXTM terminal activates the time of 3.3ms for a 6V transition. The output fall time is faster
internal tone signal, modulating the DC output with a by a factor of 3.5.
680mVPP typical symmetrical tone waveform. The presence The maximum value for TCAP would be based on the
of this signal usually provides the LNB with information maximum transition time allowed in the system application.
about the band to be received. Too small a value of the TCAP can cause high peak currents
Burst coding of the tone can be accomplished due to the fast in the boost circuit. For example, a 10V/ms slew on a 80µF
response of the EXTM input and rapid tone response. This VSW capacitor with an inductor of 15µH can cause a peak
allows implementation of the DiSEqC (EUTELSAT) inductor current of approximately 2.3A.
protocols. Current Limiting
When the ENT bit is set HIGH, a continuous 22kHz tone is Dynamic current limiting block has four thresholds that can
generated regardless of the EXTM pin logic status for the be selected by the ISEL H and ISEL L bits of the SR. Refer
regulator channel LNB-A. The ENT bit must be set LOW to Table 8 and Table 9 for threshold selection using these
when the EXTM pin is used for DiSEqC encoding. bits. The DCL bit has to be set to low for this mode of
operation. In this mode the overcurrent protection circuit
The EXTM accepts an externally modulated tone command
works dynamically: 23s after an overload is detected, the
when the MSEL I2C bit is set HIGH and ENT is set LOW.
output is shutdown for a time tOFF, typically 900ms.
DiSEqC Decoder Simultaneously, the OLF bit of the system register is set to
TDIN is the input to the tone decoder. It accepts the tone HIGH. After this time has elapsed, the output is resumed for
signal derived from the Vout thru the 10nF decoupling a time tON = 20ms. During tON, the device output will be
capacitor. The detector threshold can be set to 200mV current limited to 990mA. At the end of tON, if the overload
maximum in the receive mode and to 400mV minimum in the per that set by ISELL and ISELH bits is still detected, the
transmit mode by means of the logic presented to the TXT protection circuit will again cycle through tOFF and tON. At
pin. If tone is detected the open drain pin TDOUT is asserted the end of a full tON in which no overload is detected, normal
low. This enables the tone diagnostics to be performed, operation is resumed and the OLF bit is reset to LOW.
apart from the normal tone detection function. Typical tON + tOFF time is 920ms as determined by an
internal timer. This dynamic operation greatly reduces the
power dissipation in a short circuit condition, while still
ensuring excellent power-on start-up in most conditions.

FN9191 Rev 2.00 Page 9 of 16

Dec 5, 2008
ISL6423

However, there could be some cases in which a highly I2C Bus Interface for ISL6423
capacitive load on the output may cause a difficult start-up
(Refer to Philips I2C Specification, Rev. 2.1)
when the dynamic protection is selected. This can be solved
by initiating any power start-up in static mode (DCL = HIGH) Data transmission from main microprocessor to the ISL6423
and then switching to the dynamic mode (DCL = LOW) after and vice versa takes place through the two wire I2C bus
a predetermined interval. When in static mode, the OLF bit interface, consisting of the two lines SDA and SCL. Both
goes HIGH when the current clamp limit is reached and SDA and SCL are bidirectional lines, connected to a positive
returns LOW when the overload condition is cleared. The supply voltage via a pull up resistor. (Pull-up resistors to
OLF/BCF bit will be LOW at the end of initial power-on soft- positive supply voltage must be externally connected). When
start. In the static mode the output current through the linears the bus is free, both lines are HIGH. The output stages of
is limited to a 990mA typical. ISL6423 will have an open drain/open collector in order to
perform the wired-AND function. Data on the I2C bus can be
When a 19.3V line is connected onto a VOUT1 or 2 that has
transferred up to 100kbps in the standard-mode or up to
been set to 13.3V the linear will then enter a back current
400kbps in the fast-mode. The level of logic “0” and logic “1”
limited state. When a back current of greater than 125mA
is dependent of associated value of VDD as per electrical
typical is sensed at the lower FET of the linear for a period
specification table. One clock pulse is generated for each
greater that 100µs, the output is disabled for a period of 5ms
data bit transferred.
and the BCF bit is set. If the 19.3V remains connected, the
output will cycle through the ON = 100µs/OFF = 5ms. The Data Validity
output will recover when the fault is removed. The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
Thermal Protection
can only change when the clock signal on the SCL line is
This IC is protected against overheating. When the junction
LOW. Refer to Figure 4.
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. When the junction is cooled down to +130°C
SDA
(typical), normal operation is resumed and the OTF bit is
reset LOW.

In over temperature conditions, the OTF flag goes HIGH and SCL
the I2C data will be cleared. The user may need to monitor DATA LINE CHANGE
the I2C enable bits and OTF flag continuously and enable STABLE OF DATA
DATA VALID ALLOWED
the chip, if I2C data is cleared. OTF conditions may also
make the OLF flags go HIGH, when high capacitive loads
FIGURE 4. DATA VALIDITY
are present or self-heating conditions occur at higher loads.

External Output Voltage Selection START and STOP Conditions

When the I2C bit VSPEN is set high the output voltage can As shown in Figure 5, START condition is a HIGH to LOW
be selected by the I2C bus. Additionally, the package offers transition of the SDA line while SCL is HIGH.
the pin SELVTOP for independent 13V thru 19V output
The STOP condition is a LOW to HIGH transition on the SDA
voltage selection, when the VSPEN bit is set low. A
line while SCL is HIGH. A STOP condition must be sent
summary of the voltage control is given in the Table 1. For
before each START condition.
further details refer to the individual registers SR1 and SR3
TABLE 1.

VSPEN VTOP VBOT SELVTOP VOUT (V) SDA

0 x 0 0 13.3
0 x 1 0 14.3
SCL
0 0 x 1 18.3 S P
START STOP
0 1 x 1 19.3
CONDITION CONDITION
1 0 0 x 13.3
FIGURE 5. START AND STOP WAVEFORMS
1 0 1 x 14.3
1 1 0 x 18.3
1 1 1 x 19.3

FN9191 Rev 2.00 Page 10 of 16

Dec 5, 2008
 ISL6423

Byte Format ISL6423 Software Description

Every byte put on the SDA line must be eight bits long. The
Interface Protocol
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an The interface protocol is comprised of the following, as
acknowledge bit. Data is transferred with the most significant shown below in Table 2:
bit first (MSB). • A start condition (S)
Acknowledge • A chip address byte (MSB on left; the LSB bit determines
The master (microprocessor) puts a resistive HIGH level on read (1) or write (0) transmission) (the assigned I2C slave
the SDA line during the acknowledge clock pulse (Figure 6). address for the ISL6423 is 0001 0XXX)
The peripheral that acknowledges has to pull-down (LOW) • A sequence of data (1 byte + Acknowledge)
the SDA line during the acknowledge clock pulse, so that the
• A stop condition (P)
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.) TABLE 2. INTERFACE PROTOCOL

S 0 0 0 1 0 A1 A0 R/W ACK Data (8 bits) ACK P

The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth System Register Format
clock pulse time. In this case, the master transmitter can • R, W = Read and Write bit
generate the STOP information in order to abort the transfer. • R = Read-only bit
The ISL6423 will not generate the acknowledge if the All bits reset to 0 at Power-On
POWER OK signal from the UVLO is LOW.
TABLE 3. STATUS REGISTER (SR1)
SCL R, W R, W R, W R R R R R
1 2 8 9
SR1H SR1M SR1L OTF CABF OUVF OLF BCF
SDA
TABLE 4. TONE REGISTER (SR2)
MSB
R, W R, W R, W R, W R, W R, W R, W R, W
START ACKNOWLEDGE
FROM SLAVE
SR2H SR2M SR2L ENT MSEL TTH X X

FIGURE 6. ACKNOWLEDGE ON THE I2C BUS

TABLE 5. COMMAND REGISTER (SR3)

R, W R, W R, W R, W R, W R, W R, W R, W
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the SR3H SR3M SR3L DCL VSPEN X ISELH ISELL
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends TABLE 6. CONTROL REGISTER (SR4)
the new data. R, W R, W R, W R, W R, W R, W R, W R, W

This approach, though, is less protected from error and SR4H SR4M SR4L EN VTOP VBOT
decreases the noise immunity.
Transmitted Data (I2C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR2 thru
SR4) of the ISL6423 via I2C bus. These will be written by the
microprocessor as shown below. The spare bits of registers
can be used for other functions.

FN9191 Rev 2.00 Page 11 of 16

Dec 5, 2008
ISL6423

TABLE 7. STATUS REGISTER SR1 CONFIGURATION

SR1H SR1M SR1L OTF CABF OUVF OLF BCF FUNCTION

0 0 0 X X X X X SR1 is selected

0 0 0 X X X 0 X Iout  set limit, normal operation

0 0 0 X X X 1 X Iout > static/dynamic limiting mode/power blocks disabled

0 0 0 X X X X 0 Iobck  set limit, normal operation

0 0 0 X X X X 1 Iobck > dynamic limiting mode/power blocks disabled

0 0 0 X X 0 X X Vin/Vout within specified range

0 0 0 X X 1 X X Vin/Vout is not within specified range

0 0 0 X 0 X X X Cable is connected, Io is > 20mA

0 0 0 X 1 X X X Cable is open, Io < 2mA

0 0 0 0 X X X X TJ  +130°C, normal operation

0 0 0 1 X X X X TJ > +150°C, power blocks disabled

TABLE 8. TONE REGISTER SR2 CONFIGURATION

SR2H SR2M SR2L ENT MSEL TTH X X FUNCTION

0 0 1 X X X X X SR2 is selected

0 0 1 0 0 X X X Int Tone = 22kHz, modulated by EXTM, Tr, Tf = 10µs typical

0 0 1 0 1 X X X Ext 22k modulated input, Tr, Tf = 10µs typical

0 0 1 1 0 X X X Int Tone = 22kHz, modulated by ENT bit, Tr, Tf = 10µs typical

0 0 1 X X 0 X X TXT = 0; Decoder Rx threshold is set at 200mV maximum

0 0 1 X X 1 X X TXT = 0; Decoder Tx threshold is set at 400mV mininum

NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.

TABLE 9. COMMAND REGISTER SR3 CONFIGURATION

SR3H SR3M SR3L DCL VSPEN X ISELH ISELL FUNCTION

0 1 0 X X X X X SR3 is selected

0 1 0 0 X X 0 0 Iout1 = 275mA maximum

0 1 0 0 X X 0 1 Iout1 = 515mA maximum

0 1 0 0 X X 1 0 Iout1 = 635mA maximum

0 1 0 0 X X 1 1 Iout1 = 800mA maximum

0 1 0 1 X X X X Dynamic current limit NOT selected

0 1 0 0 X X X Dynamic current limit selected

0 1 0 X 0 X X X SELVTOP H/W pin enabled

0 1 0 X 1 X X X SELVTOP H/W pin disabled

NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.

FN9191 Rev 2.00 Page 12 of 16

Dec 5, 2008
ISL6423

TABLE 10. CONTROL REGISTER SR4 CONFIGURATION

SR4H SR4M SR4L EN X X VTOP VBOT FUNCTION

0 1 1 1 X X 0 0 SR4 is selected

0 1 1 1 X X 0 0 VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop

0 1 1 1 X X 0 1 VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop

0 1 1 1 X X 1 0 VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop

0 1 1 1 X X 1 1 VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop

0 1 1 1 X X 0 0 VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop

0 1 1 1 X X 0 1 VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop

0 1 1 1 X X 1 0 VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop

0 1 1 1 X X 1 1 VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop

0 1 1 1 X X 0 0 VSPEN = 1, SELVTOP = X Vout1 = 13V, Vboost1 = 13V + Vdrop

0 1 1 1 X X 0 1 VSPEN = 1, SELVTOP = X Vout1 = 14V, Vboost1 = 14V + Vdrop

0 1 1 1 X X 1 0 VSPEN = 1, SELVTOP = X Vout1 = 18V, Vboost1 = 18V + Vdrop

0 1 1 1 X X 1 1 VSPEN = 1, SELVTOP = X Vout1 = 19V, Vboost1 = 19V + Vdrop

0 1 1 0 X X X X PWM and Linear for channel 1 disabled

NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.

Received Data (I2C bus READ MODE) ADDR0 and ADDR1 Pins
The ISL6423 can provide to the master a copy of the system Connecting these pin to GND the chip I2C interface address
register information via the I2C bus in read mode. The read is 0001000, but, it is possible to choose between four
mode is Master activated by sending the chip address with different addresses by setting these pins to the logic levels
R/W bit set to 1. At the following Master generated clock bits, indicated in Table 11.
the ISL6423 issues a byte on the SDA data bus line (MSB
TABLE 11. ADDRESS PIN CHARACTERISTICS
transmitted first).
VADDR ADDR1 ADDR0
At the ninth clock bit the MCU master can:
VADDR-1 “0001000” 0 0
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6423. VADDR-2 “0001001” 0 1
VADDR-3 “0001010” 1 0
• Not acknowledge, stopping the read mode
communication. VADDR-4 “0001011” 1 1
The read only bits of the register SR1 convey diagnostic
information about the ISL6423, as indicated in the Table 7.

Power–On I2C Interface Reset

The I2C interface built into the ISL6423 is automatically reset
at power-on. The I2C interface block will receive a power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I2C commands and the
system register SR1 thru SR4 are all initialized to zero, thus
keeping the power blocks disabled. Once the VCC rises
above UVLO, the POWER OK signal to the I2C is asserted
high, and the I2C interface becomes operative and the SR’s
can be configured by the main microprocessor. About
400mV of hysteresis is provided in the UVLO threshold to
avoid false triggering of the power-on reset circuit. (I2C
comes up with EN = 0; EN goes HIGH at the same time as
(or later than) all other I2C data for that PWM becomes
valid).

FN9191 Rev 2.00 Page 13 of 16

Dec 5, 2008
ISL6423

I2C Bit Description I2C Electrical Characteristics

TABLE 12.
BIT NAME DESCRIPTION
TEST
EN ENable Output for channels 1 and 2
PARAMETER CONDITION MIN TYP MAX
VTOP Voltage TOP Select i.e., 18V/19V for channels 1 and 2
Input Logic SDA, SCL 2.0V
VBOT Voltage BOTtom Select i.e., 13V/14V for channels 1 High, VIH
and 2
Input Logic SDA, SCL 0.8V
ENT ENable Tone Low, VIL

MSEL Modulation SELect Input Logic SDA, SCL; 10A

Current, IIL 0.4V < VDD< 3.3V
DCL Dynamic Current Limit select
Input Logic VOL = 0.4V 3mA
VSPEN Voltage Select Pin ENable Current IOL
ISELH and Current limit “I” SELect High and Low bit Input SDA, SCL 165mV 200mV 235mV
ISELL Hysteresis
OTF Over Temperature Fault bit SCL Clock 0 100kHz 400kHz
CABF CABle Fault or open status bit. Frequency

OUVF Over and Under Voltage Fault status bit Input Filter 50ns
Spike reject
OLF Over Load Fault status bit

BCF Backward Current Fault bit

TTH Tone THreshold is the OR of the signal pin TXT

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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN9191 Rev 2.00 Page 14 of 16

Dec 5, 2008
ISL6423

Package Outline Drawing

L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06

4X 2.5
4.00 A
20X 0.50
B PIN #1 CORNER
19 24 (C 0 . 25)

PIN 1
INDEX AREA 18 1

2 . 50 ± 0 . 15

4.00

13

(4X) 0.15
12 7

24X 0 . 4 ± 0 . 1 0.10 M C A B
TOP VIEW
24X 0 . 23 +- 0
0 . 07
. 05 4
BOTTOM VIEW

SEE DETAIL "X"

0.10 C
0 . 90 ± 0 . 1 C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
SIDE VIEW
0.08 C
( 2 . 50 )

( 20X 0 . 5 )

C 0 . 2 REF 5

( 24X 0 . 25 )
0 . 00 MIN.
( 24X 0 . 6 ) 0 . 05 MAX.

DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.

FN9191 Rev 2.00 Page 15 of 16

Dec 5, 2008
ISL6423

Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)

N M28.173B
INDEX 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
E 0.25(0.010) M B M
AREA
E1 INCHES MILLIMETERS
GAUGE
-B- PLANE SYMBOL MIN MAX MIN MAX NOTES
A - 0.047 - 1.20 -
1 2 3 A1 0.002 0.006 0.05 0.15 -
TOP VIEW L A2 0.031 0.051 0.80 1.05 -
0.25
0.010 b 0.0075 0.0118 0.19 0.30 9
0.05(0.002) SEATING PLANE
c 0.0035 0.0079 0.09 0.20 -
-A-
D A D 0.378 0.386 9.60 9.80 3
E1 0.169 0.177 4.30 4.50 4
-C- 
A2 e 0.026 BSC 0.65 BSC -
c E 0.246 0.256 6.25 6.50 -
e A1
L 0.0177 0.0295 0.45 0.75 6
b 0.10(0.004)
N 28 28 7
0.10(0.004) M C A M B S
 0° 8° 0° 8° -
P - 0.138 - 5.50 11
1 2 3
P1 - 0.118 - 3.0 11
Rev. 0 6/05
NOTES:
P1
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AET, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
N
3. Dimension “D” does not include mold flash, protrusions or gate
P
burrs. Mold flash, protrusion and gate burrs shall not exceed
BOTTOM VIEW 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.

FN9191 Rev 2.00 Page 16 of 16

Dec 5, 2008