®

ISL6326

Data Sheet April 21, 2006 FN9262.0

4-Phase PWM Controller with 8-Bit DAC Features

Code Capable of Precision DCR • Proprietary Active Pulse Positioning and Adaptive Phase
Differential Current Sensing Alignment Modulation Scheme
The ISL6326 controls microprocessor core voltage regulation • Precision Multiphase Core Voltage Regulation
by driving up to 4 synchronous-rectified buck channels in - Differential Remote Voltage Sensing
parallel. Multiphase buck converter architecture uses
- ±0.5% System Accuracy Over Life, Load, Line and
interleaved timing to multiply channel ripple frequency and Temperature
reduce input and output ripple currents. Lower ripple results in
- Adjustable Precision Reference-Voltage Offset
fewer components, lower component cost, reduced power
dissipation, and smaller implementation area. • Precision resistor or DCR Current Sensing
- Accurate Load-Line Programming
Microprocessor loads can generate load transients with
- Accurate Channel-Current Balancing
extremely fast edge rates. The ISL6326 utilizes Intersil’s
- Differential Current Sense
proprietary Active Pulse Positioning (APP) and Adaptive
Phase Alignment (APA) modulation scheme to achieve the • Microprocessor Voltage Identification Input
extremely fast transient response with fewer output capacitors. - Dynamic VID™ Technology
Today’s microprocessors require a tightly regulated output - 8-Bit VID Input with Selectable VR11 Code and
Extended VR10 Code at 6.25mV Per Bit
voltage position versus load current (droop). The ISL6326
senses the output current continuously by utilizing patented • Thermal Monitoring
techniques to measure the voltage across the dedicated
• Integrated Programmable Temperature Compensation
current sense resistor or the DCR of the output inductor.
Current sensing provides the needed signals for precision • Overcurrent Protection and Channel Current Limit
droop, channel-current balancing, and overcurrent • Overvoltage Protection
protection. A programmable integrated temperature
compensation function is implemented to effectively • 2, 3 or 4 Phase Operation
compensate for the temperature coefficient of the current • Adjustable Switching Frequency up to 1MHz Per Phase
sense element. The current limit function provides the
• Package Option
overcurrent protection for the individual phase.
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
A unity gain, differential amplifier is provided for remote Flat No Leads - Product Outline
voltage sensing. Any potential difference between remote - QFN Near Chip Scale Package Footprint; Improves
and local grounds can be completely eliminated using the PCB Efficiency, Thinner in Profile
remote-sense amplifier. Eliminating ground differences
improves regulation and protection accuracy. The threshold-
• Pb-Free Plus Anneal Available (RoHS Compliant)
sensitive enable input is available to accurately coordinate
the start up of the ISL6326 with any other voltage rail.
Ordering Information
Dynamic-VID™ technology allows seamless on-the-fly VID PART NUMBER PART TEMP. PACKAGE PKG.
changes. The offset pin allows accurate voltage offset (Note) MARKING (°C) (Pb-free) DWG. #
settings that are independent of VID setting. ISL6326CRZ ISL6326CRZ 0 to70 40 Ld 6x6 QFN L40.6x6

ISL6326IRZ ISL6326IRZ -40 to 85 40 Ld 6x6 QFN L40.6x6

Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 ISL6326

Pinout ISL6326 (40 LD QFN)

TOP VIEW

EN_PWR
VR_HOT

VR_RDY
VR_FAN

EN_VTT

PWM3
VID7

TM

SS

FS
40 39 38 37 36 35 34 33 32 31

VID6 1 30 ISEN3+

VID5 2 29 ISEN3-

VID4 3 28 ISEN2-

VID3 4 27 ISEN2+

VID2 5 26 PWM2
GND
VID1 6 25 PWM4

VID0 7 24 ISEN4+

VRSEL 8 23 ISEN4-

OFS 9 22 ISEN1-

DAC 10 21 ISEN1+

11 12 13 14 15 16 17 18 19 20
COMP

IDROOP

PWM1
REF

VDIFF

RGND

VSEN

VCC
FB

TCOMP

2 FN9262.0
April 21, 2006
 ISL6326

ISL6326CR Block Diagram

VDIFF VR_RDY FS

CLOCK AND POWER-ON - 0.875

RGND - RAMP GENERATOR RESET (POR)
X1 + EN_VTT
VSEN +
N

- 0.875

+ EN_PWR
+ SOFTSTART
OVP AND
- FAULT LOGIC

+175mV
APP and APA
MODULATOR
PW M1
SS

VRSEL
APP and APA
VID7 MODULATOR
PW M2
VID6
VID5
VID4 Dynamic
VID
VID3 D/A
APP and APA
VID2 MODULATOR
PW M3
VID1
VID0

DAC
APP and APA
MODULATOR
PW M4

OFS OFFSET

REF +
E/A CHANNEL CHANNEL
- CURRENT DETECT
FB
BALANCE
AND PEAK
COMP CURRENT LIMIT
N

I_TRIP ISEN1+
-
OCP ISEN1-
+
ISEN2+
IDROOP CHANNEL
Σ
1 TEMPERATURE
ISEN2-
CURRENT
N COMPENSATION SENSE ISEN3+
ISEN3-
ISEN4+
ISEN4-
VR_HOT TEMPERATURE
THERMAL
COMPENSATION
MONITOR
GAIN ADJUST
VR_FAN

TM TCOMP GND

3 FN9262.0
April 21, 2006
 ISL6326

Typical Application - 4-Phase Buck Converter with External Temperature Compensation

+12V VIN
BOOT
THERMISTOR PVCC
NTC
o
C +5V VCC UGATE
PHASE
ISL6612
DRIVER
LGATE

FB COMP VCC DAC PWM GND

IDROOP REF
VDIFF
VSEN
RGND PWM1 +12V VIN
BOOT
ISEN1- PVCC
VTT EN_VTT
ISEN1+
VR_RDY
VCC UGATE
VID7
PHASE
VID6 ISL6326 ISL6612
VID5
DRIVER
LGATE
VID4
VID3 PWM GND
PWM2
VID2
ISEN2-
VID1
ISEN2+
VID0
+12V VIN
VRSEL BOOT
VR_FAN PWM3 PVCC
uP
ISEN3- LOAD
VR_HOT
VCC UGATE
ISEN3+
VIN PHASE
ISL6612

EN_PWR DRIVER
LGATE

PWM GND
GND
PWM4
ISEN4-
ISEN4+
TCOMP
+12V VIN
TM OFS FS SS BOOT
PVCC
+5V

VCC UGATE
PHASE
o
C
ISL6612
DRIVER
LGATE

PWM GND

4 FN9262.0
April 21, 2006
 ISL6326

Typical Application - 4-Phase Buck Converter with Integrated Temperature Compensation

+5V +12V VIN

VCC BOOT1

UGATE1
PHASE1
FB COMP VCC DAC
GND
IDROOP REF
LGATE1
VDIFF
VSEN ISL6614 PVCC
5V
To
RGND DRIVER 12V VIN
ISEN1+ BOOT2
VTT EN_VTT
ISEN1-
VR_RDY
PWM1
PWM1 UGATE2
VID7
PHASE2
VID6
VID5 ISL6326
LGATE2
VID4
VID3 PWM2 PGND
PWM3
VID2
ISEN3-
VID1
ISEN3+
VID0
VRSEL ISEN2+
VR_FAN ISEN2- uP
VR_HOT +12V VIN LOAD
PWM2
VCC BOOT1
VIN

UGATE1
EN_PWR PHASE1
PWM4
GND
GND
ISEN4-
LGATE1
ISEN4+
ISL6614 5V
PVCC
To
TCOMP DRIVER VIN
12V
BOOT2
TM OFS FS SS
+5V +5V
PWM1
UGATE2
PHASE2

NTC
LGATE2
PWM2 PGND

5 FN9262.0
April 21, 2006
 ISL6326

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V Thermal Resistance (Notes 1, 2) θJA (°C/W) θJC (°C/W)
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V QFN Package. . . . . . . . . . . . . . . . . . . . 32 3.5
ESD (Human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
ESD (Machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
ESD (Charged device model) . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature (ISL6326CRZ) . . . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature (ISL6326IRZ) . . . . . . . . . . . . . .-40°C to 85°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply VCC = 5VDC; EN_PWR = 5VDC; RT = 100kΩ, - 18 26 mA

ISEN1 = ISEN2 = ISEN3 = ISEN4 = -70μA

Shutdown Supply VCC = 5VDC; EN_PWR = 0VDC; RT = 100kΩ - 14 21 mA

POWER-ON RESET AND ENABLE

POR Threshold VCC Rising 4.3 4.5 4.7 V

VCC Falling 3.7 3.9 4.2 V

EN_PWR Threshold Rising 0.850 0.875 0.910 V

Hysteresis - 130 - mV

Falling 0.720 0.745 0.775 V

EN_VTT Threshold Rising 0.850 0.875 0.910 V

Hysteresis - 130 - mV

Falling 0.720 0.745 0.775 V

REFERENCE VOLTAGE AND DAC

System Accuracy of ISL6326CRZ (Note 3) -0.5 - 0.5 %VID

(VID = 1V-1.6V, TJ = 0°C to 70°C)

System Accuracy of ISL6326CRZ (Note 3) -0.9 - 0.9 %VID

(VID = 0.5V-1V, TJ = 0°C to 70°C)

System Accuracy of ISL6326IRZ (Note 3) -0.6 - 0.6 %VID

(VID = 1V-1.6V, TJ = -40°C to 85°C)

System Accuracy of ISL6326IRZ (Note 3) -1 - 1 %VID

(VID = 0.5V-1V,TJ = -40°C to 85°C)

VID Pull Up -60 -40 -20 μA

VID Input Low Level - - 0.4 V

VID Input High Level 0.8 - - V

VRSEL Input Low Level - - 0.4 V

VRSEL Input High Level 0.8 - - V

DAC Source Current - 4 7 mA

6 FN9262.0
April 21, 2006
 ISL6326

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC Sink Current - - 300 μA

REF Source Current 45 50 55 μA

REF Sink Current 45 50 55 μA

PIN-ADJUSTABLE OFFSET

Voltage at OFS Pin Offset resistor connected to ground 380 400 420 mV

Voltage below VCC, offset resistor connected to VCC 1.55 1.600 1.65 V

OSCILLATORS

Accuracy of Switching Frequency Setting RT = 100kΩ 225 250 275 kHz

Adjustment Range of Switching Frequency (Note 4) 0.08 - 1.0 MHz

Soft-Start Ramp Rate RS = 100kΩ (Notes 5, 6) - 1.563 - mV/µs

Adjustment Range of Soft-Start Ramp Rate (Note 4) 0.625 - 6.25 mV/µs

PWM GENERATOR

Sawtooth Amplitude - 1.25 - V

ERROR AMPLIFIER

Open-Loop Gain RL = 10kΩ to ground (Note 4) - 96 - dB

Open-Loop Bandwidth (Note 4) - 80 - MHz

Slew Rate (Note 4) - 25 - V/µs

Maximum Output Voltage 3.8 4.3 4.9 V

Output High Voltage @ 2mA 3.6 - - V

Output Low Voltage @ 2mA - - 1.8 V

REMOTE-SENSE AMPLIFIER

Bandwidth (Note 4) - 20 - MHz

Output High Current VSEN - RGND = 2.5V -500 - 500 μA

Output High Current VSEN - RGND = 0.6 -500 - 500 μA

PWM OUTPUT

PWM Output Voltage LOW Threshold Iload = ±500μA - - 0.5 V

PWM Output Voltage HIGH Threshold Iload = ±500μA 4.3 - - V

CURRENT SENSE AND OVERCURRENT PROTECTION

Sensed Current Tolerance (IDROOP) ISEN1 = ISEN2 = ISEN3 = ISEN4 = 60μA 57 60 63 μA

Overcurrent Trip Level for Average Current 72 85 98 μA

Peak Current Limit for Individual Channel 100 120 140 μA

THERMAL MONITORING AND FAN CONTROL

TM Input Voltage for VR_FAN Trip 1.55 1.65 1.75 V

TM Input Voltage for VR_FAN Reset 1.85 1.95 2.05 V

TM Input Voltage for VR_HOT Trip 1.3 1.4 1.5 V

TM Input Voltage for VR_HOT Reset 1.55 1.65 1.75 V

Leakage Current of VR_FAN With externally pull-up resistor connected to VCC - - 30 μA

VR_FAN Low Voltage IVR_FAN = 4mA - - 0.4 V

7 FN9262.0
April 21, 2006
 ISL6326

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Leakage Current of VR_HOT With externally pull-up resistor connected to VCC - - 30 μA

VR_HOT Low Voltage IVR_HOT = 4mA - - 0.4 V

VR READY AND PROTECTION MONITORS

Leakage Current of VR_RDY With externally pull-up resistor connected to VCC - - 30 μA

VR_RDY Low Voltage IVR_RDY = 4mA - - 0.4 V

Undervoltage Threshold VDIFF Falling 48 50 52 %VID

VR_RDY Reset Voltage VDIFF Rising 58 60 62 %VID

Overvoltage Protection Threshold Before valid VID 1.250 1.275 1.300 V

After valid VID, the voltage above VID 150 175 200 mV

Overvoltage Protection Reset Hysteresis - 100 - mV

NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Spec guaranteed by design.
5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.

8 FN9262.0
April 21, 2006
 ISL6326

Functional Pin Description the amplifier’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
VCC - Supplies the power necessary to operate the chip.
pins of the remote load.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the FB and COMP - Inverting input and output of the error
voltage on this pin drops below the falling POR threshold. amplifier respectively. FB can be connected to VDIFF
Connect this pin directly to a +5V supply. through a resistor. A properly chosen resistor between
VDIFF and FB can set the load line (droop), when IDROOP
GND - Bias and reference ground for the IC. The bottom
pin is tied to FB pin. The droop scale factor is set by the ratio
metal base of ISL6326 is the GND.
of the ISEN resistors and the inductor DCR or the dedicated
EN_PWR - This pin is a threshold-sensitive enable input for current sense resistor. COMP is tied back to FB through an
the controller. Connecting the 12V supply to EN_PWR external R-C network to compensate the regulator.
through an appropriate resistor divider provides a means to
DAC and REF - The DAC pin is the output of the precision
synchronize power-up of the controller and the MOSFET
internal DAC reference. The REF pin is the positive input of
driver ICs. When EN_PWR is driven above 0.875V, the
the Error Amp. In typical applications, a 1kΩ, 1% resistor is
ISL6326 is active depending on status of EN_VTT, the
used between DAC and REF to generate a precision offset
internal POR, and pending fault states. Driving EN_PWR
voltage. This voltage is proportional to the offset current
below 0.745V will clear all fault states and prime the ISL6326
determined by the offset resistor from OFS to ground or
to soft-start when re-enabled.
VCC. A capacitor is used between REF and ground to
EN_VTT - This pin is another threshold-sensitive enable smooth the voltage transition during Dynamic VID™
input for the controller. It’s typically connected to VTT output operations.
of VTT voltage regulator in the computer mother board.
PWM1, PWM2, PWM3, PWM4 - Pulse width modulation
When EN_VTT is driven above 0.875V, the ISL6326 is active
outputs. Connect these pins to the PWM input pins of the
depending on status of EN_PWR, the internal POR, and
Intersil driver IC. The number of active channels is
pending fault states. Driving EN_VTT below 0.745V will clear
determined by the state of PWM3 and PWM4. Tie PWM3 to
all fault states and prime the ISL6326 to soft-start when
VCC to configure for 2-phase operation. Tie PWM4 to VCC
re-enabled.
to configure for 3-phase operation.
FS - Use this pin to set up the desired switching frequency. A
ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-;
resistor, placed from FS to ground will set the switching
ISEN4+, ISEN4- - The ISEN+ and ISEN- pins are current
frequency. The relationship between the value of the resistor
sense inputs to individual differential amplifiers. The sensed
and the switching frequency will be described by an
current is used for channel current balancing, overcurrent
approximate equation.
protection, and droop regulation. Inactive channels should
SS - Use this pin to set up the desired start-up oscillator have their respective current sense inputs left open (for
frequency. A resistor, placed from SS to ground will set up example, open ISEN4+ and ISEN4- for 3-phase operation).
the soft-start ramp rate. The relationship between the value
For DCR sensing, connect each ISEN- pin to the node
of the resistor and the soft-start ramp up time will be
between the RC sense elements. Tie the ISEN+ pin to the
described by an approximate equation.
other end of the sense capacitor through a resistor, RISEN.
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 - The voltage across the sense capacitor is proportional to the
These are the inputs to the internal DAC that generates the inductor current. Therefore, the sense current is proportional
reference voltage for output regulation. Connect these pins to the inductor current, and scaled by the DCR of the
either to open-drain outputs with or without external pull-up inductor and RISEN.
resistors or to active pull-up outputs. All VID pins have 40µA
To match the time delay of the internal circuit, a capacitor is
internal pull-up current sources that diminish to zero as the
needed between each ISEN+ pin and GND, as described in
voltage rises above the logic-high level. These inputs can be
the Current Sensing section.
pulled up externally as high as VCC plus 0.3V.
VR_RDY - VR_RDY indicates that soft-start has completed
VRSEL - use this pin to select internal VID code. When it is
and the output voltage is within the regulated range around
connected to GND, the extended VR10 code is selected.
VID setting. It is an open-drain logic output. When OCP or
When it’s floated or pulled to high, VR11 code is selected.
OVP occurs, VR_RDY will be pulled to low. It will also be
This input can be pulled up as high as VCC plus 0.3V.
pulled low if the output voltage is below the undervoltage
VDIFF, VSEN, and RGND - VSEN and RGND form the threshold.
precision differential remote-sense amplifier. This amplifier
OFS - The OFS pin can be used to program a DC offset
converts the differential voltage of the remote output to a
current which will generate a DC offset voltage between the
single-ended voltage referenced to local ground. VDIFF is
REF and DAC pins. The offset current is generated via an

9 FN9262.0
April 21, 2006
 ISL6326

external resistor and precision internal voltage references. Operation

The polarity of the offset is selected by connecting the
resistor to GND or VCC. For no offset, the OFS pin should Multiphase Power Conversion
be left unterminated. Microprocessor load current profiles have changed to the
point that the advantages of multiphase power conversion
TCOMP - Temperature compensation scaling input. The
are impossible to ignore. The technical challenges
voltage sensed on the TM pin is utilized as the temperature
associated with producing a single-phase converter which is
input to adjust ldroop and the overcurrent protection limit to
both cost-effective and thermally viable have forced a
effectively compensate for the temperature coefficient of the
change to the cost-saving approach of multiphase. The
current sense element. To implement the integrated
ISL6326 controller helps reduce the complexity of
temperature compensation, a resistor divider circuit is
implementation by integrating vital functions and requiring
needed with one resistor being connected from TCOMP to
minimal output components. The block diagrams on pages
VCC of the controller and another resistor being connected
3, 4, and 5 provide top level views of multiphase power
from TCOMP to GND. Changing the ratio of the resistor
conversion using the ISL6326 controller.
values will set the gain of the integrated thermal
compensation. When integrated temperature compensation
Interleaving
function is not used, connect TCOMP to GND.
The switching of each channel in a multiphase converter is
IDROOP - IDROOP is the output pin of the sensed average timed to be symmetrically out of phase with each of the other
channel current which is proportional to the load current. In channels. In a 3-phase converter, each channel switches 1/3
the application which does not require loadline, this pin can cycle after the previous channel and 1/3 cycle before the
be connected to GND through a resistor to generate a following channel. As a result, the three-phase converter has
voltage signal, which is proportional the load current and the a combined ripple frequency three times greater than the
resistor value. In the application which requires load line, ripple frequency of any one phase. In addition, the peak-to-
connect this pin to FB so that the sensed average current peak amplitude of the combined inductor currents is reduced
will flow through the resistor between FB and VDIFF to in proportion to the number of phases (Equations 1 and 2).
create a voltage drop which is proportional to load current. Increased ripple frequency and lower ripple amplitude mean
Tie this pin to GND if not used. that the designer can use less per-channel inductance and
TM - TM is an input pin for the VR temperature lower total output capacitance for any performance
measurement. Connect this pin through an NTC thermistor specification.
to GND and a resistor to VCC of the controller. The voltage Figure 1 illustrates the multiplicative effect on output ripple
at this pin is reverse proportional to the VR temperature. frequency. The three channel currents (IL1, IL2, and IL3)
ISL6326 monitors the VR temperature based on the voltage combine to form the AC ripple current and the DC load
at the TM pin and outputs VR_HOT and VR_FAN signals. current. The ripple component has three times the ripple
VR_HOT - VR_HOT is used as an indication of high VR frequency of each individual channel current. Each PWM
temperature. It is an open-drain logic output. It will be pulled pulse is terminated 1/3 of a cycle after the PWM pulse of the
low if the measured VR temperature is less than a certain previous phase. The DC components of the inductor currents
level, and open when the measured VR temperature combine to feed the load.
reaches a certain level. A external pull-up resistor is needed.

VR_FAN - VR_FAN is an output pin with open-drain logic

output. It will be pulled low if the measured VR temperature IL1 + IL2 + IL3, 7A/DIV
is less than a certain level, and open when the measured VR
temperature reaches a certain level. A external pull-up
IL1, 7A/DIV
resistor is needed.
PWM1, 5V/DIV

IL2, 7A/DIV

PWM2, 5V/DIV

IL3, 7A/DIV

PWM3, 5V/DIV

1µs/DIV

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 3-PHASE CONVERTER

10 FN9262.0
April 21, 2006
 ISL6326

To understand the reduction of ripple current amplitude in the RMS input capacitor current. The single-phase converter
multiphase circuit, examine the equation representing an must use an input capacitor bank with twice the RMS current
individual channel’s peak-to-peak inductor current. capacity as the equivalent three-phase converter.
( V IN – V OUT ) V OUT Figures 18, 19 and 20 in the section entitled Input Capacitor
I PP = -----------------------------------------------------
- (EQ. 1)
L fS V Selection can be used to determine the input-capacitor RMS
IN
current based on load current, duty cycle, and the number of
In Equation 1, VIN and VOUT are the input and output channels. They are provided as aids in determining the
voltages respectively, L is the single-channel inductor value, optimal input capacitor solution. Figure 21 shows the single
and fS is the switching frequency. phase input-capacitor RMS current for comparison.

INPUT-CAPACITOR CURRENT, 10A/DIV PWM Modulation Scheme

The ISL6326 adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve transient
performance. APP control is a unique dual-edge PWM
CHANNEL 1
modulation scheme with both PWM leading and trailing
INPUT CURRENT edges being independently moved to give the best response
10A/DIV to transient loads. The PWM frequency, however, is constant
and set by the external resistor between the FS pin and
CHANNEL 2
INPUT CURRENT GND. To further improve the transient response, the
10A/DIV ISL6326 also implements Intersil's proprietary Adaptive
Phase Alignment (APA) technique. APA, with sufficiently
CHANNEL 3 large load step currents, can turn on all phases together.
INPUT CURRENT
With both APP and APA control, ISL6326 can achieve
10A/DIV
excellent transient performance and reduce the demand on
1µs/DIV
the output capacitors.
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE Under steady state conditions the operation of the ISL6326
CONVERTER PWM modulator appears to be that of a conventional trailing
edge modulator. Conventional analysis and design methods
The output capacitors conduct the ripple component of the
can therefore be used for steady state and small signal
inductor current. In the case of multiphase converters, the
operation.
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the PWM Operation
expression for the peak-to-peak current after the summation The timing of each channel is set by the number of active
of N symmetrically phase-shifted inductor currents in channels. The default channel setting for the ISL6326 is four.
Equation 2. Peak-to-peak ripple current decreases by an The switching cycle is defined as the time between PWM
amount proportional to the number of channels. Output pulse termination signals of each channel. The cycle time of
voltage ripple is a function of capacitance, capacitor the pulse signal is the inverse of the switching frequency set
equivalent series resistance (ESR), and inductor ripple by the resistor between the FS pin and ground. The PWM
current. Reducing the inductor ripple current allows the signals command the MOSFET driver to turn on/off the
designer to use fewer or less costly output capacitors. channel MOSFETs.
( V IN – N V OUT ) V OUT
I C, PP = -----------------------------------------------------------
- (EQ. 2) For 4-channel operation, the channel firing order is 4-3-2-1:
L fS V
IN PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
Another benefit of interleaving is to reduce input ripple
PWM1 delays another 1/4 of a cycle after PWM2. For
current. Input capacitance is determined in part by the
3-channel operation, the channel firing order is 3-2-1.
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple Connecting PWM4 to VCC selects three channel operation
current and allowing the designer to reduce the cost of input and the pulse times are spaced in 1/3 cycle increments. If
capacitance. The example in Figure 2 illustrates input PWM3 is connected to VCC, two channel operation is
currents from a three-phase converter combining to reduce selected and the PWM2 pulse happens 1/2 of a cycle after
the total input ripple current. PWM pulse.
The converter depicted in Figure 2 delivers 36A to a 1.5V load Switching Frequency
from a 12V input. The RMS input capacitor current is 5.9A. Switching frequency is determined by the selection of the
Compare this to a single-phase converter also stepping down frequency-setting resistor, RT, which is connected from FS
12V to 1.5V at 36A. The single-phase converter has 11.9A pin to GND (see the figures labelled Typical Applications on

11 FN9262.0
April 21, 2006
 ISL6326

pages 4 and 5). Equation 3 is provided to assist in selecting VIN

I (s)
the correct resistor value. L

L
DCR VOUT
10
2.5X10 ISL6605
R T = -------------------------- (EQ. 3) INDUCTOR
F SW COUT
VL -

+
where FSW is the switching frequency of each phase. VC(s) -

+
Current Sensing R C
ISL6326 senses the current continuously for fast response. PWM(n)

ISL6326 supports inductor DCR sensing, or resistive

ISL6326 INTERNAL CIRCUIT
sensing techniques. The associated channel current sense
amplifier uses the ISEN inputs to reproduce a signal RISEN(n)
(PTC)
proportional to the inductor current, IL. The sense current, In
ISEN, is proportional to the inductor current. The sensed
current is used for current balance, load-line regulation, and CURRENT
overcurrent protection. SENSE ISEN-(n)
+
The internal circuitry, shown in Figures 3, and 4, represents
one channel of an N-channel converter. This circuitry is -

repeated for each channel in the converter, but may not be ISEN+(n) CT
active depending on the status of the PWM3 and PWM4
DCR
I SEN = I -----------------
pins, as described in the PWM Operation section. LR
-
ISEN
INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed FIGURE 3. DCR SENSING CONFIGURATION
resistance as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a With the internal low-offset current amplifier, the capacitor
separate lumped quantity, as shown in Figure 3. The voltage VC is replicated across the sense resistor RISEN.
channel current IL, flowing through the inductor, will also Therefore, the current out of ISEN+ pin, ISEN, is proportional
pass through the DCR. Equation 4 shows the s-domain to the inductor current.
equivalent voltage across the inductor VL.
Because of the internal filter at ISEN- pin, one capacitor, CT,
V L = I L ⋅ ( s ⋅ L + DCR ) (EQ. 4) is needed to match the time delay between the ISEN- and
ISEN+ signals. Select the proper CT to keep the time
constant of RISEN and CT (RISEN x CT ) close to 27ns.
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 3. Equation 6 shows that the ratio of the channel current to the
sensed current, ISEN, is driven by the value of the sense
The voltage on the capacitor VC, can be shown to be
resistor and the DCR of the inductor.
proportional to the channel current IL, see Equation 5.
⎛ s ⋅ ------------- DCR
+ 1⎞ ⋅ ( DCR ⋅ I L )
L I SEN = I L ⋅ ------------------ (EQ. 6)
⎝ DCR ⎠ (EQ. 5) R ISEN
V C = ---------------------------------------------------------------------
( s ⋅ RC + 1 )
RESISTIVE SENSING
If the R-C network components are selected such that the
RC time constant (= R*C) matches the inductor time For accurate current sense, a dedicated current-sense
constant (= L/DCR), the voltage across the capacitor VC is resistor RSENSE in series with each output inductor can
equal to the voltage drop across the DCR, i.e., proportional serve as the current sense element (see Figure 4). This
to the channel current. technique is more accurate, but reduces overall converter
efficiency due to the additional power loss on the current
sense element RSENSE.

The same capacitor CT is needed to match the time delay

between ISEN- and ISEN+ signals. Select the proper CT to
keep the time constant of RISEN and CT (RISEN x CT ) close
to 27ns.

12 FN9262.0
April 21, 2006
 ISL6326

Equation 7 shows the ratio of the channel current to the The output of the error amplifier, VCOMP, is compared to
sensed current ISEN. sawtooth waveforms to generate the PWM signals. The
R SENSE
PWM signals control the timing of the Intersil MOSFET
I SEN = I L ⋅ ----------------------- (EQ. 7) drivers and regulate the converter output to the specified
R ISEN
reference voltage. The internal and external circuitry which
I
control voltage regulation is illustrated in Figure 5.
L
L
RSENSE VOUT
EXTERNAL CIRCUIT ISL6326 INTERNAL CIRCUIT
COUT R C CC
COMP
ISL6326 INTERNAL CIRCUIT
DAC
RISEN(n) RREF
In REF
CREF +
CURRENT
SENSE ISEN-(n) - VCOMP
FB
+

- IAVG ERROR AMPLIFIER

+ IDROOP
ISEN+(n) RFB VDROOP
CT -
VDIFF
R SENSE
I
SEN = I L -------------------------
R ISEN
-

VSEN
VOUT+
FIGURE 4. SENSE RESISTOR IN SERIES WITH INDUCTORS +

The inductor DCR value will increase as the temperature VOUT- RGND -
increases. Therefore the sensed current will increase as the
DIFFERENTIAL
temperature of the current sense element increases. In order REMOTE-SENSE
to compensate the temperature effect on the sensed current AMPLIFIER

signal, a Positive Temperature Coefficient (PTC) resistor can FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
be selected for the sense resistor RISEN, or the integrated REGULATION WITH OFFSET ADJUSTMENT
temperature compensation function of ISL6326 should be
utilized. The integrated temperature compensation function The ISL6326 incorporates an internal differential remote-
is described in the Temperature Compensation section. sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
Channel-Current Balance
voltage relative to the local controller ground reference point
The sensed current In from each active channel are summed resulting in a more accurate means of sensing output
together and divided by the number of active channels. The voltage. Connect the microprocessor sense pins to the
resulting average current IAVG provides a measure of the non-inverting input, VSEN, and inverting input, RGND, of the
total load current. Channel current balance is achieved by remote-sense amplifier. The remote-sense output, VDIFF, is
comparing the sensed current of each channel to the connected to the inverting input of the error amplifier through
average current to make an appropriate adjustment to the an external resistor.
PWM duty cycle of each channel with Intersil’s patented
current-balance method. A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
Channel current balance is essential in achieving the through VID0. The DAC decodes the eight 6-bit logic signal
thermal advantage of multiphase operation. With good (VID) into one of the discrete voltages shown in Table 1.
current balance, the power loss is equally dissipated over Each VID input offers a 45µA pull-up to an internal 2.5V
multiple devices and a greater area. source for use with open-drain outputs. The pull-up current
Voltage Regulation diminishes to zero above the logic threshold to protect
voltage-sensitive output devices. External pull-up resistors
The compensation network shown in Figure 5 assures that
can augment the pull-up current sources if case leakage into
the steady-state error in the output voltage is limited only to
the driving device is greater than 45µA.
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6326 to include the combined tolerances of each of
these elements.

13 FN9262.0
April 21, 2006
 ISL6326

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
(Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V)

0 1 0 1 0 1 1 1.6 1 0 1 0 0 0 1 1.3625

0 1 0 1 0 1 0 1.59375 1 0 1 0 0 0 0 1.35625

0 1 0 1 1 0 1 1.5875 1 0 1 0 0 1 1 1.35

0 1 0 1 1 0 0 1.58125 1 0 1 0 0 1 0 1.34375

0 1 0 1 1 1 1 1.575 1 0 1 0 1 0 1 1.3375

0 1 0 1 1 1 0 1.56875 1 0 1 0 1 0 0 1.33125

0 1 1 0 0 0 1 1.5625 1 0 1 0 1 1 1 1.325

0 1 1 0 0 0 0 1.55625 1 0 1 0 1 1 0 1.31875

0 1 1 0 0 1 1 1.55 1 0 1 1 0 0 1 1.3125

0 1 1 0 0 1 0 1.54375 1 0 1 1 0 0 0 1.30625

0 1 1 0 1 0 1 1.5375 1 0 1 1 0 1 1 1.3

0 1 1 0 1 0 0 1.53125 1 0 1 1 0 1 0 1.29375

0 1 1 0 1 1 1 1.525 1 0 1 1 1 0 1 1.2875

0 1 1 0 1 1 0 1.51875 1 0 1 1 1 0 0 1.28125

0 1 1 1 0 0 1 1.5125 1 0 1 1 1 1 1 1.275

0 1 1 1 0 0 0 1.50625 1 0 1 1 1 1 0 1.26875

0 1 1 1 0 1 1 1.5 1 1 0 0 0 0 1 1.2625

0 1 1 1 0 1 0 1.49375 1 1 0 0 0 0 0 1.25625

0 1 1 1 1 0 1 1.4875 1 1 0 0 0 1 1 1.25

0 1 1 1 1 0 0 1.48125 1 1 0 0 0 1 0 1.24375

0 1 1 1 1 1 1 1.475 1 1 0 0 1 0 1 1.2375

0 1 1 1 1 1 0 1.46875 1 1 0 0 1 0 0 1.23125

1 0 0 0 0 0 1 1.4625 1 1 0 0 1 1 1 1.225

1 0 0 0 0 0 0 1.45625 1 1 0 0 1 1 0 1.21875

1 0 0 0 0 1 1 1.45 1 1 0 1 0 0 1 1.2125

1 0 0 0 0 1 0 1.44375 1 1 0 1 0 0 0 1.20625

1 0 0 0 1 0 1 1.4375 1 1 0 1 0 1 1 1.2

1 0 0 0 1 0 0 1.43125 1 1 0 1 0 1 0 1.19375

1 0 0 0 1 1 1 1.425 1 1 0 1 1 0 1 1.1875

1 0 0 0 1 1 0 1.41875 1 1 0 1 1 0 0 1.18125

1 0 0 1 0 0 1 1.4125 1 1 0 1 1 1 1 1.175

1 0 0 1 0 0 0 1.40625 1 1 0 1 1 1 0 1.16875

1 0 0 1 0 1 1 1.4 1 1 1 0 0 0 1 1.1625

1 0 0 1 0 1 0 1.39375 1 1 1 0 0 0 0 1.15625

1 0 0 1 1 0 1 1.3875 1 1 1 0 0 1 1 1.15

1 0 0 1 1 0 0 1.38125 1 1 1 0 0 1 0 1.14375

1 0 0 1 1 1 1 1.375 1 1 1 0 1 0 1 1.1375

1 0 0 1 1 1 0 1.36875 1 1 1 0 1 0 0 1.13125

1 1 1 0 1 1 1 1.125

14 FN9262.0
April 21, 2006
 ISL6326

TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION) TABLE 1. VR10 VID TABLE (WITH 6.25mV EXTENSION)
(Continued) (Continued)

VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V) 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V)

1 1 1 0 1 1 0 1.11875 0 0 1 1 1 1 1 0.9

1 1 1 1 0 0 1 1.1125 0 0 1 1 1 1 0 0.89375

1 1 1 1 0 0 0 1.10625 0 1 0 0 0 0 1 0.8875

1 1 1 1 0 1 1 1.1 0 1 0 0 0 0 0 0.88125

1 1 1 1 0 1 0 1.09375 0 1 0 0 0 1 1 0.875

1 1 1 1 1 0 1 OFF 0 1 0 0 0 1 0 0.86875

1 1 1 1 1 0 0 OFF 0 1 0 0 1 0 1 0.8625

1 1 1 1 1 1 1 OFF 0 1 0 0 1 0 0 0.85625

1 1 1 1 1 1 0 OFF 0 1 0 0 1 1 1 0.85

0 0 0 0 0 0 1 1.0875 0 1 0 0 1 1 0 0.84375

0 0 0 0 0 0 0 1.08125 0 1 0 1 0 0 1 0.8375

0 0 0 0 0 1 1 1.075 0 1 0 1 0 0 0 0.83125
0 0 0 0 0 1 0 1.06875
TABLE 2. VR11 VID 8 BIT
0 0 0 0 1 0 1 1.0625
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
0 0 0 0 1 0 0 1.05625
0 0 0 0 0 0 0 0 OFF
0 0 0 0 1 1 1 1.05
0 0 0 0 0 0 0 1 OFF
0 0 0 0 1 1 0 1.04375
0 0 0 0 0 0 1 0 1.60000
0 0 0 1 0 0 1 1.0375
0 0 0 0 0 0 1 1 1.59375
0 0 0 1 0 0 0 1.03125
0 0 0 0 0 1 0 0 1.58750
0 0 0 1 0 1 1 1.025
0 0 0 0 0 1 0 1 1.58125
0 0 0 1 0 1 0 1.01875
0 0 0 0 0 1 1 0 1.57500
0 0 0 1 1 0 1 1.0125
0 0 0 0 0 1 1 1 1.56875
0 0 0 1 1 0 0 1.00625
0 0 0 0 1 0 0 0 1.56250
0 0 0 1 1 1 1 1
0 0 0 0 1 0 0 1 1.55625
0 0 0 1 1 1 0 0.99375
0 0 0 0 1 0 1 0 1.55000
0 0 1 0 0 0 1 0.9875
0 0 0 0 1 0 1 1 1.54375
0 0 1 0 0 0 0 0.98125
0 0 0 0 1 1 0 0 1.53750
0 0 1 0 0 1 1 0.975
0 0 0 0 1 1 0 1 1.53125
0 0 1 0 0 1 0 0.96875
0 0 0 0 1 1 1 0 1.52500
0 0 1 0 1 0 1 0.9625
0 0 0 0 1 1 1 1 1.51875
0 0 1 0 1 0 0 0.95625
0 0 0 1 0 0 0 0 1.51250
0 0 1 0 1 1 1 0.95
0 0 0 1 0 0 0 1 1.50625
0 0 1 0 1 1 0 0.94375
0 0 0 1 0 0 1 0 1.50000
0 0 1 1 0 0 1 0.9375
0 0 0 1 0 0 1 1 1.49375
0 0 1 1 0 0 0 0.93125
0 0 0 1 0 1 0 0 1.48750
0 0 1 1 0 1 1 0.925
0 0 0 1 0 1 0 1 1.48125
0 0 1 1 0 1 0 0.91875
0 0 0 1 0 1 1 0 1.47500
0 0 1 1 1 0 1 0.9125
0 0 0 1 0 1 1 1 1.46875
0 0 1 1 1 0 0 0.90625

15 FN9262.0
April 21, 2006
 ISL6326

TABLE 2. VR11 VID 8 BIT (Continued) TABLE 2. VR11 VID 8 BIT (Continued)

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0 0 0 1 1 0 0 0 1.46250 0 1 0 0 0 0 0 0 1.21250

0 0 0 1 1 0 0 1 1.45625 0 1 0 0 0 0 0 1 1.20625

0 0 0 1 1 0 1 0 1.45000 0 1 0 0 0 0 1 0 1.20000

0 0 0 1 1 0 1 1 1.44375 0 1 0 0 0 0 1 1 1.19375

0 0 0 1 1 1 0 0 1.43750 0 1 0 0 0 1 0 0 1.18750

0 0 0 1 1 1 0 1 1.43125 0 1 0 0 0 1 0 1 1.18125

0 0 0 1 1 1 1 0 1.42500 0 1 0 0 0 1 1 0 1.17500

0 0 0 1 1 1 1 1 1.41875 0 1 0 0 0 1 1 1 1.16875
0 0 1 0 0 0 0 0 1.41250 0 1 0 0 1 0 0 0 1.16250

0 0 1 0 0 0 0 1 1.40625 0 1 0 0 1 0 0 1 1.15625

0 0 1 0 0 0 1 0 1.40000 0 1 0 0 1 0 1 0 1.15000

0 0 1 0 0 0 1 1 1.39375 0 1 0 0 1 0 1 1 1.14375

0 0 1 0 0 1 0 0 1.38750 0 1 0 0 1 1 0 0 1.13750

0 0 1 0 0 1 0 1 1.38125 0 1 0 0 1 1 0 1 1.13125
0 0 1 0 0 1 1 0 1.37500 0 1 0 0 1 1 1 0 1.12500

0 0 1 0 0 1 1 1 1.36875 0 1 0 0 1 1 1 1 1.11875

0 0 1 0 1 0 0 0 1.36250 0 1 0 1 0 0 0 0 1.11250

0 0 1 0 1 0 0 1 1.35625 0 1 0 1 0 0 0 1 1.10625

0 0 1 0 1 0 1 0 1.35000 0 1 0 1 0 0 1 0 1.10000

0 0 1 0 1 0 1 1 1.34375 0 1 0 1 0 0 1 1 1.09375

0 0 1 0 1 1 0 0 1.33750 0 1 0 1 0 1 0 0 1.08750

0 0 1 0 1 1 0 1 1.33125 0 1 0 1 0 1 0 1 1.08125

0 0 1 0 1 1 1 0 1.32500 0 1 0 1 0 1 1 0 1.07500

0 0 1 0 1 1 1 1 1.31875 0 1 0 1 0 1 1 1 1.06875
0 0 1 1 0 0 0 0 1.31250 0 1 0 1 1 0 0 0 1.06250

0 0 1 1 0 0 0 1 1.30625 0 1 0 1 1 0 0 1 1.05625

0 0 1 1 0 0 1 0 1.30000 0 1 0 1 1 0 1 0 1.05000
0 0 1 1 0 0 1 1 1.29375 0 1 0 1 1 0 1 1 1.04375

0 0 1 1 0 1 0 0 1.28750 0 1 0 1 1 1 0 0 1.03750

0 0 1 1 0 1 0 1 1.28125 0 1 0 1 1 1 0 1 1.03125

0 0 1 1 0 1 1 0 1.27500 0 1 0 1 1 1 1 0 1.02500

0 0 1 1 0 1 1 1 1.26875 0 1 0 1 1 1 1 1 1.01875

0 0 1 1 1 0 0 0 1.26250 0 1 1 0 0 0 0 0 1.01250
0 0 1 1 1 0 0 1 1.25625 0 1 1 0 0 0 0 1 1.00625

0 0 1 1 1 0 1 0 1.25000 0 1 1 0 0 0 1 0 1.00000

0 0 1 1 1 0 1 1 1.24375 0 1 1 0 0 0 1 1 0.99375

0 0 1 1 1 1 0 0 1.23750 0 1 1 0 0 1 0 0 0.98750

0 0 1 1 1 1 0 1 1.23125 0 1 1 0 0 1 0 1 0.98125

0 0 1 1 1 1 1 0 1.22500 0 1 1 0 0 1 1 0 0.97500
0 0 1 1 1 1 1 1 1.21875 0 1 1 0 0 1 1 1 0.96875

16 FN9262.0
April 21, 2006
 ISL6326

TABLE 2. VR11 VID 8 BIT (Continued) TABLE 2. VR11 VID 8 BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE

0 1 1 0 1 0 0 0 0.96250 1 0 0 1 0 0 0 0 0.71250

0 1 1 0 1 0 0 1 0.95625 1 0 0 1 0 0 0 1 0.70625

0 1 1 0 1 0 1 0 0.95000 1 0 0 1 0 0 1 0 0.70000

0 1 1 0 1 0 1 1 0.94375 1 0 0 1 0 0 1 1 0.69375

0 1 1 0 1 1 0 0 0.93750 1 0 0 1 0 1 0 0 0.68750

0 1 1 0 1 1 0 1 0.93125 1 0 0 1 0 1 0 1 0.68125

0 1 1 0 1 1 1 0 0.92500 1 0 0 1 0 1 1 0 0.67500

0 1 1 0 1 1 1 1 0.91875 1 0 0 1 0 1 1 1 0.66875
0 1 1 1 0 0 0 0 0.91250 1 0 0 1 1 0 0 0 0.66250

0 1 1 1 0 0 0 1 0.90625 1 0 0 1 1 0 0 1 0.65625

0 1 1 1 0 0 1 0 0.90000 1 0 0 1 1 0 1 0 0.65000

0 1 1 1 0 0 1 1 0.89375 1 0 0 1 1 0 1 1 0.64375

0 1 1 1 0 1 0 0 0.88750 1 0 0 1 1 1 0 0 0.63750

0 1 1 1 0 1 0 1 0.88125 1 0 0 1 1 1 0 1 0.63125
0 1 1 1 0 1 1 0 0.87500 1 0 0 1 1 1 1 0 0.62500

0 1 1 1 0 1 1 1 0.86875 1 0 0 1 1 1 1 1 0.61875

0 1 1 1 1 0 0 0 0.86250 1 0 1 0 0 0 0 0 0.61250

0 1 1 1 1 0 0 1 0.85625 1 0 1 0 0 0 0 1 0.60625

0 1 1 1 1 0 1 0 0.85000 1 0 1 0 0 0 1 0 0.60000

0 1 1 1 1 0 1 1 0.84375 1 0 1 0 0 0 1 1 0.59375

0 1 1 1 1 1 0 0 0.83750 1 0 1 0 0 1 0 0 0.58750

0 1 1 1 1 1 0 1 0.83125 1 0 1 0 0 1 0 1 0.58125

0 1 1 1 1 1 1 0 0.82500 1 0 1 0 0 1 1 0 0.57500

0 1 1 1 1 1 1 1 0.81875 1 0 1 0 0 1 1 1 0.56875
1 0 0 0 0 0 0 0 0.81250 1 0 1 0 1 0 0 0 0.56250

1 0 0 0 0 0 0 1 0.80625 1 0 1 0 1 0 0 1 0.55625

1 0 0 0 0 0 1 0 0.80000 1 0 1 0 1 0 1 0 0.55000
1 0 0 0 0 0 1 1 0.79375 1 0 1 0 1 0 1 1 0.54375

1 0 0 0 0 1 0 0 0.78750 1 0 1 0 1 1 0 0 0.53750

1 0 0 0 0 1 0 1 0.78125 1 0 1 0 1 1 0 1 0.53125

1 0 0 0 0 1 1 0 0.77500 1 0 1 0 1 1 1 0 0.52500

1 0 0 0 0 1 1 1 0.76875 1 0 1 0 1 1 1 1 0.51875

1 0 0 0 1 0 0 0 0.76250 1 0 1 1 0 0 0 0 0.51250
1 0 0 0 1 0 0 1 0.75625 1 0 1 1 0 0 0 1 0.50625

1 0 0 0 1 0 1 0 0.75000 1 0 1 1 0 0 1 0 0.50000

1 0 0 0 1 0 1 1 0.74375 1 1 1 1 1 1 1 0 OFF

1 0 0 0 1 1 0 0 0.73750 1 1 1 1 1 1 1 1 OFF

1 0 0 0 1 1 0 1 0.73125

1 0 0 0 1 1 1 0 0.72500
1 0 0 0 1 1 1 1 0.71875

17 FN9262.0
April 21, 2006
 ISL6326

Load-Line Regulation Output Voltage Offset Programming

Some microprocessor manufacturers require a precisely- The ISL6326 allows the designer to accurately adjust the
controlled output resistance. This dependence of output offset voltage. When a resistor, ROFS, is connected between
voltage on load current is often termed “droop” or “load line” OFS to VCC, the voltage across it is regulated to 1.6V. This
regulation. By adding a well controlled output impedance, causes a proportional current (IOFS) to flow into OFS. If
the output voltage can effectively be level shifted in a ROFS is connected to ground, the voltage across it is
direction which works to achieve the load-line regulation regulated to 0.4V, and IOFS flows out of OFS. A resistor
required by these manufacturers. between DAC and REF, RREF, is selected so that the
product (IOFS x ROFS) is equal to the desired offset voltage.
In other cases, the designer may determine that a more
These functions are shown in Figure 6.
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that Once the desired output offset voltage has been determined,
results from fast load-current demand changes. use the following formulas to set ROFS:
The magnitude of the spike is dictated by the ESR and ESL For Positive Offset (connect ROFS to VCC):
of the output capacitors selected. By positioning the no-load 1.6 × R REF
voltage level near the upper specification limit, a larger R OFS = ------------------------------ (EQ. 11)
V OFFSET
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
For Negative Offset (connect ROFS to GND):
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without 0.4 × R REF
crossing the upper specification limit. R OFS = ------------------------------ (EQ. 12)
V OFFSET

As shown in Figure 5, a current proportional to the average

current of all active channels, IAVG, flows from FB through a FB
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as DYNAMIC DAC
VID D/A
V DROOP = I AVG R FB (EQ. 8) RREF

E/A
The regulated output voltage is reduced by the droop voltage REF

VDROOP. The output voltage as a function of load current is CREF

derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
⎛ I OUT R X ⎞ VCC
V OUT = V REF – V OFS – ⎜ ------------
- ------------------ R FB⎟ (EQ. 9) OR
⎝ N R ISEN ⎠ GND

-
Where VREF is the reference voltage, VOFS is the 1.6V ROFS
programmed offset voltage, IOUT is the total output current + +
of the converter, RISEN is the sense resistor connected to 0.4V
- OFS
the ISEN+ pin, and RFB is the feedback resistor, N is the ISL6326B
active channel number, and RX is the DCR, or RSENSE VCC GND
depending on the sensing method.
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
R FB R X
R LL = ------------ ------------------ (EQ. 10)
N R ISEN

18 FN9262.0
April 21, 2006
 ISL6326

Dynamic VID family of Intersil MOSFET drivers, which require 12V

Modern microprocessors need to make changes to their bias.
core voltage as part of normal operation. They direct the 3. The voltage on EN_VTT must be higher than 0.875V to
core voltage regulator to do this by making changes to the enable the controller. This pin is typically connected to the
VID inputs during regulator operation. The power output of VTT VR.
management solution is required to monitor the DAC inputs ISL6326 INTERNAL CIRCUIT EXTERNAL CIRCUIT
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within VCC +12V
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core voltage 10kΩ
POR ENABLE
regulator. CIRCUIT COMPARATOR
EN_PWR
In order to ensure the smooth transition of output voltage +
during VID change, a VID step change smoothing network, -
composed of RREF and CREF as shown in Figure 6, can be 910Ω

used. The selection of RREF is based on the desired offset 0.875V

voltage as detailed above in Output Voltage Offset
Programming. The selection of CREF is based on the time
+ EN_VTT
duration for 1 bit VID change and the allowable delay time.

Assuming the microprocessor controls the VID change at 1 -

bit every TVID, the relationship between the time constant of

RREF and CREF network and TVID is given by the following 0.875V
equation.
SOFT-START
C REF R REF = T VID (EQ. 13)
AND
FAULT LOGIC

Operation Initialization
FIGURE 7. POWER SEQUENCING USING THRESHOLD-
Prior to converter initialization, proper conditions must exist
SENSITIVE ENABLE (EN) FUNCTION
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is When all conditions above are satisfied, ISL6326 begins the
within the proper window of operation, VR_RDY asserts soft-start and ramps the output voltage to 1.1V first. After
logic high. remaining at 1.1V for some time, ISL6326 reads the VID
code at VID input pins. If the VID code is valid, ISL6326 will
Enable and Disable regulate the output to the final VID setting. If the VID code is
While in shutdown mode, the PWM outputs are held in a OFF code, ISL6326 will shut down, and cycling VCC,
high-impedance state to assure the drivers remain off. The EN_PWR or EN_VTT is needed to restart.
following input conditions must be met before the ISL6326 is
released from shutdown mode. Soft-Start
ISL6326 based VR has 4 periods during soft-start as shown
1. The bias voltage applied at VCC must reach the internal
in Figure 8. After VCC, EN_VTT and EN_PWR reach their
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of POR/enable thresholds, The controller will have fixed delay
the ISL6326 is guaranteed. Hysteresis between the rising period TD1. After this delay period, the VR will begin first
and falling thresholds assure that once enabled, the soft-start ramp until the output voltage reaches 1.1V Vboot
ISL6326 will not inadvertently turn off unless the bias voltage. Then, the controller will regulate the VR voltage at
voltage drops substantially (see Electrical 1.1V for another fixed period TD3. At the end of TD3 period,
Specifications). ISL6326 reads the VID signals. If the VID code is valid,
2. The ISL6326 features an enable input (EN_PWR) for ISL6326 will initiate the second soft-start ramp until the
power sequencing between the controller bias voltage voltage reaches the VID voltage minus offset voltage.
and another voltage rail. The enable comparator holds
the ISL6326 in shutdown until the voltage at EN_PWR The soft-start time is the sum of the 4 periods as shown in
rises above 0.875V. The enable comparator has about the following equation.
130mV of hysteresis to prevent bounce. It is important
T SS = TD1 + TD2 + TD3 + TD4 (EQ. 14)
that the driver ICs reach their POR level before the
ISL6326 becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6326 with the ISL66xx TD1 is a fixed delay with the typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid

19 FN9262.0
April 21, 2006
 ISL6326

VID voltage. If the VID is valid before the output reaches the when an undervoltage or overvoltage condition is detected,
1.1V, the minimum time to validate the VID input is 500ns. or the controller is disabled by a reset from EN_PWR,
Therefore the minimum TD3 is about 86µs. EN_VTT, POR, or VID OFF-code.

During TD2 and TD4, ISL6326 digitally controls the DAC Undervoltage Detection
voltage change at 6.25mV per step. The time for each step is The undervoltage threshold is set at 50% of the VID code.
determined by the frequency of the soft-start oscillator which When the output voltage at VSEN is below the undervoltage
is defined by the resistor Rss from SS pin to GND. The threshold, VR_RDY is pulled low.
second soft-start ramp time TD2 and TD4 can be calculated
based on the following equations: Overvoltage Protection
1.1xR SS Regardless of the VR being enabled or not, the ISL6326
TD2 = ------------------------ ( μs ) (EQ. 15)
6.25x25 overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
( V VID – 1.1 )xR SS operation conditions. When VR is not enabled and during
TD4 = ------------------------------------------------ ( μs ) (EQ. 16)
6.25x25 the soft-start intervals TD1, TD2 and TD3, the OVP
threshold is 1.275V. Once the controller detects valid VID
For example, when VID is set to 1.5V and the Rss is set at input, the OVP trip point will be changed to DAC plus
100kΩ, the first soft-start ramp time TD2 will be 704µs and 175mV.
the second soft-start ramp time TD4 will be 256µs.
Two actions are taken by the ISL6326 to protect the
After the DAC voltage reaches the final VID setting, microprocessor load when an overvoltage condition occurs.
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85µs. At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
VOUT, 500mV/DIV PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326 will again command the lower
MOSFETs to turn on. The ISL6326 will continue to protect
TD1 TD2 TD3 TD4 TD5
the load in this fashion as long as the overvoltage condition
occurs.
EN_VTT
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6326 is reset. Cycling the
VR_RDY
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
500µs/DIV VID codes will not reset the controller.
FIGURE 8. SOFT-START WAVEFORMS

Fault Monitoring and Protection

The ISL6326 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.

VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful
soft-start and a fixed delay TD5. VR_RDY will be pulled low

20 FN9262.0
April 21, 2006
 ISL6326

VR_RDY

OUTPUT CURRENT

UV
+
-

50% 0A

DAC SOFT-START, FAULT - 85µA

OC OUTPUT VOLTAGE
AND CONTROL LOGIC
+ IAVG

VDIFF + 0V
2ms/DIV
OV
- FIGURE 10. OVERCURRENT BEHAVIOR IN HICCUP MODE.
FSW = 500kHz
VID + 0.175V
For the individual channel overcurrent protection, the
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
ISL6326 continuously compares the sensed current signal of
Overcurrent Protection each channel with the 120µA reference current. If one
channel current exceeds the reference current, ISL6326 will
ISL6326 has two levels of overcurrent protection. Each
pull PWM signal of this channel to low for the rest of the
phase is protected from a sustained overcurrent condition by
switching cycle. This PWM signal can be turned on next
limiting its peak current, while the combined phase currents
cycle if the sensed channel current is less than the 120µA
are protected on an instantaneous basis.
reference current. The peak current limit of individual
In instantaneous protection mode, the ISL6326 utilizes the channel will not trigger the converter to shutdown.
sensed average current IAVG to detect an overcurrent
condition. See the Channel-Current Balance section for Thermal Monitoring (VR_HOT/VR_FAN)
more detail on how the average current is measured. The There are two thermal signals to indicate the temperature
average current is continually compared with a constant status of the voltage regulator: VR_HOT and VR_FAN. Both
85µA reference current, as shown in Figure 9. Once the VR_FAN and VR_HOT pins are open-drain outputs, and
average current exceeds the reference current, a external pull-up resistors are required. Those signals are
comparator triggers the converter to shutdown. valid only after the controller is enabled.
At the beginning of overcurrent shutdown, the controller The VR_FAN signal indicates that the temperature of the
places all PWM signals in a high-impedance state within voltage regulator is high and more cooling airflow is needed.
20ns, commanding the Intersil MOSFET driver ICs to turn off The VR_HOT signal can be used to inform the system that
both upper and lower MOSFETs. The system remains in this the temperature of the voltage regulator is too high and the
state a period of 4096 switching cycles. If the controller is still CPU should reduce its power consumption. The VR_HOT
enabled at the end of this wait period, it will attempt a soft- signal may be tied to the CPU’s PROC_HOT signal.
start. If the fault remains, the trip-retry cycles will continue
indefinitely (as shown in Figure 10) until either controller is The diagram of thermal monitoring function block is shown in
disabled or the fault is cleared. Note that the energy Figure 11. One NTC resistor should be placed close to the
delivered during trip-retry cycling is much less than during power stage of the voltage regulator to sense the operational
full-load operation, so there is no thermal hazard during this temperature, and one pull-up resistor is needed to form the
kind of operation. voltage divider for the TM pin. As the temperature of the
power stage increases, the resistance of the NTC will
reduce, resulting in the reduced voltage at the TM pin.
Figure 12 shows the TM voltage over the temperature for a
typical design with a recommended 6.8kΩ NTC (P/N:
NTHS0805N02N6801 from Vishay) and 1kΩ resistor RTM1.
We recommend using those resistors for the accurate
temperature compensation.

There are two comparators with hysteresis to compare the

TM pin voltage to the fixed thresholds for VR_FAN and

21 FN9262.0
April 21, 2006
 ISL6326

VR_HOT signals respectively. The VR_FAN signal is set to

high when the TM voltage is lower than 33% of VCC voltage,
TM
and is pulled to GND when the TM voltage increases to
above 39% of VCC voltage. The VR_FAN signal is set to 0.39*Vcc
high when the TM voltage goes below 28% of VCC voltage, 0.33*Vcc
and is pulled to GND when the TM voltage goes back to 0.28*Vcc

above 33% of VCC voltage. Figure 13 shows the operation

of those signals. VR_FAN

VR_HOT Temperature

VCC T1 T2 T3
VR_FAN
FIGURE 13. VR_HOT AND VR_FAN SIGNAL vs TM VOLTAGE

Based on the NTC temperature characteristics and the

RTM1 0.33VCC desired threshold of the VR_HOT signal, the pull-up resistor
VR_HOT RTM1 of TM pin is given by:
TM
R TM1 = 2.75xR NTC ( T3 ) (EQ. 17)
oc RNTC
0.28VCC RNTC(T3) is the NTC resistance at the VR_HOT threshold
temperature T3.
FIGURE 11. BLOCK DIAGRAM OF THERMAL MONITORING
The NTC resistance at the set point T2 and release point T1
FUNCTION
of VR_FAN signal can be calculated as:

R NTC ( T2 ) = 1.267xR NTC ( T3 ) (EQ. 18)

V TM / V CC vs. Tem perature

R NTC ( T1 ) = 1.644xR NTC ( T3 ) (EQ. 19)
100%

90%
With the NTC resistance value obtained from Equations 17
80%
and 18, the temperature value T2 and T1 can be found from
70% the NTC datasheet.
V TM / V CC

60%
Temperature Compensation
50%
ISL6326 supports inductor DCR sensing, or resistive
40% sensing techniques. The inductor DCR has a positive
30% temperature coefficient, which is about +0.38%/°C. Since the
voltage across inductor is sensed for the output current
20%
information, the sensed current has the same positive
0 20 40 60 80 100 120 140
temperature coefficient as the inductor DCR.
Tem perature ( oC)
In order to obtain the correct current information, there
FIGURE 12. THE RATIO OF TM VOLTAGE TO NTC should be a way to correct the temperature impact on the
TEMPERATURE WITH RECOMMENDED PARTS
current sense component. ISL6326 provides two methods:
integrated temperature compensation and external
temperature compensation.

Integrated Temperature Compensation

When the TCOMP voltage is equal or greater than VCC/15,
ISL6326 will utilize the voltage at TM and TCOMP pins to
compensate the temperature impact on the sensed current.
The block diagram of this function is shown in Figure 14.

22 FN9262.0
April 21, 2006
 ISL6326

ISL6326 multiplexes the TCOMP factor N with the TM digital

signal to obtain the adjustment gain to compensate the
VCC
temperature impact on the sensed channel current. The
Isen4 compensated channel current signal is used for droop and
RTM1 Channel current Isen3 overcurrent protection functions.
sense Isen2
TM Non-linear Isen1
Design Procedure
A/D 1. Properly choose the voltage divider for the TM pin to
I4 I3 I2 I1
oc RNTC match the TM voltage vs temperature curve with the
recommended curve in Figure 12.
ki 2. Run the actual board under the full load and the desired
D/A cooling condition.
VCC
3. After the board reaches the thermal steady state, record
RTC1 the temperature (TCSC) of the current sense component
(inductor or MOSFET) and the voltage at TM and VCC
TCOMP 4-bit
Droop & pins.
A/D
Over current protection
4. Use the following equation to calculate the resistance of
RTC2 the TM NTC, and find out the corresponding NTC
temperature TNTC from the NTC datasheet.
V TM xR
TM1
FIGURE 14. BLOCK DIAGRAM OF INTEGRATED R NTC ( T ) = -------------------------------
- (EQ. 20)
NTC V CC – V
TEMPERATURE COMPENSATION TM

5. Use the following equation to calculate the TCOMP

When the TM NTC is placed close to the current sense factor N:
component (inductor), the temperature of the NTC will track 209x ( T CSC – T )
the temperature of the current sense component. Therefore NTC (EQ. 21)
N = -------------------------------------------------------- + 4
3xTNTC + 400
the TM voltage can be utilized to obtain the temperature of
the current sense component. 6. Choose an integral number close to the above result for
the TCOMP factor. If this factor is higher than 15, use
Based on VCC voltage, ISL6326 converts the TM pin voltage
N = 15. If it is less than 1, use N = 1.
to a 6-bit TM digital signal for temperature compensation.
7. Choose the pull-up resistor RTC1 (typical 10kΩ).
With the non-linear A/D converter of ISL6326, the TM digital
signal is linearly proportional to the NTC temperature. For 8. If N = 15, do not need the pull-down resistor RTC2,
accurate temperature compensation, the ratio of the TM otherwise obtain RTC2 by the following equation:
voltage to the NTC temperature of the practical design NxR TC1
R TC2 = ----------------------- (EQ. 22)
should be similar to that in Figure 12. 15 – N

Depending on the location of the NTC and the airflow, the 9. Run the actual board under full load again with the proper
NTC may be cooler or hotter than the current sense resistors connected to the TCOMP pin.
component. The TCOMP pin voltage can be utilized to 10. Record the output voltage as V1 immediately after the
correct the temperature difference between NTC and the output voltage is stable with the full load. Record the
current sense component. When a different NTC type or output voltage as V2 after the VR reaches the thermal
different voltage divider is used for the TM function, the steady state.
TCOMP voltage can also be used to compensate for the 11. If the output voltage increases over 2mV as the
difference between the recommended TM voltage curve in temperature increases, i.e. V2-V1 > 2mV, reduce N and
Figure 13 and that of the actual design. According to the redesign RTC2; if the output voltage decreases over 2mV
VCC voltage, ISL6326 converts the TCOMP pin voltage to a as the temperature increases, i.e. V1-V2 > 2mV, increase
N and redesign RTC2.
4-bit TCOMP digital signal as TCOMP factor N.
External Temperature Compensation
The TCOMP factor N is an integer between 0 and 15. The
integrated temperature compensation function is disabled for By pulling the TCOMP pin to GND, the integrated
N = 0. For N = 4, the NTC temperature is equal to the temperature compensation function is disabled. And one
temperature of the current sense component. For N < 4, the external temperature compensation network, shown in
NTC is hotter than the current sense component. The NTC is Figure 15, can be used to cancel the temperature impact on
cooler than the current sense component for N > 4. When the droop (i.e. load line).
N > 4, the larger TCOMP factor N, the larger the difference
between the NTC temperature and the temperature of the
current sense component.

23 FN9262.0
April 21, 2006
 ISL6326

General Design Guide

ISL6326
COMP Internal This design guide is intended to provide a high-level
circuit explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
IDROOP
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
o
C designs that include schematics, bills of materials, and
FB example board layouts for all common microprocessor
applications.

VDIFF Power Stages

The first step in designing a multiphase converter is to
FIGURE 15. EXTERNAL TEMPERATURE COMPENSATION determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
The sensed current will flow out of the IDROOP pin and on system constraints that differ from one design to the next.
develop a droop voltage across the resistor equivalent (RFB) Principally, the designer will be concerned with whether
between the FB and VDIFF pins. If RFB resistance reduces components can be mounted on both sides of the circuit
as the temperature increases, the temperature impact on the board; whether through-hole components are permitted; and
droop can be compensated. An NTC resistor can be placed the total board space available for power-supply circuitry.
close to the power stage and used to form RFB. Due to the Generally speaking, the most economical solutions are
non-linear temperature characteristics of the NTC, a resistor those in which each phase handles between 15 and 20A. All
network is needed to make the equivalent resistance surface-mount designs will tend toward the lower end of this
between the FB and VDIFF pins reverse proportional to the current range. If through-hole MOSFETs and inductors can
temperature. be used, higher per-phase currents are possible. In cases
The external temperature compensation network can only where board space is the limiting constraint, current can be
compensate the temperature impact on the droop, while it pushed as high as 40A per phase, but these designs require
has no impact to the sensed current inside ISL6326. heat sinks and forced air to cool the MOSFETs, inductors
Therefore, this network cannot compensate for the and heat-dissipating surfaces.
temperature impact on the overcurrent protection function. MOSFETs

Current Sense Output The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
The current from the IDROOP pin is the sensed average
frequency; the capability of the MOSFETs to dissipate heat;
current inside the ISL6326. In typical application, the
and the availability and nature of heat sinking and air flow.
IDROOP pin is connected to the FB pin for the application
where load line is required. LOWER MOSFET POWER CALCULATION

When load line function is not needed, the IDROOP pin can The calculation for heat dissipated in the lower MOSFET is
be used to obtain the load current information: with one simple, since virtually all of the heat loss in the lower
resistor from the IDROOP pin to GND, the voltage at the MOSFET is due to current conducted through the channel
IDROOP pin will be proportional to the load current: resistance (RDS(ON)). In Equation 24, IM is the maximum
continuous output current; IPP is the peak-to-peak inductor
R IDROOP R X (EQ. 23) current (see Equation 1); d is the duty cycle (VOUT/VIN); and
V IDROOP = ---------------------------
- ------------------ I LOAD
N R ISEN L is the per-channel inductance.

⎛ I M⎞ 2 I L, 2PP ( 1 – d ) (EQ. 24)

where VIDROOP is the voltage at the IDROOP pin, RIDROOP -⎟ ( 1 – d ) + --------------------------------
P LOW, 1 = r DS ( ON ) ⎜ -----
is the resistor between the IDROOP pin and GND, ILOAD is ⎝ N⎠ 12
the total output current of the converter, RISEN is the sense
resistor connected to the ISEN+ pin, N is the active channel An additional term can be added to the lower-MOSFET loss
number, and RX is the resistance of the current sense equation to account for additional loss accrued during the
element, either the DCR of the inductor or RSENSE dead time when inductor current is flowing through the
depending on the sensing method. lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON); the switching
The resistor from the IDROOP pin to GND should be chosen frequency, fS; and the length of dead times, td1 and td2, at
to ensure that the voltage at the IDROOP pin is less than 2V the beginning and the end of the lower-MOSFET conduction
under the maximum load current. interval respectively.
If the IDROOP pin is not use, tie it to GND.

24 FN9262.0
April 21, 2006
 ISL6326

solutions to the loss equations for different MOSFETs and

I M I PP⎞ ⎛I ⎞ different switching frequencies.
P LOW, 2 = V D ( ON ) f S ⎛ ----- M I--------
- t d1 + ⎜ -----
- – PP-⎟ t d2
(EQ. 25)
⎝ N- + --------
2 ⎠ ⎝N 2 ⎠
⎛ I M⎞
2
I PP2
P UP,4 ≈ r DS ( ON ) ⎜ -----
-⎟ d + ---------- d (EQ. 29)
Thus the total maximum power dissipated in each lower ⎝ N⎠ 12
MOSFET is approximated by the summation of PLOW,1 and
PLOW,2.
Current Sensing Resistor
Upper MOSFET Power Calculation The resistors connected to the Isen+ pins determine the
In addition to RDS(ON) losses, a large portion of the upper- gains in the load-line regulation loop and the channel-current
MOSFET losses are due to currents conducted across the balance loop as well as setting the overcurrent trip point.
input voltage (VIN) during switching. Since a substantially Select values for these resistors by the following equation:
higher portion of the upper-MOSFET losses are dependent RX I OCP
R ISEN = ----------------------
- -------------
- (EQ. 30)
on switching frequency, the power calculation is more –6 N
85 ×10
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET where RISEN is the sense resistor connected to the ISEN+
switching times; the lower-MOSFET body-diode reverse- pin, N is the active channel number, RX is the resistance of
recovery charge, Qrr; and the upper MOSFET RDS(ON) the current sense element, either the DCR of the inductor or
conduction loss. RSENSE depending on the sensing method, and IOCP is the
desired overcurrent trip point. Typically, IOCP can be chosen
When the upper MOSFET turns off, the lower MOSFET does
to be 1.3 times the maximum load current of the specific
not conduct any portion of the inductor current until the
application.
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper With integrated temperature compensation, the sensed
MOSFET falls to zero as the current in the lower MOSFET current signal is independent on the operational temperature
ramps up to assume the full inductor current. In Equation 26, of the power stage, i.e. the temperature effect on the current
the required time for this commutation is t1 and the sense element RX is cancelled by the integrated
approximated associated power loss is PUP,1. temperature compensation function. RX in Equation 30
I M I PP⎞ ⎛ t 1 ⎞ should be the resistance of the current sense element at the
P UP,1 ≈ V IN ⎛ ----- - ⎜ ---- ⎟ f (EQ. 26)
⎝ N- + --------
2 ⎠⎝ 2⎠ S
room temperature.

When the integrated temperature compensation function is

At turn on, the upper MOSFET begins to conduct and this disabled by pulling the TCOMP pin to GND, the sensed
transition occurs over a time t2. In Equation 27, the current will be dependent on the operational temperature of
approximate power loss is PUP,2. the power stage, since the DC resistance of the current
sense element may be changed according to the operational
⎛ I M I PP⎞ ⎛ t 2 ⎞
P UP, 2 ≈ V IN ⎜ -----
- – ---------⎟ ⎜ ---- ⎟ f S (EQ. 27) temperature. RX in Equation 30 should be the maximum DC
⎝N 2 ⎠⎝ 2⎠
resistance of the current sense element at the all operational
temperature.
A third component involves the lower MOSFET’s reverse-
recovery charge, Qrr. Since the inductor current has fully In certain circumstances, it may be necessary to adjust the
commutated to the upper MOSFET before the lower- value of one or more ISEN resistors. When the components
MOSFET’s body diode can draw all of Qrr, it is conducted of one or more channels are inhibited from effectively
through the upper MOSFET across VIN. The power dissipating their heat so that the affected channels run hotter
dissipated as a result is PUP,3 and is approximately than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
P UP,3 = V IN Q rr f S (EQ. 28)
Balance). Choose RISEN,2 in proportion to the desired
decrease in temperature rise in order to cause proportionally
Finally, the resistive part of the upper MOSFET’s is given in
less current to flow in the hotter phase:
Equation 29 as PUP,4.
ΔT
R ISEN ,2 = R ISEN ----------2 (EQ. 31)
The total power dissipated by the upper MOSFET at full load ΔT 1
can now be approximated as the summation of the results
from Equations 26, 27, and 28. Since the power equations In Equation 31, make sure that ΔT2 is the desired temperature
depend on MOSFET parameters, choosing the correct rise above the ambient temperature, and ΔT1 is the measured
MOSFETs can be an iterative process involving repetitive temperature rise above the ambient temperature. While a
single adjustment according to Equation 31 is usually
sufficient, it may occasionally be necessary to adjust RISEN

25 FN9262.0
April 21, 2006
 ISL6326

two or more times to achieve optimal thermal balance Fortunately, there is a simple approximation that comes very
between all channels. close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
Load-Line Regulation Resistor
poles and the ESR zero of the voltage-mode approximation,
The load-line regulation resistor is labelled RFB in Figure 5. yields a solution that is always stable with very close to ideal
Its value depends on the desired loadline requirement of the transient performance.
application.
C2 (OPTIONAL)
The desired loadline can be calculated by the following
equation:
V DROOP RC CC
R LL = ------------------------
- (EQ. 32) COMP
I FL

where IFL is the full load current of the specific application, FB

ISL6326
and VRDROOP is the desired voltage droop under the full
load condition. +
IDROOP
RFB VDROOP
Based on the desired loadline RLL, the loadline regulation -
resistor can be calculated by the following equation: VDIFF
NR R
ISEN LL (EQ. 33)
R FB = ---------------------------------
-
RX

where N is the active channel number, RISEN is the sense FIGURE 16. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6326 CIRCUIT
resistor connected to the ISEN+ pin, and RX is the
resistance of the current sense element, either the DCR of
the inductor or RSENSE depending on the sensing method. The feedback resistor, RFB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
If one or more of the current sense resistors are adjusted for
bandwidth for the compensated system, f0. The target
thermal balance, as in Equation 31, the load-line regulation
bandwidth must be large enough to assure adequate
resistor should be selected based on the average value of
transient performance, but smaller than 1/3 of the
the current sensing resistors, as given in the following
perHchannel switching frequency. The values of the
equation:
compensation components depend on the relationships of f0
R LL
R FB = ----------
RX ∑ RISEN ( n ) (EQ. 34) to the L-C pole frequency and the ESR zero frequency. For
n each of the three cases which follow, there is a separate set
of equations for the compensation components.
where RISEN(n) is the current sensing resistor connected to
the nth ISEN+ pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.

COMPENSATING LOAD-LINE REGULATED

CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.

Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.

26 FN9262.0
April 21, 2006
 ISL6326

1 C2
Case 1: ------------------- > f 0
2π LC
2πf 0 V pp LC
R C = R FB -----------------------------------
- RC CC
0.75V IN
COMP

0.75V IN
C C = -----------------------------------
-
2πV PP R FB f 0 FB
C1

ISL6326
1 1
------------------- ≤ f 0 < -----------------------------
- R1 RFB IDROOP
Case 2: 2π LC 2πC ( ESR )

V PP ( 2π ) 2 f 02 LC VDIFF
R C = R FB -------------------------------------------- (EQ. 35)
0.75 V IN
0.75V IN
C C = ------------------------------------------------------------
- FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED
( 2π ) f 02 V PP R FB LC
2
CONVERTER WITHOUT LOAD-LINE
REGULATION

1 The first step is to choose the desired bandwidth, f0, of the

Case 3: f 0 > ------------------------------
2πC ( ESR ) compensated system. Choose a frequency high enough to
2π f 0 V pp L
assure adequate transient performance but not higher than
R C = R FB -----------------------------------------
- 1/3 of the switching frequency. The type-III compensator has
0.75 V IN ( ESR )
an extra high-frequency pole, fHF. This pole can be used for
0.75V IN ( ESR ) C added noise rejection or to assure adequate attenuation at
C C = ------------------------------------------------
-
2πV PP R FB f 0 L the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose fHF = 10f0, but it can be
In Equation 35, L is the per-channel filter inductance divided
higher if desired. Choosing fHF to be lower than 10f0 can
by the number of active channels; C is the sum total of all
cause problems with too much phase shift below the system
output capacitors; ESR is the equivalent-series resistance of
bandwidth.
the bulk output-filter capacitance; and VPP is the sawtooth
amplitude described in Electrical Specifications. In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
The optional capacitor C2, is sometimes needed to bypass
Equation 36, RFB is selected arbitrarily. The remaining
noise away from the PWM comparator (see Figure 16). Keep
compensation components are then selected according to
a position available for C2, and be prepared to install a
Equation 36.
highHfrequency capacitor of between 22pF and 150pF in
case any leading-edge jitter problem is noted. C ( ESR )
R 1 = R FB -----------------------------------------
LC – C ( ESR )
Once selected, the compensation values in Equation 35
assure a stable converter with reasonable transient LC – C ( ESR )
C 1 = -----------------------------------------
performance. In most cases, transient performance can be R FB
improved by making adjustments to RC. Slowly increase the
0.75V IN
value of RC while observing the transient performance on an C 2 = ------------------------------------------------------------------
- (EQ. 36)
oscilloscope until no further improvement is noted. Normally, ( 2π ) 2 f 0 f HF LCR FB V PP
CC will not need adjustment. Keep the value of CC from
2
Equation 35 unless some performance issue is noted. V PP ⎛ 2π⎞ f 0 f HF LCR FB
⎝ ⎠
R C = --------------------------------------------------------------------
-
COMPENSATION WITHOUT LOAD-LINE REGULATION ⎛2πf ⎞
0.75 V IN ⎝ HF LC – 1⎠
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
0.75V IN ⎛2πf ⎞
resonant frequency and a zero at the ESR frequency. A ⎝ HF LC – 1⎠
C C = -------------------------------------------------------------------
type III controller, as shown in Figure 17, provides the ( 2π ) 2 f 0 f HF LCR FB V PP
necessary compensation.

In Equation 36, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and VPP is the sawtooth
signal amplitude as described in Electrical Specifications.

27 FN9262.0
April 21, 2006
 ISL6326

Output Filter Design Since the capacitors are supplying a decreasing portion of
The output inductors and the output capacitor bank together the load current while the regulator recovers from the
to form a low-pass filter responsible for smoothing the transient, the capacitor voltage becomes slightly depleted.
pulsating voltage at the phase nodes. The output filter also The output inductors must be capable of assuming the entire
must provide the transient energy until the regulator can load current before the output voltage decreases more than
respond. Because it has a low bandwidth compared to the ΔVMAX. This places an upper limit on inductance.
switching frequency, the output filter necessarily limits the Equation 39 gives the upper limit on L for the cases when
system transient response. The output capacitor must the trailing edge of the current transient causes a greater
supply or sink load current while the current in the output output voltage deviation than the leading edge. Equation 40
inductors increases or decreases to meet the demand. addresses the leading edge. Normally, the trailing edge
In high-speed converters, the output capacitor bank is dictates the selection of L because duty cycles are usually
usually the most costly (and often the largest) part of the less than 50%. Nevertheless, both inequalities should be
circuit. Output filter design begins with minimizing the cost of evaluated, and L should be selected based on the lower of
this part of the circuit. The critical load parameters in the two results. In each equation, L is the per-channel
choosing the output capacitors are the maximum size of the inductance, C is the total output capacitance, and N is the
load step, ΔI; the load-current slew rate, di/dt; and the number of active channels.
maximum allowable output voltage deviation under transient 2NCVO
L ≤ --------------------
- ΔV MAX – ΔI ( ESR ) (EQ. 39)
loading, ΔVMAX. Capacitors are characterized according to ( ΔI ) 2
their capacitance, ESR, and ESL (equivalent series
inductance). ( 1.25 ) NC (EQ. 40)
L ≤ -------------------------- ΔV MAX – ΔI ( ESR ) ⎛ V IN – V O⎞
( ΔI ) 2 ⎝ ⎠
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
Input Supply Voltage Selection
initially deviate by an amount approximated by the voltage
The VCC input of the ISL6326 can be connected either
drop across the ESL. As the load current increases, the
directly to a +5V supply or through a current limiting resistor
voltage drop across the ESR increases linearly until the load
to a +12V supply. An integrated 5.8V shunt regulator
current reaches its final value. The capacitors selected must
maintains the voltage on the VCC pin when a +12V supply is
have sufficiently low ESL and ESR so that the total output
used. A 300Ω resistor is suggested for limiting the current
voltage deviation is less than the allowable maximum.
into the VCC pin to a worst-case maximum of approximately
Neglecting the contribution of inductor current and regulator
25mA.
response, the output voltage initially deviates by an amount:
di Switching Frequency Selection
ΔV ≈ ( ESL ) ----- + ( ESR ) ΔI (EQ. 37)
dt There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
The filter capacitor must have sufficiently low ESL and ESR the upper-MOSFET loss calculation. These effects are
so that ΔV < ΔVMAX. outlined in MOSFETs, and they establish the upper limit for
Most capacitor solutions rely on a mixture of high-frequency the switching frequency. The lower limit is established by the
capacitors with relatively low capacitance in combination requirement for fast transient response and small output
with bulk capacitors having high capacitance but limited voltage ripple as outlined in Output Filter Design. Choose the
high-frequency performance. Minimizing the ESL of the lowest switching frequency that allows the regulator to meet
high-frequency capacitors allows them to support the output the transient-response requirements.
voltage as the current increases. Minimizing the ESR of the Input Capacitor Selection
bulk capacitors allows them to supply the increased current
The input capacitors are responsible for sourcing the AC
with less output voltage deviation.
component of the input current flowing into the upper
The ESR of the bulk capacitors also creates the majority of MOSFETs. Their RMS current capacity must be sufficient to
the output voltage ripple. As the bulk capacitors sink and handle the AC component of the current drawn by the upper
source the inductor AC ripple current (see Interleaving and MOSFETs which is related to duty cycle and the number of
Equation 2), a voltage develops across the bulk-capacitor active phases.
ESR equal to IC,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
VPP(MAX), determines the lower limit on the inductance.

⎛V – N V ⎞
⎝ IN OUT⎠ V OUT
L ≥ ( ESR ) ------------------------------------------------------------ (EQ. 38)
f S V IN V PP( MAX )

28 FN9262.0
April 21, 2006
 ISL6326

0.3 and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
INPUT-CAPACITOR CURRENT (IRMS/IO)

board parasitic impedances and maximize suppression.

0.3
IL,PP = 0 IL,PP = 0.5 IO
0.2 IL,PP = 0.25 IO IL,PP = 0.75 IO

INPUT-CAPACITOR CURRENT (IRMS/IO)

0.2

0.1
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO 0.1

0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VO/VIN)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER 0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VO/VIN)

0.3 FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT

IL,PP = 0 IL,PP = 0.5 IO
vs DUTY CYCLE FOR 4-PHASE CONVERTER
IL,PP = 0.25 IO IL,PP = 0.75 IO
INPUT-CAPACITOR CURRENT (IRMS/IO)

MULTIPHASE RMS IMPROVEMENT

Figure 21 is provided as a reference to demonstrate the
0.2
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a two-phase
converter versus that of a single phase. Assume both
0.1 converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of IL,PP to IO of 0.5. The
single phase converter would require 17.3Arms current
capacity while the two-phase converter would only require
10.9Arms. The advantages become even more pronounced
0
0 0.2 0.4 0.6 0.8 1.0 when output current is increased and additional phases are
DUTY CYCLE (VO/VIN) added to keep the component cost down relative to the
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT single phase approach.
vs DUTY CYCLE FOR 3-PHASE CONVERTER
0.6
For a two phase design, use Figure 18 to determine the
INPUT-CAPACITOR CURRENT (IRMS/IO)

input-capacitor RMS current requirement given the duty

cycle, maximum sustained output current (IO), and the ratio
of the per-phase peak-to-peak inductor current (IL,PP) to IO. 0.4
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage. 0.2
IL,PP = 0
Figures 19 and 20 provide the same input RMS current IL,PP = 0.5 IO
IL,PP = 0.75 IO
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described above. 0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VO/VIN)
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS
and falling edge voltage spikes. The result from the high CURRENT vs DUTY CYCLE FOR SINGLE-PHASE
CONVERTER
current slew rates produced by the upper MOSFETs turn on

29 FN9262.0
April 21, 2006
 ISL6326

Layout Considerations
The following layout strategies are intended to minimize the
impact of board parasitic impedances on converter
performance and to optimize the heat-dissipating capabilities
of the printed-circuit board. These sections highlight some
important practices which should not be overlooked during the
layout process.

Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most
critical because they carry large amounts of energy and tend
to generate high levels of noise. Switching component
placement should take into account power dissipation. Align
the output inductors and MOSFETs such that space between
the components is minimized while creating the PHASE
plane. Place the Intersil MOSFET driver IC as close as
possible to the MOSFETs they control to reduce the parasitic
impedances due to trace length between critical driver input
and output signals. If possible, duplicate the same
placement of these components for each phase.

Next, place the input and output capacitors. Position one

high-frequency ceramic input capacitor next to each upper
MOSFET drain. Place the bulk input capacitors as close to
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains result in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity to the microprocessor
socket.

30 FN9262.0
April 21, 2006
 ISL6326

Quad Flat No-Lead Plastic Package (QFN) L40.6x6

Micro Lead Frame Plastic Package (MLFP) 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
2X (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C)
0.15 C A
A D MILLIMETERS
9 D/2 SYMBOL MIN NOMINAL MAX NOTES

D1 A 0.80 0.90 1.00 -

A1 - - 0.05 -
D1/2
2X
N 0.15 C B A2 - - 1.00 9
6
INDEX A3 0.20 REF 9
AREA 1 E1/2 E/2 b 0.18 0.23 0.30 5, 8
2
3 E1 E D 6.00 BSC -

9 D1 5.75 BSC 9
2X D2 3.95 4.10 4.25 7, 8
0.15 C B
E 6.00 BSC -
2X B
TOP VIEW
0.15 C A E1 5.75 BSC 9

A2 E2 3.95 4.10 4.25 7, 8

4X
0
A / / 0.10 C e 0.50 BSC -
C
0.08 C k 0.25 - - -
L 0.30 0.40 0.50 8
SEATING PLANE SIDE VIEW A3 A1
9 L1 - - 0.15 10
NX b 5 N 40 2
0.10 M C A B
4X P Nd 10 3
D2 7 8
Ne 10 3
(DATUM B) NX k
D2 P - - 0.60 9
2 N
4X P θ - - 12 9
1 Rev. 1 10/02
(DATUM A) 2
3 (Ne-1)Xe NOTES:
6 E2 REF.
INDEX 7 1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
AREA E2/2 2. N is the number of terminals.
NX L 8
3. Nd and Ne refer to the number of terminals on each D and E.
N e
9 4. All dimensions are in millimeters. Angles are in degrees.
8 (Nd-1)Xe CORNER
REF. 5. Dimension b applies to the metallized terminal and is measured
OPTION 4X
between 0.15mm and 0.30mm from the terminal tip.
BOTTOM VIEW
A1 6. The configuration of the pin #1 identifier is optional, but must be
NX b located within the zone indicated. The pin #1 identifier may be
5 either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
C SECTION "C-C"
L 8. Nominal dimensions are provided to assist with PCB Land Pattern
C
L Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
L L Anvil singulation method is used and not present for saw
10 10
L1 L1 singulation.
e e
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
C C
TERMINAL TIP minus L1 to be equal to or greater than 0.3mm.
FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

31 FN9262.0
April 21, 2006