EEE 598: VLSI High Speed I/O Circuits

Fall 2010

Project 2

Team Members:

1. Sampath Venkatesan, ASU #1202054403

2. Giser Ali, ASU # 993491966
3. Abul Bashar Ishteak Hossain, ASU # 993779692
4. Mohammad Reza Ghajar ASU # 1200919126
Subject: EEE598 Project #2, “VLSI High-Speed I/O Circuits” Fall2010, ASU
From: Dr. Hongjiang Song
Due Date: Sept. 23, 2010 (end of class)

Problem 1: VerilogA coding and simulation on Cadence.

Instruction: This project is designed for you to setup your simulation environment in Cadence
and to learn basic coding technique of VerilogA for simple circuits, such as digital gates.
The easiest way to do this is to copy an existing digital gate to the component name you would
like create. Then modify the symbol and the VerilogA code (text format) to match your
component. An EEE598Lib is posted for you to start with your project. You may download the
file to you unix/lynix fold, un-zip it and then un-tar it.

Here is the project assignment:

1) Create the VerilogA view and symbol view for the digital Full Adder circuit. Simulate it
into Cadence (Spectre) to prove your design.
2) Using the Full Adder circuit to create an 8-bit binary Carry propagation adder by
connecting 8 Full Adder schematic. And simulate it in Spectre to prove your design.

A Co
S
A Co B
Ci
S
B
Ci
A Co
S
B
Ci

A Co
S
B
Ci
Solution:
The verilog A code for the Full Adder is shown below:

module full_adder(vin1, vin2, vin_carry, vout_sum, vout_carry)

(vlogic_high, vlogic_low, vtrans, tdel, trise, tfall)
node [V, I] vin1, vin2, vin_carry, vout_sum, vout_carry;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 1.4;
parameter real tdel = 3u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);
{
integer a, b, c;
real vout_sum_val;
real vout_carry_val;

initial {
if (vlogic_high < vlogic_low) {
$error("Range specification error. vlogic_high = (%E) less than vlogic_low = (%E).\n",
vlogic_high, vlogic_low );
}
if (vtrans > vlogic_high || vtrans < vlogic_low) {
$warning("Inconsistent $threshold specification w/logic family.\n");
}
}

analog {
a = V(vin1) > vtrans;
b = V(vin2) > vtrans;
c = V(vin_carry) > vtrans;

if ($threshold(V(vin1) - vtrans, 1)) a = 1;

if ($threshold(V(vin1) - vtrans, -1)) a = 0;

if ($threshold(V(vin2) - vtrans, 1)) b = 1;

if ($threshold(V(vin2) - vtrans, -1)) b = 0;

if ($threshold(V(vin_carry) - vtrans, 1)) c = 1;

if ($threshold(V(vin_carry) - vtrans, -1)) c = 0;

vout_sum_val = (c ^ a ^ b) ? vlogic_high : vlogic_low;

vout_carry_val = ((c && (a || b)) || (a && b))

? vlogic_high : vlogic_low;

V(vout_sum) <- $transition( vout_sum_val, tdel, trise, tfall);

V(vout_carry) <- $transition( vout_carry_val, tdel, trise, tfall);
}
}
The above Full-Adder is simulated in the Cadence (Spectre) and the simulation schematic and
waveform is plotted Fig.1 and Fig 2 below:

Fig 1: Full adder schematic

Fig 2: Simulation waveform for Adder block from the Verilog A code
An 8-bit binary carry propagation adder is created by concatenating the full-adder blocks. The
schematic diagram for the 8-bit binary adder is shown in Fig. 3.

Fig. 3: Schematic for the 8-bit binary carry propagation adder

The adder was tested as a Full bit adder blockwise first which is given in Fig 2. Then during 8 bit
binary carry propagation adder, the simulation was done such that the carry propagates through
all the adders and results at Cout.

Input given:
A8 A7 A6 A5 A4 A3 A2 A1 = 1 1 1 1 1 1 1 1
B8 B7 B6 B5 B4 B3 B2 B1 = 0 0 0 0 0 0 0 0
Cin = 0 given for half the period and Cin =1 for rest of the time.

Output results:
When Cin = 0
S8 S7 S6 S5 S4 S3 S2 S1 = 1 1 1 1 1 1 1 1
C8 C7 C6 C5 C4 C3 C2 C1 = 0 0 0 0 0 0 0 0

When Cin =1, Carry will propogate through the adders and we will have:
S8 S7 S6 S5 S4 S3 S2 S1 = 0 0 0 0 0 0 0 0
C8 C7 C6 C5 C4 C3 C2 C1 = 1 1 1 1 1 1 1 1
The above the 8-bit binary carry propagation adder is simulated in the Cadence (Spectre) and the
simulation waveform for all the sums and carry outs are given below in Fig 4.

Fig 4: Simulation waveform for the 8-bit binary carry propagation adder
Problem 2: For the CMOS buffer circuit below, find based on the simulation the Mean, the
Standard Deviation of the Absolute Jitter (or TIE), the Period Jitter, and the Cycle-to-Cycle Jitter
of the output clock signal. (Assuming TSMC0.18 process technology)

[1.5 + 0.1xSin(t)]V  = 2 x10Mhz

1.5V 1.5V

1.5V
…
0 A A A A Do

T =2ns
Rise time = fall time = 50ps P: 1.8u/0.18u
N: 1.2u/0.18u

Solution:

Test bench

Fig 5: Test bench for calculation of jitter due to power noise.

Vout = Jittered output due to introduction of the power noise.

Vout2 = Ideal output with no power noise (ideal power).
Results

Ideal output

Vdd Noise

Jittered output

Fig 6: Input Output voltages for calculation of jitter due to power noise.

We have used the following definitions for calculation of different jitter measurements.
 Fig 7: Simulation results for calculation of jitter due to power noise.

Statistical calculation on Jitter,

AJ mean = 469.5fs
PJ_mean = 2.099fs.
CJ_mean = -75.87as.
AJ_stddev = 5.839ps
PJ_stddev = 736.6fF
CJ_stddev = 113.6fF
Problem 3. For step function Vs(t) find the voltage signal at VA(t), VB(t), and VC(t). Verify your
result using circuit simulation (Hint: use T-line model in Cadence/spice).

Delay = 1s
Delay = 9s

- + VB
Vs(t) 25 VA 50 VC

ZL >> 50

1V

Vs(t)

Solution:

Given:
ZO=50 Ω
ZS=25 Ω
ZL=∞ Ω

Source end (attenuation):

α= ZS/( ZS+ ZO)
α= 50/(25+50)= 0.667
and,
ρS=( ZS- ZO)/ ( ZS+ ZO)
ρS=(25-50)/(25+50)=-0.333

Load end (reflection):

ρL= ( ZL- ZO)/ ( ZL+ ZO)
ρL = 1
Test Bench

Fig 8: Test bench for Transmission line delay calculation.

Results
Fig 8: Simulation results for Transmission line delay calculation.