EXPERIMENT-1

AIM: Design a half adder

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (a, b: in std_logic;
s, c: out std_logic);
end half adder;
architecture behavioral of half_adder is
begin
process (a, b)
begin
s<=a xor b;
c<=a and b;
end process;
end behavioral;
 EXPERIMENT-2
AIM: Design a full adder
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (a, b, cin: in std_logic;
s, cout: out std_logic);
end full adder;
architecture behavioral of full_adder is
begin
process (a, b, c)
begin
s<=a xor b xor cin;
cout<= ((a and b) or (b and cin) or (cin and a));
end process;
end behavioral;
 EXPERIMENT-3
AIM: Design all types of flip flops--
PROGRAM: S-R flip flop:
library ieee;
use ieee.std_logic_1164.all;
entity srff is
port (s, r, clk: in std_logic;
q: out std_logic);
end srff;
architecture behavioral of srff is
begin
process (s, r, clk)
begin
if (clk=’1’ and clk’ event) then
if (s=’0’ and r=’0’0 then
q<=’q’;
and r=’1’) then
q<=’1’;
elsif (s=’1’ and r=’0’) then
q<=’0’;
elsif (s=’1’ and r=’1’) then
q<=’u’;
end if;
end if;
end process;
end behavioral;
 EXPERIMENT-4
AIM: Design all types of flip flops--
PROGRAM: J-K flip flop:
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port (j, k, clk, reset: in std_logic;
q, qbar: out std_logic);
end jkff;
architecture behavioral of jkff is
begin
process (j, k, clk, reset)
begin
if (reset= ‘0’) then
state <= ‘0’;
elsif (clk=’1’ and clk’ event)
case JK is
when ‘10’ => state <= ‘1’;
when ‘01’ => state <= ‘0’;
when ‘11’ => state <= not state;
when others => null;
end case;
end if;
end process;
q<= state;
qbar<= not state;
end behavioral;
 EXPERIMENT-5
AIM: Design all types of flip flops--
PROGRAM: D flip flop:
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (d, clk: in std_logic;
q: out std_logic);
end dff;
architecture behavioral of dff is
begin
process (d, clk)
begin
if (clk=’1’ and clk’ event)
if (d=’0’) then
q<= ‘0’;
else
q<=’1’;
end if;
end if;
end process;
end behavioral;
 EXPERIMENT-6
AIM: Design all types of flip flops--
PROGRAM: T flip flop:
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port (t, clk: in std_logic;
q: out std_logic);
end tff;
architecture behavioral of tff is
begin
process (t, clk)
begin
if (clk=’1’ and clk’ event)
if (t=’0’) then
q<= ‘1’;
else
q<=’0’;
end if;
end if;
end process;
end behavioral;
 EXPERIMENT-7
AIM: Design of the 4:1 multiplexer.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d: in std_logic;
sel: in std_logic_vector(1 down to 0)
y: out std_logic);
end mux;
architecture behavioral of mux is
begin
process (a, b, c, d, sel)
begin
if (sel =”00”) then
y<=a;
elsif (sel =”01”) then
y<=’b’;
elsif (sel =”10”) then
y<=’c’;
else
y<=’d’;
end if;
end process;
end behavioral;
 EXPERIMENT-8
AIM: Design of the 8:3 encoder.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
entity encoder is
port (a: in std_logic_vector(7 down to 0);
y: out std_logic_vector(2 down to 0);
end encoder;
architecture arch of encoder is
begin
process (a)
begin
case a is
when “00000001” => y <= “000”;
when “00000010” => y <= “001”;
when “00000100” => y <= “010”;
when “00001000” => y <= “011”;
when “00010000” => y <= “100”;
when “00100000” => y <= “101”;
when “01000000” => y <= “110”;
when “10000000” => y <= “111”;
when others => y <= “xxx”;
end case;
end process;
end arch;
 EXPERIMENT-9
AIM: Design of the 3:8 decoder.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee std_logic_unsigned.all;
entity decoder is
port (a: in integer range 0 to 7;
y: out std_logic_vector(7 down to 0);
end decoder;
architecture arch of decoder is
begin
with a select
y <= “00000001” when 0,
“00000010” when 1,
“00000100” when 2,
“00001000” when 3,
“00010000” when 4,
“00100000” when 5,
“01000000” when 6,
“10000000” when 7,
“00000000” when others;

end arch;
 INDEX

S.NO NAME OF EXPERIMENT DATE REMARK

1. Design of half adder.

2. Design of full adder.

3. Design of all types of flip flops- S-R flip flop.

4. Design of all types of flip flops- J-K flip flop.

5. Design of all types of flip flops- D flip flop.

6. Design of all types of flip flops- T flip flop.

7. Design of the 4:1 multiplexer.

8. Design of the 8:3 encoder.

9. Design of the 3:8 decoder.