Synthesis of Digital Systems

Online Course
Jan-Apr 2017

Part 2: Hardware Modelling

and VHDL
Preeti Ranjan Panda
Department of Computer Science and Engineering
Indian Institute of Technology Delhi
panda@cse.iitd.ac.in
http://www.cse.iitd.ac.in/~panda/
 Specification
• Layout editor
– directly enter layout
Layout
– ~103 of unique transistors
Editor
– complex circuits possible
• memory, aided by generators
• Schematic Capture
– enter gates and interconnections Schematic
– ~105 transistors Editor
• Hardware Description Languages
– text description
– >107 transistors
• System Level Design y = a + b;
if (y < 0) HDL
– text description ...
– >109 transistors
(C) P. R. Panda, I.I.T Delhi, 2017 2
 Specification Levels
Maintainability Optimality
Complexity
Modifiability Efficiency

Layout

Schematic
?

y = a + b;
HDL / if (y < 0)
System Level ...

(C) P. R. Panda, I.I.T Delhi, 2017 3

 Efficiency vs. Time-to-Market

• Efficiency more important for high-

performance designs
– processors, memory
– high volume, so cost is amortised
• Time-to-market more important for most
other classes of designs
– consumer electronics
– efficiency can be sacrificed

(C) P. R. Panda, I.I.T Delhi, 2017 4

 Requirements for Hardware
Description Languages - 1
• Time
– how the behaviour of the system changes
with time
– creating waveforms

(C) P. R. Panda, I.I.T Delhi, 2017 5

 Requirements for Hardware
Description Languages - 2
• Periodic Signals
– clocks

(C) P. R. Panda, I.I.T Delhi, 2017 6

 Requirements for Hardware
Description Languages - 3
• Concurrency

P1 P2

x=x+1 y=a-b

Specify: Processes P1 and P2 execute in parallel

(C) P. R. Panda, I.I.T Delhi, 2017 7

 Requirements for Hardware
Description Languages - 4
• Structure, composition, and interconnection

A B
W
X1 Y1 X2

X
Block A contains two sub-blocks: X1 and Y1
Block X is duplicated
Wire W connects A and B
(C) P. R. Panda, I.I.T Delhi, 2017 8
 Requirements for Hardware
Description Languages - 5
• Bit-true data types
– Not so important in SW
– Important in HW
int<6:0> var;

Specify the bit-width of variables

(C) P. R. Panda, I.I.T Delhi, 2017 9

 Requirements for Hardware
Description Languages - 6
• Modules and Interfaces
– Ports

Input Port P Output Port P

Input Port Q Module M
Inout Port P
Input Port R

(C) P. R. Panda, I.I.T Delhi, 2017 10

 Requirements for Hardware
Description Languages - 7
• Electrical Characteristics
– Current Levels
– Tristating
• Sensitivity
– rising edge/falling edge

(C) P. R. Panda, I.I.T Delhi, 2017 11

 Requirements for Hardware
Description Languages - 8
• Other programming constructs
– Text and File I/O
• useful in simulation/debugging

(C) P. R. Panda, I.I.T Delhi, 2017 12

 VHDL
(VHSIC [Very High Speed Integrated Circuit]
Hardware Description Language)
 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 14
 Hardware Description Languages

• VHDL - VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language
– originally meant for simulation/documentation
– syntax based on Ada/Pascal
• Verilog
– syntax based on C
• SystemC
– based on C++
– system level language

(C) P. R. Panda, I.I.T Delhi, 2017 15

 Which HDL to use?
• Coverage of Hardware concepts
– equally good
• Learning one language eases learning of the
other
– most differences are minor/syntactic
• Status of tool support
– equally good for both VHDL/Verilog
– SystemC used more in system level modelling

(C) P. R. Panda, I.I.T Delhi, 2017 16

 Fundamental VHDL Objects:
entity/architecture pairs

entity represents
VHDL model Entity
external interface
consists of
two parts
architecture
Architecture represents
functionality/contents

(C) P. R. Panda, I.I.T Delhi, 2017 17

 Specifying interfaces:
entities and ports

a
y
b
Entity has Model Name
interface only.
No functionality. ENTITY and_gate IS
PORT (a: IN BIT;
b: IN BIT; Port direction
Port Name y: OUT BIT);
END and_gate;
Port type
(C) P. R. Panda, I.I.T Delhi, 2017 18
 Specifying Functionality:
architectures

ARCHITECTURE data_flow OF and_gate IS

BEGIN
y <= a AND b;
END data_flow;

May have multiple architectures for given entity

• different views
• different levels of detail

(C) P. R. Panda, I.I.T Delhi, 2017 19

 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 20
 Specifying Concurrency:
Concurrent Signal Assignment
ci

ai
bi + si

ARCHITECTURE data_flow
co
OF full_adder IS
BEGIN Concurrent Signal Assignments
si <= ai XOR bi XOR ci;
co <= (ai AND bi) OR (bi AND ci)
OR (ai AND ci);
END data_flow;
(C) P. R. Panda, I.I.T Delhi, 2017 21
 When is Signal Assignment
Executed?
Assignment executed when any signal on RHS changes

ARCHITECTURE data_flow
OF full_adder IS
Executed when
BEGIN
ai, bi, or ci changes
si <= ai XOR bi XOR ci;
co <= (ai AND bi) OR (bi AND ci) Executed when
OR (ai AND ci); ai, bi, or ci changes
END data_flow;

(C) P. R. Panda, I.I.T Delhi, 2017 22

 Order of Execution

• Execution independent of specification

order
ARCHITECTURE data_flow ARCHITECTURE data_flow
OF full_adder IS OF full_adder IS
BEGIN BEGIN
si <= ai XOR bi XOR ci; co <= (ai AND bi) OR (bi AND ci)
co <= (ai AND bi) OR (bi AND ci) OR (ai AND ci);
OR (ai AND ci); si <= ai XOR bi XOR ci;
END data_flow; END data_flow;

These two are equivalent

(C) P. R. Panda, I.I.T Delhi, 2017 23
 Modelling Combinational Logic

• One concurrent assignment for each

output
ARCHITECTURE data_flow
OF comb_logic IS
i1 o1 BEGIN
i2 Comb o2 o1 <= i1 and i2;
i3 Logic o3 o2 <= (i2 or i3) xor (i1 and i4);
o3 <= ...;
i4 o4
o4 <= ...;
END data_flow;

(C) P. R. Panda, I.I.T Delhi, 2017 24

 When Logic Complexity Increases

• Temporary SIGNALS needed

• Avoid redundant evaluations

y = g (f (x))
g t = f (x) g y = g (t)
x f x f
h z = h (f (x)) h z = h (t)

Ports: x, y, z Signal: t

(C) P. R. Panda, I.I.T Delhi, 2017 25

 SIGNALS
• Represent intermediate wires/storage
• Internal - not visible outside entity
ENTITY comb_logic IS
ENTITY comb_logic IS PORT (i1, i2, i3, i4: IN BIT;
PORT (i1, i2, i3, i4: IN BIT; o1, o2: OUT BIT);
o1, o2: OUT BIT); END comb_logic;
END comb_logic;
ARCHITECTURE data_flow1
ARCHITECTURE data_flow OF comb_logic IS
OF comb_logic IS SIGNAL temp: BIT;
BEGIN BEGIN
o1 <= (i1 and i2 and i3) xor i2; temp <= (i1 and i2 and i3);
o2 <= (i1 and i2 and i3) or i4; o1 <= temp xor i2;
END data_flow; o2 <= temp or i4;
END data_flow;
(C) P. R. Panda, I.I.T Delhi, 2017 26
 SIGNALS

• executed when i1, i2,

ARCHITECTURE data_flow
or i3 changes OF comb_logic IS
• executed when temp or SIGNAL temp: BIT;
BEGIN
i2 changes temp <= (i1 and i2 and i3);
• SIGNALS are o1 <= temp xor i2;
o2 <= temp or i4;
associated with END data_flow;
time/waveforms
• PORT is a special type
of SIGNAL

(C) P. R. Panda, I.I.T Delhi, 2017 27

 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 28
 Modelling Delays: inertial delay
• Models gate delays
• Spikes suppressed
y <= INERTIAL NOT a AFTER 10 ns;
y <= NOT a AFTER 10 ns; -- inertial delay is default

0 10 12 22 30 35
(C) P. R. Panda, I.I.T Delhi, 2017 29
 Modelling Delays: transport delay
• Models wires/transmission lines
– used in more abstract modelling
• Spikes propagated
y <= TRANSPORT NOT a AFTER 10 ns;

0 10 12 22 30 35 40 45
(C) P. R. Panda, I.I.T Delhi, 2017 30
 Events and Transactions

• Event
– Signal assignment that causes change in
value
• Transaction
– Value scheduled for signal assignment
• may or may not cause change in value

(C) P. R. Panda, I.I.T Delhi, 2017 31

Events and Transactions: Example

ARCHITECTURE demo OF example IS

SIGNAL a, b, c: BIT := ‘0’;
BEGIN
a <= ‘1’ AFTER 15 NS;
b <= NOT a AFTER 5 NS;
c <= a AFTER 10 NS;
END demo;

Source: Z. Navabi, VHDL - analysis and modeling of digital systems

(C) P. R. Panda, I.I.T Delhi, 2017 32

 Events and Transactions: Example
ARCHITECTURE demo OF
example IS a
SIGNAL a, b, c: BIT := ‘0’;
0
BEGIN
a <= ‘1’ AFTER 15 NS; b 0
b <= NOT a AFTER 5 NS;
c <= a AFTER 10 NS; c 0
END demo;
0 5 10 15 20 25

a (1, 15)
Events b (1,5) c (0, 10)
and b (1,5)
Transaction Transaction
Transactions c (0, 10) Expires Expires
Transactions Event Created No Event
Scheduled
(C) P. R. Panda, I.I.T Delhi, 2017 33
 Events and Transactions: Example
ARCHITECTURE demo OF
example IS a
SIGNAL a, b, c: BIT := ‘0’;
0
BEGIN
a <= ‘1’ AFTER 15 NS; b 0
b <= NOT a AFTER 5 NS;
c <= a AFTER 10 NS; c 0
END demo;
0 5 10 15 20 25

a (1, 15) b (0, 5) b (0, 5) c (1, 10)

Events
and c (1, 10) Transaction Transaction
Transaction
Transactions Expires New Expires Expires
Event Created Transactions Event Created Event Created
(C) P. R. Panda, I.I.T Delhi, 2017 34
 Inertial Delay: Suppressing a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; -- transport b 0
b <= NOT a AFTER 8 NS; -- inertial
0 8

a (1, 10)
Events a (0, 15) b (1, 8)
and
b (1, 8) Transaction
Transactions
Transactions Expires
Scheduled Event Created

(C) P. R. Panda, I.I.T Delhi, 2017 35

 Inertial Delay: Suppressing a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; -- transport b 0
b <= NOT a AFTER 8 NS; -- inertial
0 10 15

Events a (1, 10) b (0, 8) a (0, 15) b (1, 8)

and Transaction
Transactions New Transaction New Transaction
Expires Transaction Expires Scheduled -
Event Created Scheduled Event Created Cancels Old
Transaction
(C) P. R. Panda, I.I.T Delhi, 2017 36
 Inertial Delay: Suppressing a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; -- transport b 0
b <= NOT a AFTER 8 NS; -- inertial
0 8 10 15 23

b (1,8)
Events
and Transaction
Transactions Expires
No Event

(C) P. R. Panda, I.I.T Delhi, 2017 37

 Transport Delay: Propagating a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; b 0
b <= TRANSPORT NOT a
AFTER 8 NS; 0 8

a (1, 10)
Events a (0, 15) b (1,8)
and
b (1,8) Transaction
Transactions
Transactions Expires
Scheduled Event Created

(C) P. R. Panda, I.I.T Delhi, 2017 38

 Transport Delay: Propagating a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; b 0
b <= NOT a AFTER 8 NS;
0 10 15

Events a (1, 10) b (0,8) a (0, 15) b (1,8)

and Transaction
Transactions New Transaction New Transaction
Expires Transaction Expires Scheduled - Old
Event Created Scheduled Event Created Transaction
Retained
(C) P. R. Panda, I.I.T Delhi, 2017 39
 Transport Delay: Propagating a
pulse
SIGNAL a, b: BIT := ‘0’;
... a 0
a <= ‘1’ AFTER 10 NS,
‘0’ AFTER 15 NS; -- transport b 0
b <= TRANSPORT
NOT a AFTER 8 NS; 0 8 10 15 18 23

b (0,8) b (1,8)
Events
and
Transactions Transaction Transaction
Expires Expires
Event Created Event Created

(C) P. R. Panda, I.I.T Delhi, 2017 40

 Generating clocks

a
0 10 20 30 40 50

a <= NOT a AFTER 10 ns;

(C) P. R. Panda, I.I.T Delhi, 2017 41

 Delta Delays
ARCHITECTURE x of y IS
SIGNAL b, c: bit;
BEGIN zero-delay
b <= NOT a; signal assignments
c <= clock NAND b;
d <= c AND b;
END x;

a <= 0 c <= 0
b <= 1 d <= 0
(clock = 1) d <= 1

Delta 1 Delta 2 Delta 3 Delta 4

Simulation time does not advance

(C) P. R. Panda, I.I.T Delhi, 2017 42
 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 43
Describing Behaviour: Processes

• Signal assignment statements OK for

simple behaviour
• Complex behaviour requires more
constructs
– conditionals (IF, CASE)
– loops (FOR, WHILE)
• Use VHDL PROCESS

(C) P. R. Panda, I.I.T Delhi, 2017 44

 VHDL PROCESS
ARCHITECTURE x of a IS BEGIN
• Execution within a
PROCESS is sequential f <= g+ 1;
• Processes are concurrent
p1: PROCESS
w.r.t each other BEGIN
• Signal assignment is a IF (x) THEN ...
ELSE ...;
simple special case END PROCESS;
• Architecture consists of a
p2: PROCESS
set of Processes (and BEGIN
signal assignments) at FOR i in 1 TO 5 LOOP
top level a (i) <= 0;
END LOOP;...
• Processes communicate END PROCESS;
using signals END x;
(C) P. R. Panda, I.I.T Delhi, 2017 45
 PROCESS Execution Semantics

• Need to define when Process is

executed
– suspending/resuming execution
– more complex than signal assignment
(“evaluate when any signal on RHS
changes”)
• No notion of “completion” of execution
– needs to emulate hardware
(C) P. R. Panda, I.I.T Delhi, 2017 46
 Process Sensitivity List

• Process is sensitive to
signals on Sensitivity List
• All processes executed Sensitivity List
once at time=0
• Suspended at end of PROCESS (a, b)
BEGIN
process c <= a AND b;
END PROCESS;
• Reactivated when event
occurs on any signal in
sensitivity list

(C) P. R. Panda, I.I.T Delhi, 2017 47

 Process and Signal Assignment

ARCHITECTURE x of y IS
BEGIN
Identical
ARCHITECTURE x of y IS
PROCESS (a, b) BEGIN
BEGIN
c <= a AND b; c <= a AND b;
END PROCESS;
END x;
END x;

Need not use PROCESS for modelling simple

combinational behaviour

(C) P. R. Panda, I.I.T Delhi, 2017 48

 Process Synchronisation

• Sensitivity list is optional PROCESS

BEGIN
• wait is general c <= a and b;
synchronisation wait on a,b;
mechanism END PROCESS;

• Implicit infinite loop in PROCESS (a, b)

process Identical BEGIN
c <= a AND b;
• Execution continues until END PROCESS;
suspended by wait
statement

(C) P. R. Panda, I.I.T Delhi, 2017 49

 Synchronisation with WAITs

• Synchronisation with wait more flexible

• Both sensitivity list and wait not allowed
in same process
– process can have any number of waits
• For combinational logic, place ALL input
signals in sensitivity list
• For sequential logic, use waits
appropriately
(C) P. R. Panda, I.I.T Delhi, 2017 50
 WAIT Examples
PROCESS PROCESS
BEGIN BEGIN
wait for 10 ns; wait until clk’event and clk=‘1’;
outp <= inp; q <= d;
END PROCESS END PROCESS
Sample input every 10 ns Edge triggered flip flop

PROCESS (clk, reset)

BEGIN PROCESS
IF reset THEN BEGIN
q <= ‘0’; outp <= inp;
ELSIF clk’event and clk=‘1’ END PROCESS
q <= d;
END IF; Error! (no waits)
END PROCESS (Compare signal
assignment at
Flip flop with Reset
architecture level)
(C) P. R. Panda, I.I.T Delhi, 2017 51
 Process Variables

• Variables used for local

PROCESS
computations VARIABLE result : BIT;
– within processes BEGIN
wait until clk’event and clk=‘1’;
• Not associated with result := ‘0’;
events/transactions for i in 0 to 6 loop
result := result XOR inp (i);
– unlike signals end loop;
• Assignment of value is outp <= result;
END PROCESS;
immediate
– unlike signals

(C) P. R. Panda, I.I.T Delhi, 2017 52

 Signal Assignments in Processes
PROCESS (x)
BEGIN Multiple PROCESS
A <= ‘1’; assignments OK. VARIABLE p: BIT;
A <= ‘0’; -- overrides Sequential BEGIN
END PROCESS; Execution. -- A=‘0’ here
A <= ‘1’;
p := A; -- p=‘0’
B <= p; -- B=‘0’
PROCESS wait on x;
Signal
BEGIN END PROCESS;
assignments
-- A=‘0’ here
take effect
A <= ‘1’; Variable assignments
when process
B <= A; -- B=‘0’ take effect immediately
suspends
wait on x; (same delta)
(next delta)
END PROCESS;

(C) P. R. Panda, I.I.T Delhi, 2017 53

 Signal Assignments in Processes
PROCESS
VARIABLE p, tA, tB: BIT;
PROCESS BEGIN
Signal Assignment
VARIABLE p: BIT; tA := ‘0’;
to A equivalent to:
BEGIN if (c) then tA := ‘1’;
(1) introduction of
A <= ‘0’; else begin
temporary variable
if (c) then A <= ‘1’; p := B;
tA when A occurs
else begin tA := p;
on LHS and (2)
p := B; end
assignment of tA to
A <= p; A <= tA;
A when process
end wait on x;
suspends
wait on x; tB := A;
B <= A; tA := B;
A <= B; A <= tA;
wait on x; B <= tB;
END PROCESS; Equivalent wait on x;
END PROCESS;
(C) P. R. Panda, I.I.T Delhi, 2017 54
 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 55
 Structural Description

• Instantiation
• Interconnection

(C) P. R. Panda, I.I.T Delhi, 2017 56

 Hierarchy
ENTITY x IS
PORT (a, b: IN BIT,
c: OUT BIT); a c
END x;
ARCHITECTURE xa OF x IS x
BEGIN b z
c <= a AND b; p
r
END xa; y1
x1
ENTITY y IS q
PORT (a : IN BIT,
b: OUT BIT); a b
END y; z contains
y
ARCHITECTURE ya OF y IS instances of
BEGIN
b <= NOT a;
x and y
END xa;
(C) P. R. Panda, I.I.T Delhi, 2017 57
 Instantiation and Interconnection - 1
ENTITY z IS
PORT (p, q: IN BIT, z
p
r: OUT BIT); r
END x; x1 y1
ARCHITECTURE structural OF z IS t
COMPONENT xc
q
PORT (a, b: IN BIT; c: OUT BIT);
END COMPONENT;
COMPONENT yc
Component declaration
PORT (a: IN BIT; c: OUT BIT);
END COMPONENT; Configuration specification
FOR ALL: xc USE WORK.x (xa);
FOR ALL: yc USE WORK.y (ya); (which architecture?)
SIGNAL t: BIT; Temporary signal
BEGIN
x1: xc PORT MAP (p, q, t);
y1: yc PORT MAP (t, r); Instantiation
END structural; (C) P. R. Panda, I.I.T Delhi, 2017 58
 Instantiation and Interconnection - 2

z
Instance name p
r
x1 y1
Component name t
q

Port association list:

x1: xc PORT MAP (p, q, t); order of names
y1: yc PORT MAP (t, r); determines connectivity:
a-p
Same name b-q
implies connection c-t

(C) P. R. Panda, I.I.T Delhi, 2017 59

 Port Mapping
COMPONENT xc
PORT (a, b: IN BIT; c: OUT BIT);
END COMPONENT;

Mapping by position: preferred for short port lists

x1: xc PORT MAP (p, q, t);

Mapping by name: preferred for long port lists

x1: xc PORT MAP (b => q, a => p, c => t);

In both cases, complete port mapping should be specified

(C) P. R. Panda, I.I.T Delhi, 2017 60
 Test Benches

• Purpose - test correctness of Design

Under Test (DUT)
– provide input stimulus
– observe outputs
– compare against expected outputs
• Test Bench is also a VHDL model

(C) P. R. Panda, I.I.T Delhi, 2017 61

 Test Bench Modelling - 1

• Test bench a
separate VHDL
entity
• Ports are connected
to DUT’s ports Test
– i/p port DUT
Bench
corresponding to
DUT’s o/p port
– o/p port
corresponding to
DUT’s i/p port
(C) P. R. Panda, I.I.T Delhi, 2017 62
 Test Bench Modelling - 2

• Test bench
instantiates the DUT
Test Bench
• Stimulus generation
and output
monitoring in Test
separate VHDL Bench DUT
process Process

• Signals are Signals

connected to DUT’s
ports
(C) P. R. Panda, I.I.T Delhi, 2017 63
 Libraries and Packages

• PACKAGE - collection of
– components
– data types
– functions/procedures
• LIBRARY - collection of PACKAGEs

(C) P. R. Panda, I.I.T Delhi, 2017 64

 Packages
PACKAGE util IS
COMPONENT c IS
PORT (a: IN BIT, b: OUT BIT); Package declaration
END COMPONENT
TYPE my_int IS INTEGER RANGE -7 TO 7;
FUNCTION comp (a: BIT_VECTOR)
RETURN BIT_VECTOR;
END util;

PACKAGE BODY util IS

FUNCTION comp (a: BIT_VECTOR)
RETURN BIT_VECTOR IS Package body
BEGIN
RETURN NOT a;
END comp;
END util;
(C) P. R. Panda, I.I.T Delhi, 2017 65
 Using a Package

Package
Library Name
All
PACKAGE util IS Name
Contents
COMPONENT c IS
PORT (a: IN BIT, b: OUT BIT);
END COMPONENT
TYPE my_int IS INTEGER RANGE -7 TO 7; USE WORK.UTIL.ALL;
FUNCTION comp (a: BIT_VECTOR) ...
RETURN BIT_VECTOR;
END util;
SIGNAL x: my_int;
... a <= comp (b);

(C) P. R. Panda, I.I.T Delhi, 2017 66

 Libraries

• STD
– STANDARD
• types/utilities (BIT, TIME, INTEGER,...)
– TEXTIO
• interface to text files
• WORK
– default library for storing user designs
• STD_LOGIC_1164
– multi-valued logic
(C) P. R. Panda, I.I.T Delhi, 2017 67
 TEXTIO Package

• Data types and functions for

– reading from text files
– writing out text files
FILE f: TEXT IS “file_name”;
VARIABLE one_line: line;
VARIABLE str: STRING;
...
READLINE (f, one_line); -- read one line from file
READ (str, one_line); -- read a word from line
WRITELINE (g, one_line); -- write one line to file
WRITE (str, one_line); -- write a word into line
(C) P. R. Panda, I.I.T Delhi, 2017 68
 Design Parameterisation:
GENERICs
ENTITY e IS
GENERIC (delay: TIME := 2 NS; width: INTEGER := 4);
PORT (a: IN BIT_VECTOR (0 TO width);
b: OUT BIT_VECTOR (0 TO width));
END e;
Default
ARCHITECTURE a OF e IS Value
BEGIN
b <= NOT a AFTER delay;
END a;

Generic
Parameters

(C) P. R. Panda, I.I.T Delhi, 2017 69

 Passing GENERIC Parameters
ENTITY c IS
GENERIC (delay: TIME := 4 ns); PORT (a: IN BIT; b: OUT BIT);
END c;

ARCHITECTURE a OF e IS ARCHITECTURE def OF e IS

COMPONENT c COMPONENT c
GENERIC (t: TIME:= 4 NS); GENERIC (t: TIME:= 4 NS);
PORT (a: IN BIT, b: OUT BIT); PORT (a: IN BIT, b: OUT BIT);
END COMPONENT; END COMPONENT;
SIGNAL x, y: BIT; SIGNAL x, y: BIT;
FOR ALL: c USE work.c (arc); FOR ALL: c USE work.c (arc);
BEGIN BEGIN
c1: c GENERIC MAP (3 ns) c1: c PORT MAP (x, y);
PORT MAP (x, y); END def;
END a; Default Delay = 4 ns
Delay parameter = 3 ns
(C) P. R. Panda, I.I.T Delhi, 2017 70
 Conditional and Looped
Instantiation
Number of instances of DFF determined by Generic Parameter n

Inp Outp

DFF_0 DFF_1 DFF_2 DFF_n

Clk

(C) P. R. Panda, I.I.T Delhi, 2017 71

 Conditional and Looped
Instantiation: GENERATE
GENERIC (n: INTEGER)...
... Need intermediate
SIGNAL t: BIT_VECTOR (0 TO n-1); signal t (0 to n-1)
t (0) t (1) t (2) t (n-1)

Inp Outp

DFF_0 DFF_1 DFF_2 DFF_n

Clk

(C) P. R. Panda, I.I.T Delhi, 2017 72

 GENERATE Statement
SIGNAL t: BIT_VECTOR (0 TO n-1);
...
dff_0: DFF PORT MAP (Inp, Clk, t (0));
dff_n: DFF PORT MAP (t (n-1), Clk, Outp);
FOR i IN 1 TO n-1 GENERATE
dffx: DFF PORT MAP ( t (i-1), Clk, t (i) );
END GENERATE;

Inp t(0) t(1) t(2) t(n-1) Outp

DFF_0 DFFX(1) DFFX(2) DFF_n

Clk

(C) P. R. Panda, I.I.T Delhi, 2017 73

 Contents

• Introduction
• Signal assignment
• Modelling delays
• Describing behaviour
• Structure, test benches, libraries,
parameterisation
• Standards
(C) P. R. Panda, I.I.T Delhi, 2017 74
 VHDL Standards

• Std_LOGIC 1164 Package

– IEEE Standard
– Supported by all VHDL
simulation/synthesis tools
• VITAL
– Modelling timing in VHDL

(C) P. R. Panda, I.I.T Delhi, 2017 75

 9-valued Logic Type: std_ulogic

• Modelling CMOS TYPE std_ulogic IS (

‘U’, -- uninitialised
– Current strengths ‘X’, -- unknown
– Tristating ‘0’, -- Forcing 0
‘1’, -- Forcing 1
• Modelling Don’t Care ‘Z’, -- High impedance
‘W’, -- Weak Unknown
• Simulation Values ‘L’, -- Weak 0
– Unknown ‘H’, -- Weak 1
‘-’, -- Don’t care
– Uninitialised
);

(C) P. R. Panda, I.I.T Delhi, 2017 76

 Signal Drivers
ARCHITECTURE x...
SIGNAL a: BIT;
begin
PROCESS
begin
... Driver for a
a <= ‘1’;
...a <= ‘0’;... Multiple drivers
end; not allowed for
PROCESS
begin same signal!
... Driver for a - leads to conflicts
a <= ‘0’;
...
end; Driver for a
a <= ‘0’;
end x;
(C) P. R. Panda, I.I.T Delhi, 2017 77
 Resolution Functions

• Multiple drivers allowed only when signal is

declared to be RESOLVED
– using RESOLUTION FUNCTION

FUNCTION res (values: BIT_VECTOR) RETURN BIT IS

VARIABLE accum : BIT := ‘1’;
BEGIN Multiple driving
FOR i IN values’RANGE LOOP values treated
accum := accum AND values(i); as vector
END LOOP;
RETURN accum; Modelling
END; Wired AND

(C) P. R. Panda, I.I.T Delhi, 2017 78

 Resolving std_ulogic Signals
• Models the effect of shorting two wires in CMOS
TYPE stdlogic_table is array(std_ulogic, std_ulogic)
of std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
-- U X 0 1 Z W L H -
('U','U','U','U','U','U','U','U','U' ), -- | U |
('U','X','X','X','X','X','X','X','X' ), -- | X |
('U','X','0','X','0','0','0','0','0' ), -- | 0 |
('U','X','X','1','1','1','1','1','1' ), -- | 1 |
('U','X','0','1','Z','W','L','H','Z' ), -- | Z |
('U','X','0',’1','W','W','W','W','W' ), -- | W |
('U','X','0','1','L','W','L','W','L' ), -- | L |
('U','X','0','1','H','W','W','H','H' ), -- | H |
('U','X','0','1','Z','W','L','H',‘-' ) -- | - | );

(C) P. R. Panda, I.I.T Delhi, 2017 79

 Resolution Function for std_ulogic

FUNCTION resolved ( s : std_ulogic_vector )

RETURN std_ulogic IS
VARIABLE result : std_ulogic := ‘-';-- weakest state default
BEGIN
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE -- Iterate through all inputs
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP; -- Return the resultant value
RETURN result;
END IF;
END resolved;

(C) P. R. Panda, I.I.T Delhi, 2017 80

 Resolved Type: std_logic

• Multiple std_ulogic types resolved into

std_logic type
SUBTYPE std_logic IS resolved std_ulogic;
... unresolved
type
SIGNAL x: std_logic;
... resolution
x <= ‘Z’; function
x <= ‘1’; resolved
-- No conflict. Value of x resolves to ‘1’ type

(C) P. R. Panda, I.I.T Delhi, 2017 81