De La Salle University – Dasmariñas

College of Engineering, Architecture and Technology

CPET428L: COMPUTER SYSTEMS ARCHITECTURE LAB

Experiment # 3
DESIGN OF CARRY LOOKAHEAD ADDERS

Submitted by:
AURE, RECHELLE ANNE D. (CPE51)
EDON, SEAN DARWIN S. (CPE51)
PALINO, PAULA CAMILLE A. (CPE41)
MAULION, JOHN MICHAEL V. (CPE52)

Date Performed: February 22, 2020

Submitted to:
ENGR. MICHAEL OLIVO
I. RESULTS

1. Design of Carry Lookahead Adders

2. Truth Table
A B C C+1 Condition
0 0 0 0 No Carry
 0 0 1 0
Generate
0 1 0 0
0 1 1 1
No Carry
1 0 0 0
Propogate
1 0 1 1
1 1 0 1 Carry
1 1 1 1 Generate

3. Advantages of Carry Lookahead Adders

NAME: AURE, RECHELLE ANNE D.

II. OBSERVATION
In this experiment, the group constructed and designed a carry lookahead adders with the
use of Multisim software application. It is consists of two exclusive-or gates, two AND gates
and one OR gate which represents the carry out bit.
The addition of two 1-digit inputs A and B is said to generate if the addition will always
carry, regardless of whether there is an input-carry (equivalently, regardless of whether any less
significant digits in the sum carry). The addition of two 1-digit inputs A and B is said to
propagate if the addition will carry whenever there is an input carry (equivalently, when the
next less significant digit in the sum carries).

III. CONCLUSION
The ripple-carry adder limiting factor is the time it takes to propagate the carry and the
carry look-ahead adder solves this problem by calculating the carry signals in advance, based
on the input signals. The result is a reduced carry propagation time. To be able to understand
how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing
with the full adder.
A carry look-ahead adder reduces the propagation delay by introducing more complex
hardware. In this design, the ripple carry design is suitably transformed such that the carry
 logic over fixed groups of bits of the adder is reduced to two-level logic. They work by
creating two signals P and G known to be Carry Propagator and Carry Generator. The carry
propagator is propagated to the next level whereas the carry generator is used to generate the
output carry ,regardless of input carry. The number of gate levels for the carry propagation can
be found from the circuit of full adder. The signal from input carry Cin to output carry Cout
requires an AND gate and an OR gate, which constitutes two gate levels.

NAME: EDON, SEAN DARWIN S.

I. OBSERVATION

In this experiment, we are tasked to make and build a carry lookahead adders. A
carry-Lookahead adder is a fast parallel adder as it reduces the propagation delay by more
complex hardware, hence it is costlier. In this design, the carry logic over fixed groups of
bits of the adder is reduced to two-level logic, which is nothing but a transformation of
the ripple carry design. It is also fast parallel adder as it reduces the propagation delay by
more complex hardware, hence it is costlier. In this design, the carry logic over fixed
groups of bits of the adder is reduced to two-level logic, which is nothing but a
transformation of the ripple carry design.

II. CONCLUSION

In conclusion, The carry lookahead adder is a faster circuit for adding binary
numbers because it reduces the propagation time of carry values Doing more work does
not necessarily make a circuit slower. Circuits are inherently parallel, and you only count
serial operations when discussing speed. Designing circuits involves trade-offs among
speed, complexity, size and power.
NAME: PALINO, PAULA CAMILLE A.

I. OBSERVATION
For this experiment we were tasked to design a carry lookahead adder using multisim. A carry
lookahead adder is said to be a very superior adder in terms of speed when compared to full
adder. Speed is the most important factor in efficiency of any digital circuit. Inside the adder
are gates specifically the XOR, AND, and OR gates. Each and every gate will thake some time
to produce the output depending upon the input. In CLA we have something called a
propogation delay. Propogation delay is stated to be “the time required for a digital signal to
travel from the input of a logic gate to the output.” The advantages of a carry lookahead adder
are the decreased of propogation delay and it provides the fastest addition logic. Some of its
disadvantages are The Carry Look-ahead adder circuit gets complicated as the number of
variables increase. The circuit is costlier as it involves a greater number of hardware. For the
CLA, the carry-in bits of each adder component do not have wait for the pervious adder to
compute the carryout bit.
 II. CONCLUSION
We use carry lookahead adder if we want the addition process of logic gates to be faster,
and it eliminates the problem due to interstage carry delay. The carry-look ahead adder calculates
one or more carry bits before the sum, which reduces the wait time to calculate the result of the
larger value bits. The design of a carry lookahead adder is to reduce the computation time, they
work by creating two signals carry propagator and carry generator. The carry generator is used to
generate the output carry and the carry propagator is propagated to the next level. A carry
lookahead adder explicitly the high-speed adder are used as implemented ICs.

NAME: MAULION, JOHN MICHAEL V.

I. OBSERVATION

On this experiment, we desgined a carry lookahead adders and tried to find the truth table of
it. We needed 2 XOR, 2 AND and 1 OR gate/s to made the carry lookahead adders. According to
the diagram, the A and B input needed to pass through the XOR gate and an AND gate first, then
the output of the XOR gate must pass through to an another XOR gate and an another AND gate,
but they will be combined by an another input which is the Carry-in. The output of the last XOR
gate will be the SUMMATION OUTPUT. The two AND gate will pass through an OR gate and
its output will be the CARRY OUT
 II. CONCLUSION
The carry lookahead adder is a faster circuit for adding binary numbers because it reduces the
propagation time of carry values. The idea behind the carry lookahead adder is that we don’t wait
for the carries to ripple through the circuit. Instead we figure out ahead of time where the carries
will come into play.