March 28, 2007 Exercice Session Intgrated System Design

Number 3 Prof. G. De Micheli

ARM INSTRUCTION SET

OVERALL DESCRIPTION:

The ARM architecture (Acorn RISC Machine) is a 32-bit RISC processor architecture widely
used in embedded and low power applications. Nowadays, the most important chip
manufacturers have licensed the basic ARM design for various uses. Today it counts for over
75% of all 32-bit embedded CPUs.

The ARM architecture comes in various versions (ARM7, ARM9, Cortex, XScale…) with
different architectures (von Neumann, Harvard) and variable features (pipeline, memory
management unit (MMU), speed…). In the following, we will concentrate on the functionality
of a version 7 ARM instruction set.

ARM allows addresses to be 32-bit long. An address refers to a byte (8 bits), not a word (32
bits). Therefore, the word 0 in ARM address space is located at location 0; the word 1 is at 4
and so on…

ARM REGISTERS:

ARM has load-store architecture: data operands must first be loaded into the CPU, and then
stored back to main memory to save the results. It has 16 general-purpose registers, r0
through r15. Except for r15, they are identical. The r15 register has the same capabilities as
the other registers, but it can also be used as a program counter (PC).

The other important basic register is the current program status register (CPSR). This
register is set automatically during every arithmetic, logical, or shifting operation. The top 4
bits hold the following information of that operation:
• The Negative (N) bit is set when the result is negative in two’s-complement
arithmetic.
• The Zero (Z) bit is set when every bit of the result is zero.
• The Carry (C) bit is set when there is a carry out of the operation.
• The Overflow (V) bit is set when an arithmetic operation results in an overflow.

ARM INSTRUCTIONS:

The major assembly instructions for data operations are summarized in the annex. They
allow arithmetic, logical and shift/rotate operations, as well as comparison, and data moving
and loading. The shift/rotate operations are considered as additional operands to the
previous operation. On the other hand, one should separately consider the branch instruction

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B which sets the PC register at a position corresponding to the operand of the B instruction,
i.e. it defines the next instruction to be executed. The branching can be achieved with or
without conditions. The whole branching instruction set is shown in the last table of the
annex.
QUESTIONS:

1) What would the ARM status be (NZCV bits) after the following operations?
a. 2 – 3
b. -4 + 5
c. -1 + 1
d. 231 – 1 + 1

2) Implement the following C assignments in ARM instructions:

3) A finite impulse response (FIR) filter is a commonly used method for processing
signals. A signal x0 feeds the FIR. It goes through n successive delay stages; the
obtained delayed forms of x0 are noted x1 through xn. The signal processing consists in
amplifying the delayed forms of x0 and summing them up. The mathematical
expression of a FIR filter is a simple multilinear form: f = ∑ c i ⋅ x i (Figure 1).
1≤ i ≤ n

c1 c2 cn-1 cn
Δ Δ Δ
x0 x1 x2 xn-1 xn
Figure 1

Implement a FIR filter in C then in ARM instructions for a given number of stages n.

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ANNEX

Arithmetic
Inst. Example Explanation
ADD ADD r0, r1, r2 r0 Í r1 + r2 without carry
ADC ADC r0, r1, r2 r0 Í r1 + r2 with carry
SUB SUB r0, r1, r2 r0 Í r1 - r2 without carry
SBC SBC r0, r1, r2 r0 Í r1 - r2 with carry
RSB RSB r0, r1, r2 r0 Í r2 - r1 without carry
RSC RSC r0, r1, r2 r0 Í r2 - r1 with carry
MUL MUL r0, r1, r2 r0 Í r1 * r2; different registers r1and r2
MLA MLA r0, r1, r2, r3 r0 Í r1 * r2 + r3

Logical
Inst. Example Explanation
AND AND r0, r1, r2 r0 Í r1 AND r2 bitweise
ORR ORR r0, r1, r2 r0 Í r1 OR r2 bitweise
EOR EOR r0, r1, r2 r0 Í r1 XOR r2 bitweise
BIC BIC r0, r1, r2 r0 Í r1 AND NOT(r2) bitweise

Shift/Rotate
Inst. Example Explanation
LSL LSL r0 Logic shift of r0’s bits to the left, fill with 0
LSR LSR r0 Logic shift of r0’s bits to the right, fill with 0
ASL ASL r0 Arithmetic shift: similar to LSL, conserves the sign bit
ASR ASR r0 Arithmetic shift: similar to LSR, conserves the sign bit
ROR ROR r0 Rotates r0 to the right
RRX RRX r0 Rotates r0 to the right, inserts C bit above the sign bit

Comparison
Inst. Example Explanation
CMP CMP r0, r1 Computes r0 - r1 and sets NZCV bits

Move
Inst. Example Explanation
MOV MOV r0, r1 r0 Í r1
MVN MVN r0, r1 r0 Í one’s complement of r1

Load/Store and Pseudo-Operations

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 LDR r0, [r1] Load r0 with address r1
LDR LDR r0, [r1, -r2] Other variant: load r0 with address r1 – r2
LDR r0, [r1, #4] Other variant: load r0 with address r1 + 4
STR STR r0, [r1] Store r0 into address r1 (variants above possible)
LDRH LDRH r0, [r1] Like LDR for half word (16 bits)
STRH STRH r0, [r1] Like STR for half word (16 bits)
LDRB LDRB r0, [r1] Like LDR for one byte (8 bits)
STRB STRB r0, [r1] Like STR for one byte (8 bits)
ADR ADR r0, 0x100 Load r0 with address 0x100

Branching
Inst. Example Explanation
B B label PC Í instruction labeled label
BEQ BEQ label Equals zero: B label for Z=1
BNE BNE label Not equal zero: B label for Z=0
BCS BCS label Carry set: B label for C=1
BCC BCC label Carry clean: B label for C=0
BMI BMI label Minus: B label for N=1
BPL BPL label Nonnegative (plus): B label for N=0
BVS BVS label Overflow: B label for V=1
BVC BVC label No overflow: B label for V=0
BHI BHI label Unsigned higher

BLS BLS label Unsigned lower or same

BGE BGE label Signed greater than or equal

BLT BLT label Signed less than

BGT BGT label Signed greater than

BLE BLE label Signed less than or equal