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Instruction Set
Instruction set defines the operations that can change the state. ARM
instructions are all 32bit long are all 32-bit long (except for Thumb mode) There
are 232 possible machine instructions.
Features of ARM instruction set
1. Load-store architecture
2. 3-address instructions
3. Conditional execution of every instruction
4. Possible to load/store multiple registers at once
5. Possible to combine shift and ALU operations in a single instruction
Data Processing Instruction
Data processing instructions are move, arithmetic, logical, comparison and
multiply instructions. The load / store instruction only work on registers, NOT
memory. They each perform a specific operation on one or two operands.

Sr. No. Instruction type Instructions

1 Arithmetic ADD, ADC, SUB, SBC, RSB, RSC
2 Logical AND, ORR, EOR, BIC
3 Comparisons CMP, CMN, TST, TEQ
4 Data movement MOV, MVN

MOV and MVN Instruction

MOV instruction move the data from one register to another register.
Format is as follows :
MOV destination_reg , source_reg
Registers R1 to R12 can be used for data movement. These are the general
purpose registers. The register R13, R14 and R15 are also used for data
movement.
The "MVN" stands for "MOVE Negated". Toggling is done by using MVN
instruction. Toggling means switching between 0 and 1. The easiest type of

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toggling is just switching all the bits in a register. This is easily done with a MVN
instruction.
The syntax of MVN instruction :
MVN (first_register),(second_register)

Example : MVN rO, r2

Move the complemented value of r2 to rO
All the bits in the second_register will switch (1 to 0 or 0 to 1) and then the result
will be stuck in the first_register.
Example :
MOV R5, R7 ; copy content of R7 to R5
MOV R9, R3 ; copy content of R3 to R9
MVN Rl, R4 ; move the complemented value of R4 to R1
Shift and Rotate
Logical and arithmetic are the two shift types. There are six mnemonics for
the different shift types :
a) Logical Shift Left (LSL)
b) Arithmetic Shift Left (ASL)
c) Logical Shift Right (LSR)
d) Arithmetic Shift Right (ASR)
e) Rotate Right (ROR)
f) Rotate Right with Extend (RRX)
Logical Shift Left
Shifts left by the specified amount. LSL means "logical shift left by the
specified number of bits." This instruction is executed in a single clock cycle.
Example : LSL # n

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Here n is the number of bit positions by which the value is shifted. Shifting
left by n-bit on a signed or unsigned binary number has the effect of multiplying
it by 2n.

Logical Shift Right (LSR)

LSR by 0 to 32 places, fill the vacated bits at the most significant end of
the word with zeros.
Logical shifts can be useful as efficient ways of performing multiplication
or division of unsigned integers by powers of two.
Shifting right by n-bit on an unsigned binary number has the effect of
dividing it by 2n.

Arithmetic Shift Left and Right

Arithmetic Shift Left (ASL) is same as logical shift left.
Arithmetic Shift Right (ASR) by 0 to 32 places, fill the vacated bits at the
most significant end of the word with zeros if the source operand was positive
and with ones it is negative.

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Rotate Right (ROR)

Rotate right by 0 to 32 places. The last bit rotated out is available in the
carry flag. Rotate left instruction is not used in ARM processor.
Rotate left by "n" positions is the same as a rotate right by (32 - n).

Rotate Right Extended (RRX)

It is always rotate by one bit only.

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The vacated bit is filled with the old value of the C flag and the operand is
shifted one place to the right. This operation uses the CSPR C flag as a 33rd bit.
Conditional Code Instruction
ARM processor supports for conditional execution. The instruction is
executed only when condition is true. Any data processing instruction is used for
this purpose.
Most instruction sets only allow branches to be executed conditionally.
However by reusing the condition evaluation hardware, ARM effectively
increase number of instruction. All instructions contain a condition field which
determines whether the CPU will execute them.
Bits 28 to 31 of each ARM instruction provide a condition field that defines
whether the current instruction is to be executed.

Suffix Description Flags tested

EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Minus N=1
PL Positive or zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C = 1 and Z = 0
LS Unsigned lower or same C = 0 or Z = 1
GE Greater or equal N=V
LT Less than N! = V
GT Greater than Z = 0 and N = V
LE Less than or equal Z = 1 or N = !V
AL Always
Condition codes are simply a way of testing the ALU status flags.

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Example :
ARM code
C language code
Unconditional code Conditional code
if (rO == 0) CMP rO, #0 CMP rO, #0
{ BNE else ADDEQ rl, rl, #1
rl = rl + 1; ADD rl, rl, #1 ADDNE r2, r2, #1
} B end
else else
{ ADD r2, r2, #1
r2 = r2 + 1; end
}
If the conditional sequence is three instructions or less, it is better to use
conditional execution than a branch.
Condition if ((RO==R1) && (R2==R3)) R4++
CMP RO, R1 BNE loop
CMP R2, R3
Unconditional
BNE loop
ADD R4, R4, #1 loop :...
CMP RO, R1
Conditional CMPEQ R2, R3
ADDEQ R4, R4, #1
If corresponding condition is true, the instruction is executed. If the
condition is false, the instruction is turned into a nop. The condition is specified
by suffixing the instruction with a condition code mnemonic.
Compare Instruction
These four instructions set the status bits/flags (N, Z, C, V) in the PSR
according to the results of their operations.
CMP : Compare, using subtraction
CMN : Compare negated, using addition
TEQ : Test for equality, using XOR - does not affect V flag
TST : Test bit(s), using AND - does not affect V flag
Comparison is done by using subtraction operation. Source and destination
value is not changed only conditional flags are affected.

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Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd.
They are used only to perform tests and to set the condition codes on the result
and always have the S bit set.
Logic :
AND Rd, Rn, Rm
Performs the bit-wise logical AND of the operands in registers Rn and Rm
and writes the result into register Rd.
The Bit Clear Instruction ( BIC) is closely related to the AND instruction.
The bits of Rm are complemented before they are ANDed with the bits of Rn.
If RO = 02FA62CA
Rl = OOOOFFFF
BIC RO, RO, Rl
results In 02FA0000 being written Into RO
Test instruction syntax :
TST Rn, Rm or #value
It performs bit-wise logical AND of the two operands, then sets condition code
flags.
Example : TST R2, #1
sets Z 1 if low-order bit of R2 is 0
sets Z  0 if low-order bit of R2 is 1
TEQ instruction :
TEQ Rn, Rm or #value
It performs bit-wise logical XOR of the two operands, then sets condition code
flags.
Example : TEQ R2, #5
sets Z  1 if R2 contains 5
sets Z  0 otherwise

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TST and TEQ instruction does not affect V flag. The TST instruction is
useful to determine if one or more bits are set and it is often used with a constant
called a "MASK".
TEQ instruction is useful for determining if the content of two registers
contains identical values.
Multiplication Instruction
Multiplication instruction takes more than one cycle. it also requires hardware to
perform operation.
Multiply
Syntax : MUL Rd, Rm, Rs
where Rd = Destination register
Rm, Rs = Source register
Example : MUL RO, R1, R2 @ RO = R1 x R2
Features :
1. Second operand cannot be immediate.
2. The result register must be different from the first operand.
3. if S bit is set, C flag is meaningless.
Multiple Register Load and Store
These instructions transfer large quantities of data more efficiently. It is
used for procedure entry and exit for saving and restoring workspace registers
and the return address.
LDM Instruction
LDR and STR instructions only load/store a single 32-bit word. ARM
processor can load/store ANY subset of the 16 registers in a single instruction.

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STM Instruction
Any registers can be specified. However, beware that if you include rl5
(PC), you are effectively forcing a branch in the program flow.
The complementary instruction to LDMIA is the STMIA instruction :
STMIA rl, {rO, r2, r4} ; mem32[rl] : = rO
; mem32[rl + 4] : = r2
; mem32[rl + 8] : = r4
The Load and Store Multiple Instructions (LDM/STM) allow between 1
and 16 registers to be transferred to or from memory. The order of register transfer
cannot be specified, order in the list is insignificant.
The lowest register number is always transferred to/from lowest memory
location accessed. The transferred registers can be either :
1. Any subset of the current bank of registers (default)
2. Any subset of the user mode bank of registers when in a privileged
mode (postfix instruction with a "A")
Base register used to determine where memory access should occur at four
different addressing modes and base register can optionally update following the
transfer.
Branch Instruction
The branch instructions cause the processor to execute instructions from a
different address. Two branch instruction are available B and BL. These
instructions are only executed if the condition is true.
The BL instruction in addition to branching, also stores the return address in the
lr register, and hence can be used for sub-routine invocation.
A simple branch or branch with link instruction :
B{condition} <address>
BL{condition} <address>
Bits [27:25] identify this as a B or BL instruction, they have values 101
only for these instructions.

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The top 4 bits [31:28] are used to specify the conditions under which the
instruction is executed, this is common with all other instructions.
The L-bit (bit 24) is set if it is a branch with link instruction and clear if it
is a plain branch. BL is jump to subroutine instruction.
24-bit signed offset specifies destination of branch in 2's complement form.
The word offset is shifted left by 2 bits to form a byte offset. This offset is added
to the PC by the processor.
The instruction can therefore specify a branch of +/- 32 Mbytes. The branch
offset must take account of the prefetch operation, which causes the PC to be 2
words (8 bytes) ahead of the current instruction.
Branches beyond +/- 32 Mbytes must use an offset or absolute destination
which has been previously loaded into a register.
Branch with Link (BL) writes the old PC into the link register (R14) of
the current bank. The PC value written into R14 is adjusted to allow for the
prefetch, and contains the address of the instruction following the branch and link
instruction. Note that the CPSR is not saved with the PC.
Stores return address in LR. Returning implemented by restoring the PC
from LR. For non-leaf functions, LR will have to be stacked.

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