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VLSI Design: Dept. of CSE Bangladesh University

The document describes the 15 step CMOS fabrication process. It begins with a p-type silicon substrate which undergoes oxidation, photolithography, etching, and diffusion steps to create n-well and p-type and n-type doped regions. Metalization is then added through sputtering and patterning of aluminum to connect the transistors and form integrated circuits on the chip. The process takes place in clean rooms and involves masking, etching, and diffusion to build up the transistor components in a layer-by-layer self-aligned process on the silicon wafer.

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Imran Hossain
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54 views19 pages

VLSI Design: Dept. of CSE Bangladesh University

The document describes the 15 step CMOS fabrication process. It begins with a p-type silicon substrate which undergoes oxidation, photolithography, etching, and diffusion steps to create n-well and p-type and n-type doped regions. Metalization is then added through sputtering and patterning of aluminum to connect the transistors and form integrated circuits on the chip. The process takes place in clean rooms and involves masking, etching, and diffusion to build up the transistor components in a layer-by-layer self-aligned process on the silicon wafer.

Uploaded by

Imran Hossain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Design

CSE-3106

Dept. of CSE
Bangladesh University
CMOS Fabrication

 CMOS transistors are fabricated on silicon wafer.


 Chips are built in huge factories called fabs.
 Contain clean rooms as large as football fields.
Step 1: Substrate

 Primarily, start the process with a p-substrate.

p substrate
Step 2: Oxidation

 Grow SiO2 on top of Si wafer


 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate
Step 3: Photoresist

 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Softens where exposed to light

Photoresist
SiO2

p substrate
Step 4: Lithography

 Expose photoresist through n-well mask

Photoresist
SiO2

p substrate
Step 5: Etching

 Etch oxide with hydrofluoric acid (HF)


 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate
Step 6: Strip Photoresist

 The remaining photoresist is stripped off using the mixture of acids called piranah
etch.

SiO2

p substrate
Step 7: n-well

 n-well is formed with diffusion or ion implantation

SiO2

n well
Step 8: Strip Oxide

 Strip off the remaining oxide using HF

n well
p substrate
Step 9: Polysilicon

 Deposit very thin layer of gate oxide


 Chemical Vapor Deposition (CVD) of silicon layer

Polysilicon
Thin gate oxide

n well
p substrate
Step 10: Polysilicon Patterning

 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
Step 11: Self-Aligned Process

 Use oxide and masking to expose where n+ dopants should be diffused or


implanted
 N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate
Step 12: N-diffusion

 Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate
N-diffusion cont.

 Historically dopants were diffused

n+ n+ n+

n well
p substrate
N-diffusion cont.

 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate
Step 13: P-Diffusion

 Similar set of steps form p+ diffusion regions for pMOS source and drain and
substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate
Step 14: Contacts

 Now we need to wire together the devices


 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide


p+ n+ n+ p+ p+ n+

n well
p substrate
Step 15: Metalization

 Sputter on aluminum over whole wafer


 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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