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Fabrication

The document outlines the fabrication processes for nMOS and pMOS transistors, detailing steps such as oxidation, photolithography, diffusion, and metallization. It describes the creation of insulating layers, the introduction of dopants, and the deposition of materials to form the transistors. Additionally, it explains CMOS technology, which integrates both types of transistors on a single chip using various fabrication methods.

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7 views4 pages

Fabrication

The document outlines the fabrication processes for nMOS and pMOS transistors, detailing steps such as oxidation, photolithography, diffusion, and metallization. It describes the creation of insulating layers, the introduction of dopants, and the deposition of materials to form the transistors. Additionally, it explains CMOS technology, which integrates both types of transistors on a single chip using various fabrication methods.

Uploaded by

shantanukk0108
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Fabrication process

1. Oxidation: 3. Diffusion:
This process involves creating an insulating layer of silicon A process in which P+/N+ regions (such as source and drain
dioxide (SiO₂) with a thickness of 1 µm on the silicon regions) are created by passing a gas containing impurities at
substrate. It is essential to isolate the transistor from other high temperatures into the substrate, allowing the impurities
devices and regions on the chip. to diffuse into specific regions.
4. Chemical Vapor Deposition (CVD):
This technique is used to deposit polysilicon at the gate
terminal. CVD involves the reaction of gaseous chemicals to
form a solid material on the substrate, which in this case is
polysilicon.
5. Ion Implantation:
A process for creating the channel region between the
2. Photolithography: source and drain terminals in the transistor. High-energy ions
This technique consists of three steps: are implanted into the substrate to form the channel,
a. Depositing Photoresist Layer: A light-sensitive controlling the conductivity in the MOSFET.
material (photoresist) is applied over the surface. 6. Metallization:
The process of creating electrical contacts with the source,
b. Applying UV Rays through a Mask: UV light is drain, and gate terminals by depositing metal (e.g., copper
projected through a mask to define specific patterns on wires). This step ensures proper connectivity between the
the photoresist. terminals and external circuitry.
c. Etching: The areas exposed to UV light are selectively
etched away to form the desired pattern on the
substrate.
Fabrication of the nMOS Transistor

7. Polysilicon Deposition via Chemical Vapor Deposition (CVD):


1. Start with p-type Silicon Substrate: Use chemical vapor deposition
Begin the process with a p-type silicon (CVD) to deposit a layer of
substrate as the base for nMOS fabrication. polysilicon at the center, which will
act as the gate electrode.
2. Oxidation to Deposit Oxide Layer:
Use the oxidation process to 8. Photolithography to Create
deposit a 1 µm thick silicon Window for N+ Diffusion:
dioxide (SiO₂) layer on the surface Apply photolithography again to
of the p-type substrate. open a window in the oxide layer,
preparing the regions for the
3. Apply Photoresist Layer: diffusion of N+ impurities (source
Coat the surface with a and drain regions).
photoresist layer, which will
help in patterning the areas 9. N+ Region Formation by Diffusion:
for subsequent steps. Perform the diffusion process to
introduce N+ impurities into the
4. Expose Photoresist to UV Light two regions on either side of the
through Mask: polysilicon gate, forming the
Expose the photoresist to UV rays source and drain regions.
using a mask, which will define the
regions where the oxide should remain 10. Metallization to Deposit
and where it should be etched away. Aluminum (Al):
Use the metallization process to
5. Etching: deposit a layer of aluminum (Al)
Perform the etching process to across the entire substrate to
remove the unwanted soft areas create electrical contacts.
of the photoresist and oxide,
exposing the underlying silicon 11. Remove Excess Metal and
where the nMOS will be created. Deposit Insulating Oxide:
Finally, remove the excess metal and deposit another oxide layer to insulate the
6. Second Oxidation to Form Thin Oxide Layer: structure and prevent unwanted contacts, completing the nMOS transistor
After etching, carry out fabrication.
another oxidation process
to create a thin SiO₂ layer
on the exposed silicon
surface. This will serve as
the gate oxide.

Fabrication of pMOS is same, just swap, n-type to p-type, and p-type to n-type
CMOS Fabrication
CMOS technology integrates both nMOS and pMOS transistors on the same chip. The nMOS and pMOS are connected in a complementary way, with:
• pMOS connected between Vdd and the output.
• nMOS connected between the output and ground.
To fabricate both types of transistors, wells are created:
• p-well in an n-type substrate (for nMOS).
• n-well in a p-type substrate (for pMOS).
There are three main CMOS fabrication methods:
1. N-well process
2. P-well process
3. Twin-tub process (both wells created).

1. Start with p-type Silicon Substrate and Grow Oxide Layer: Begin with a p-type silicon substrate and grow a thick silicon dioxide (SiO₂) layer
via oxidation to insulate the surface.

2. Photoresist Application and Patterning: Apply a photoresist layer and expose it to UV light through a mask. This defines the areas for the n-
well formation. Etch the SiO₂ in the exposed regions, revealing the p-substrate.

3. N-Well Formation: Perform ion implantation or diffusion to introduce n-type dopants, creating the n-well region in the exposed silicon. A new
oxide layer is grown to protect the n-well.
4. Gate Oxide and Polysilicon Deposition: Grow a thin gate oxide layer over the entire surface, followed by chemical vapor deposition (CVD) of
polysilicon, which will form the gate electrode.
5. Polysilicon Patterning: Use photolithography to pattern the polysilicon, defining the gate region for the transistor.

6. Source/Drain Window Creation and Diffusion: Open windows in the oxide layer using photolithography, then introduce n+ and p+ dopants to
form the source and drain regions for both nMOS and pMOS transistors.

7. Metallization and Contact Formation: Deposit metal (usually aluminum) to form electrical contacts for the gate, source, and drain. Pattern
the metal to interconnect the devices.

8. Final Oxide Layer and Metallization: Deposit a protective oxide layer over the entire structure and open windows for metal contacts,
completing the metallization process.

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