Computer Organization &

Assembly Languages

Floating-Point Processing

Pu-Jen Cheng

Adapted from the slides prepared by Kip Irvine for the book,
Assembly Language for Intel-Based Computers, 5th Ed.
And prepared by Behrooz Parhami for the book, Computer
Architecture, 2005
 Outline

„ Floating-Point Binary Representation

„ Floating-Point Unit
Decimal Fractions vs Binary Floating-Point
 Floating-Point Binary Representation

„ IEEE Floating-Point Binary Reals

„ The Exponent
„ Normalized Binary Floating-Point Numbers
„ Creating the IEEE Representation
„ Converting Decimal Fractions to Binary Reals
 IEEE Floating-Point Binary Reals
„ Types
¾ Single Precision
„ 32 bits: 1 bit for the sign, 8 bits for the exponent,

and 23 bits for the fractional part of the significand.

¾ Double Precision
„ 64 bits: 1 bit for the sign, 11 bits for the exponent,

and 52 bits for the fractional part of the significand.

¾ Double Extended Precision
„ 80 bits: 1 bit for the sign, 16 bits for the exponent,

and 63 bits for the fractional part of the significand.

 Single-Precision Format (short real)
Sign
1 8 23
„
exponent fraction
¾ 1 = negative, 0 = positive
„ Significand sign

¾ decimal digits to the left & right of decimal point

¾ weighted
i h d positional
ii l notation
i
¾ Example:
123.154 = (1 x 102) + (2 x 101) + (3 x 100) + (1 x 10–1)
+ (5 x 10–2) + (4 x 10–3)
„ Exponent
¾ unsigned integer
¾ integer bias (127 for single precision)
approximate normalized range: 2-126 to 2127
 Single-Precision Format (cont.)
„ Biased Exponent = Actual Exponent + 127

„ Normalized: a single 1 appears to the left of the binary point

„ Unnormalized: exponent is zero
 Examples (Single Precision)
„ Order: sign bit, exponent bits, and fractional part
 ANSI/IEEE Standard Floating-Point Format

Short exponent range is –127 to 128

Short (32-bit) format but the two extreme values
are reserved for special operands
(similarly for the long format)
8 bits, 23 bits for fractional part
bias = 127, (plus hidden 1 in integer part)
–126 to 127

Sign Exponent Significand

11 bits,
bias = 1023, 52 bits for fractional part
–1022 to 1023 (plus hidden 1 in integer part)

Long (64-bit) format

 Real-Number Encodings
„ Normalized finite numbers
¾ all the nonzero finite values that can be encoded in a
normalized real number between zero and infinity
„ Positive and Negative Infinity
„ N N (not
NaN ( t a number)
b )
¾ bit pattern that is not a valid FP value
¾ Two types: quiet, signaling
Specific encodings (single precision)
 Distribution of Floating-point Numbers on the Real Line

±0, ±∞, NaN Denormals:

1.f × 2e 0.f × 2emin
Denormals allow
graceful underflow

Negative numbers Positive numbers

–∞ max – FLP – min – ±0 min + FLP + max + +∞

Sparser Denser Denser Sparser

Overflow Underflow Overflow

region regions region

Midway Underflow Typical Overflow

example example example example
 Converting Single-Precision to Decimal

1. If the MSB is 1, the number is negative; otherwise, it is positive.

2. The next 8 bits represent the exponent. Subtract binary 01111111
(decimal 127), producing the unbiased exponent. Convert the unbiased
exponent to decimal.
3. The next 23 bits represent the significand. Notate a “1.”, followed by
the significand bits. Trailing zeros can be ignored. Create a floating
floating-
point binary number, using the significand, the sign determined in step
1, and the exponent calculated in step 2.
4. Unnormalize the binary number produced in step 3. (Shift the binary
point the number of places equal to the value of the exponent. Shift
right if the exponent is positive, or left if the exponent is negative.)
5. From left to right, use weighted positional notation to form the decimal
sum of the powers of 2 represented by the floating-point binary
number.
 Example

Convert 0 10000010 1011000000000000000000 to Decimal

1. The number is positive.
2. The unbiased exponent is binary 00000011, or decimal 3.
3 Combining the sign,
3. sign exponent,
exponent and significand,
significand the binary
number is +1.01011 X 23.
4. The unnormalized binary number is +1010.11.
5. The decimal value is +10 3/4, or +10.75.
 Outline

„ Floating-Point Binary Representation

„ Floating-Point Unit
 Floating Point Unit
„ FPU Register Stack
„ Rounding
„ Floating-Point Exceptions
„ Floating-Point Instruction Set
„ Arithmetic Instructions
„ Comparing Floating-Point Values
„ Reading and Writing Floating-Point Values
„ Exception Synchronization
„ Mixed-Mode Arithmetic
„ Masking and Unmasking Exceptions
 FPU Register Stack
„ 8 individually addressable 80-bit data registers
„ Register stack: R0~R7
„ Three-bit field named TOP in the FPU status word identifies
the register number that is currently the top of stack.
 Special-Purpose Registers
• Opcode register: stores opcode of last
noncontrol instruction executed
• Control register: controls precision and
rounding method for calculations
• Status register: top-of-stack pointer,
condition
diti codes,
d exception
ti warnings
i
• Tag register: indicates content type of
each register in the register stack
• Last instruction pointer register: pointer to
last non-control executed instruction
• Last data (operand) pointer register:
points to data operand used by last
executed instruction
 Rounding
„ FPU attempts to round an infinitely accurate result
from a floating-point calculation
¾ may be impossible because of storage limitations
„ Example
¾ Store +1.0111
St 1 0111 in
i 3 fractional
f ti l bits
bit
¾ rounding up by adding .0001 produces 1.100
¾ rounding down by subtracting .0001 produces 1.011
„ Round to nearest even
„ Round down toward – ∞
„ Round up toward ∞
„ Round toward zero
 Round-to-Nearest (Even)

rtnei(x) rtni(x)
4 4

3 3

2 2

1 1
x x
–4 –3 –2 –1 1 2 3 4 –4 –3 –2 –1 1 2 3 4

–1 –1

–2 –2

–3 –3

–4 –4

(a) Round to nearest even integer (b) Round to nearest integer

 Directed Rounding
ritni(x) rutni(x)
4 4

3 3

2 2

1 1
x x
–4 –3 –2 –1 1 2 3 4 –4 –3 –2 –1 1 2 3 4

–1 –1

–2 –2

–3 –3

–4 –4

(a) Round inward to nearest integer (b) Round upward to nearest integer
 Floating-Point Exceptions
„ Six types of exception conditions
¾ Invalid operation
¾ Divide by zero
¾ Denormalized operand
¾ Numeric overflow (or underflow)
¾ Inexact precision
„ Each has a corresponding mask bit
¾ if set when an exception occurs, the exception is handled
automatically by FPU
¾ if clear when an exception occurs, a software exception handler is
invoked
 FPU Instruction Set
„ Instruction mnemonics begin with letter F
„ Second letter identifies data type of memory
operand
¾ B = bcd
¾ I = integer
i t
¾ no letter: floating point
„ Examples
¾ FBLD load binary coded decimal
¾ FISTP store integer and pop stack
¾ FMUL multiply floating-point operands
 FPU Instruction Set
„ Operands
¾ zero, one, or two
¾ no immediate operands
¾ no general-purpose registers (EAX, EBX, ...)
¾ integers must be loaded from memory onto the stack
and converted to floating-point before being used in
calculations
¾ if an instruction has two operands, one must be a FPU
register
 FP Instruction Set
„ Data Types
 Load Floating-Point Value
„ FLD
¾ Copies floating point operand from memory into the top

of the FPU stack, ST(0)

„ Example

„ Loading constants: FLD1 (1), FLDZ (0), FLDL2T (log210),

FLDPI, FLDLG2 (log102), FLDLN2 (loge2)
 Store Floating-Point Value
„ FST
¾ Copies floating point operand from the top of the FPU
stack into memory

„ FSTP
¾ pops the stack after copying
 Arithmetic Instructions
„ Same operand types as FLD and FST
 Floating-Point Add
„ FADD
¾ Adds source to destination
¾ No-operand version pops the FPU stack after
adding (ST(1) = ST(0)+ST(1); pop ST(0))
„ Examples:

fadd=faddp st(1), st(0)

 Floating-Point Subtract
„ FSUB
¾ subtracts source from
destination.
¾ No-operand version pops the FPU
stack after subtracting
g
„ Example:
 Floating-Point Multiply
„ FMUL
¾ Multiplies source by
destination, stores product in
destination

„ FDIV
¾ Divides destination by source,
then pops the stack

The no-operand versions of FMUL and FDIV pop

the stack after multiplying or dividing.
 Comparing FP Values
„ FCOM instruction
„ Operands:

„ Condition codes set by FPU

¾ Codes similar to CPU flags
 Branching after FCOM
„ Required steps:
1. Use the FNSTSW instruction to move the FPU status
word into AX.
2. Use the SAHF instruction to copy AH into the EFLAGS
register.
3. Use JA, JB, etc to do the branching.
Fortunately, the FCOMI instruction does steps
1 and 2 for you.
fcomi ST(0), ST(1)
jnb Label1
 Comparing for Equality
„ Calculate the absolute value of the difference
between two floating-point values
.data
epsilon REAL8 1.0E-12 ; difference value
val2 REAL8 0.0 ; value to compare
val3 REAL8 1.001E-13
1.001E 13 ; considered equal to val2

.code
; if( val2 == val3 ), display "Values are equal".
fld epsilon
fld val2
fsub val3
fabs
fcomi ST(0),ST(1)
ja skip
mWrite <"Values are equal",0dh,0ah>
skip:
 Exception Synchronization
„ Main CPU and FPU can execute instructions concurrently
¾ if an unmasked exception occurs, the current FPU instruction is
interrupted and the FPU signals an exception
¾ But the main CPU does not check for pending FPU exceptions. It
might use a memory value that the interrupted FPU instruction was
supposed
pp to set.
¾ Example:

.data
intVal DWORD 25
.code
fild intVal ; load integer into ST(0)
inc intVal ; increment the integer
 Exception Synchronization
„ (continued)
„ For safety, insert a fwait instruction, which tells the CPU to
wait for the FPU's exception handler to finish:

.data
intVal DWORD 25
.code
code
fild intVal ; load integer into ST(0)
fwait ; wait for pending exceptions
inc intVal ; increment the integer
FPU Code Example

expression: valD = –valA + (valB * valC).

.data
valA REAL8 1.5
valB REAL8 2.5
valC REAL8 3.0
valD REAL8 ? ; will be +6.0

.code
fld valA ; ST(0) = valA
fchs ; change sign of ST(0)
fld valB ; load valB into ST(0)
fmul valC ; ST(0) *= valC
fadd ; ST(0) += ST(1)
fstp valD ; store ST(0) to valD
 Mixed-Mode Arithmetic
„ Combining integers and reals.
¾ Integer arithmetic instructions such as ADD and MUL cannot handle
reals
¾ FPU has instructions that promote integers to reals and load the
values onto the floating point stack.
„ Example:
.data
data
N SDWORD 20
X REAL8 3.5
Z REAL8 ?
Y SDWORD ?
.code
fild N ; load integer into ST(0)
fadd X ; add mem to ST(0)
fist Y ; store ST(0) to mem int Y = N + X
fstp Z ; store ST(0) to mem real8 Z = N + X
 Changing the Rounding Mode
„ The RC field (bits 11 and 10) of the FPU Control Word
determines how the FPU will round results:
¾ 00 = Round to nearest, or to even if equidistant (initialized state)
01 = Round down (toward -infinity)
10 = Round up (toward +infinity)
11 = Truncate ((toward 0))
.data
N SDWORD 20
X REAL8 3.5
Z REAL8 ?
ctrlWord WORD ?
.code
fstcw ctrlWord ; store control word
or ctrlWord, 110000000000b ; set RC = truncate
fldcw ctrlWord, ctrlWord ; load control word
fild N ; load integer into ST(0)
fadd X ; add mem to ST(0)
fist Y ; store ST(0) to mem int Y = 23
 Masking and Unmasking Exceptions
„ Exceptions are masked by default
¾ Divide by zero just generates infinity, without halting the
program
.data
ctrlWord WORD ?
val1 DWORD 1
val2 REAL8 0.0
.code
fild val1 ; load int into ST(0)
fdiv val2 ; ST(0) = positive infinity
fstcw ctrlWord ; get the control word
and ctrlWord,1111111111111011b ; unmask divide by zero
fldcw ctrlWord ; load it back into FPU
fild val1 ; load int into ST(0)
fdiv val2 ; MS Windows will show exception
Floating-Point Addition

(±2e1s1) + (±2e1(s2 / 2e1–e2)) = ±2e1(s1 ± s2 / 2e1–e2)

(±2e2s2)
Numbers to be added:
x = 25 × 1.00101101 Operand with
y = 21 × 1.11101101 smaller exponent
to be preshifted
Operands after alignment shift:
x = 25 × 1.00101101
y = 25 × 0.000111101101
Extra bits to be
Result of addition: rounded off
s = 25 × 1.010010111101
s = 25 × 1.01001100 Rounded sum
 Inp u t 1 Inp u t 2

U np a c k
S ig ns E xp o n e n ts S ig n ific an ds

Ad d ′S u b

Hardware for Mu x Sub

P o s s ib le s w a p
Floating-Point & c o m p le m e n t

Addition A lig n
C o n tr o l s ig nific a nd s
& s ig n
lo g ic
A dd

N o rm a lize
& ro u nd
±

S ig n E xp o n e n t S ig n ific an d
P ack
O u tp ut