ST7LITE2

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

DATA EEPROM, ADC, TIMERS, SPI

■ Memories
– 8 Kbytes single voltage Flash Program mem-
ory with read-out protection, In-Circuit Pro-
gramming and In-Application programming
(ICP and IAP). 10K write/erase cycles guar-
anteed, data retention: 20 years at 55°C.
– 384 bytes RAM SO20
– 256 bytes data EEPROM with read-out pro- DIP20 300”
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C. outputs, input capture and output compare
■ Clock, Reset and Supply Management
functions
– Enhanced reset system ■ 1 Communication Interface
– Enhanced low voltage supervisor (LVD) for – SPI synchronous serial interface
main supply and an auxiliary voltage detector ■ Interrupt Management
(AVD) with interrupt capability for implement-
ing safe power-down procedures – 10 interrupt vectors plus TRAP and RESET
– Clock sources: Internal 1% RC oscillator, – 15 external interrupt lines (on 4 vectors)
crystal/ceramic resonator or external clock ■ A/D Converter
– Internal 32-MHz input clock for Auto-reload – 7 input channels
timer
– Fixed gain Op-amp
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock – 13-bit resolution for 0 to 430 mV (@ 5V VDD)
– Five Power Saving Modes: Halt, Active-Halt, – 10-bit resolution for 430 mV to 5V (@ 5V VDD)
Wait and Slow, Auto Wake Up From Halt ■ Instruction Set
■ I/O Ports – 8-bit data manipulation
– Up to 15 multifunctional bidirectional I/O lines – 63 basic instructions
– 7 high sink outputs – 17 main addressing modes
■ 4 Timers – 8 x 8 unsigned multiply instructions
– Configurable Watchdog Timer ■ Development Tools
– Two 8-bit Lite Timers with prescaler, – Full hardware/software development package
1 realtime base and 1 input capture – DM (Debug Module)
– One 12-bit Auto-reload Timer with 4 PWM
Device Summary
Features ST7LITE20 ST7LITE25 ST7LITE29
Program memory - bytes 8K
RAM (stack) - bytes 384 (128)
Data EEPROM - bytes - - 256
Lite Timer with Watchdog, Lite Timer with Watchdog,
Peripherals Autoreload Timer, SPI, Autoreload Timer with 32-MHz input clock,
10-bit ADC with Op-Amp SPI, 10-bit ADC with Op-Amp
Operating Supply 2.4V to 5.5V
Up to 8Mhz Up to 8Mhz (w/ ext OSC up to 16MHz
CPU Frequency
(w/ ext OSC up to 16MHz) and int 1MHz RC 1% PLLx8/4MHz)
Operating Temperature -40°C to +85°C
Packages SO20 300”, DIP20

Rev. 2.0
August 2003 1/131

1
 Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
131
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 114
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 123
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 129

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17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 129.

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1 INTRODUCTION
The ST7LITE2 is a member of the ST7 microcon- software developers, enabling the design of highly
troller family. All ST7 devices are based on a com- efficient and compact application code. In addition
mon industry-standard 8-bit core, featuring an en- to standard 8-bit data management, all ST7 micro-
hanced instruction set. controllers feature true bit manipulation, 8x8 un-
The ST7LITE2 features FLASH memory with signed multiplication and indirect addressing
byte-by-byte In-Circuit Programming (ICP) and In- modes.
Application Programming (IAP) capability. For easy reference, all parametric data are located
Under software control, the ST7LITE2 device can in section 13 on page 91.
be placed in WAIT, SLOW, or HALT mode, reduc- The devices feature an on-chip Debug Module
ing power consumption when the application is in (DM) to support in-circuit debugging (ICD). For a
idle or standby state. description of the DM registers, refer to the ST7
The enhanced instruction set and addressing ICC Protocol Reference Manual.
modes of the ST7 offer both power and flexibility to
Figure 1. General Block Diagram

PLL
Int. 8MHz -> 32MHz
1% RC
1MHz PLL x 8
12-Bit
or PLL X4 Auto-Reload
TIMER 2
CLKIN

/2 8-Bit
LITE TIMER 2
OSC1 Ext.
OSC2 OSC
1MHz Internal PA7:0
to CLOCK PORT A
16MHz (8 bits)
PB6:0
LVD PORT B (7 bits)
ADDRESS AND DATA BUS

ADC
VDD POWER
+ OpAmp
VSS SUPPLY

SPI
RESET CONTROL

8-BIT CORE
ALU
Debug Module

PROGRAM
MEMORY DATA EEPROM
(8K Bytes) (256 Bytes)

RAM
(384 Bytes) WATCHDOG

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2 PIN DESCRIPTION
Figure 2. 20-Pin SO Package Pinout

VSS 1 20 OSC1/CLKIN
VDD 2 19 OSC2
RESET 3 18 PA0 (HS)/LTIC
SS/AIN0/PB0 4 17 PA1 (HS)/ATIC
ei0
SCK/AIN1/PB1 5 ei3 16 PA2 (HS)/ATPWM0
MISO/AIN2/PB2 6 15 PA3 (HS)/ATPWM1
MOSI/AIN3/PB3 7 14 PA4 (HS)/ATPWM2
CLKIN/AIN4/PB4 8 ei2 13 PA5 (HS)/ATPWM3/ICCDATA
ei1
AIN5/PB5 9 12 PA6/MCO/ICCCLK/BREAK
AIN6/PB6 10 11 PA7(HS)

(HS) 20mA high sink capability

eix associated external interrupt vector

Figure 3. 20-Pin DIP Package Pinout

MISO/AIN2/PB2 1 ei3 SCK/AIN1/PB1

20
ei3
MOSI/AIN3/PB3 2 19 SS/AIN0/PB0
CLKIN/AIN4/PB4 3 18 RESET
ei2
AIN5/PB5 4 17 VDD
AIN6/PB6 5 16 VSS
PA7(HS) 6 15 OSC1/CLKIN
MCO/ICCCLK/BREAK/PA6 7 14 OSC2
ei1
ATPWM3/ICCDATA/PA5(HS) 8 13 PA0(HS)/LTIC
ATPWM2/PA4(HS) 9 ei0 12 PA1(HS)/ATIC
ATPWM1/PA3(HS) 10 ei0 11 PA2(HS)/ATPWM0

(HS) 20mA high sink capability

eix associated external interrupt vector

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PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin No. Level Port / Control
Main
Type

Input Output
Output

Pin Name Function Alternate Function

DIP20
SO20

Input

(after reset)
float

wpu

ana

OD

PP
int

1 16 VSS S Ground
2 17 VDD S Main power supply
Top priority non maskable interrupt (active
3 18 RESET I/O CT X X
low)
ADC Analog Input 0 or SPI
4 19 PB0/AIN0/SS I/O CT X X X X Port B0
Slave Select (active low)
ei3 ADC Analog Input 1 or SPI Se-
5 20 PB1/AIN1/SCK I/O CT X X X X Port B1
rial Clock
ADC Analog Input 2 or SPI
6 1 PB2/AIN2/MISO I/O CT X X X X Port B2
Master In/ Slave Out Data
ADC Analog Input 3 or SPI
7 2 PB3/AIN3/MOSI I/O CT X X X X Port B3
Master Out / Slave In Data
ei2 ADC Analog Input 4 or Exter-
8 3 PB4/AIN4/CLKIN I/O CT X X X X Port B4
nal clock input
9 4 PB5/AIN5 I/O CT X X X X Port B5 ADC Analog Input 5
10 5 PB6/AIN6 I/O CT X X X X Port B6 ADC Analog Input 6
11 6 PA7 I/O CT HS X ei1 X X Port A7
Main Clock Output or In Circuit
Communication Clock or Ex-
ternal BREAK
Caution: During reset, this pin
PA6 /MCO/ must be held at high level to
12 7 I/O CT X ei1 X X Port A6
ICCCLK/BREAK avoid entering ICC mode un-
expectedly (this is guaranteed
by the internal pull-up if the ap-
plication leaves the pin float-
ing).

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ST7LITE2

Pin No. Level Port / Control

Main

Type
Input Output

Output
Pin Name Function Alternate Function
DIP20
SO20

Input
(after reset)

float

wpu

ana

OD

PP
int
PA5 /ATPWM3/ Auto-Reload Timer PWM3 or
13 8 I/O CT HS X X X Port A5
ICCDATA ei1 In Circuit Communication Data
14 9 PA4/ATPWM2 I/O CT HS X X X Port A4 Auto-Reload Timer PWM2
15 10 PA3/ATPWM1 I/O CT HS X X X Port A3 Auto-Reload Timer PWM1
16 11 PA2/ATPWM0 I/O CT HS X X X Port A2 Auto-Reload Timer PWM0
ei0 Auto-Reload Timer Input Cap-
17 12 PA1/ATIC I/O CT HS X X X Port A1
ture
18 13 PA0/LTIC I/O CT HS X X X Port A0 Lite Timer Input Capture
19 14 OSC2 O Resonator oscillator inverter output
Resonator oscillator inverter input or Exter-
20 15 OSC1/CLKIN I
nal clock input

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 ST7LITE2

3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of ad- dressing space so the reset and interrupt vectors
dressing 64K bytes of memories and I/O registers. are located in Sector 0 (F000h-FFFFh).
The available memory locations consist of 128 The size of Flash Sector 0 and other device op-
bytes of register locations, 384 bytes of RAM, 256 tions are configurable by Option byte (refer to sec-
bytes of data EEPROM and 8 Kbytes of user pro- tion 15.1 on page 123).
gram memory. The RAM space includes up to 128
bytes for the stack from 180h to 1FFh.
IMPORTANT: Memory locations marked as “Re-
The highest address bytes contain the user reset served” must never be accessed. Accessing a re-
and interrupt vectors. seved area can have unpredictable effects on the
The Flash memory contains two sectors (see Fig- device.l
ure 4) mapped in the upper part of the ST7 ad-
Figure 4. Memory Map

0080h
Short Addressing
RAM (zero page)
0000h 00FFh
HW Registers 0100h
(see Table 2) 16-bit Addressing
007Fh RAM
0080h
RAM 017Fh
0180h
(384 Bytes)
01FFh 128 Bytes Stack
0200h
Reserved 01FFh
0FFFh
1000h
Data EEPROM 1000h
RCCR0
(256 Bytes)
10FFh
1100h RCCR1
1001h

Reserved 8K FLASH see section 7.1 on page 23

PROGRAM MEMORY

DFFFh
E000h
E000h 7 Kbytes
Flash Memory FBFFh SECTOR 1
(8K) FC00h 1 Kbyte
SECTOR 0
FFDFh FFFFh
FFE0h FFDEh
Interrupt & Reset Vectors RCCR0
(see Table 5)
FFFFh RCCR1
FFDFh

see section 7.1 on page 23

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Table 2. Hardware Register Map

Address Block Register Label Register Name Reset Status Remarks

0000h PADR Port A Data Register FFh1) R/W

0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 40h R/W

0003h PBDR Port B Data Register FFh 1) R/W

0004h Port B PBDDR Port B Data Direction Register 00h R/W
0005h PBOR Port B Option Register 00h R/W2)

0006h
Reserved Area (2 bytes)
0007h

0008h LTCSR2 Lite Timer Control/Status Register 2 0Fh R/W

0009h LTARR Lite Timer Auto-reload Register 00h R/W
LITE
000Ah LTCNTR Lite Timer Counter Register 00h Read Only
TIMER 2
000Bh LTCSR1 Lite Timer Control/Status Register 1 0X00 0000h R/W
000Ch LTICR Lite Timer Input Capture Register xxh Read Only

000Dh ATCSR Timer Control/Status Register 0X00 0000h R/W

000Eh CNTRH Counter Register High 00h Read Only
000Fh CNTRL Counter Register Low 00h Read Only
0010h ATRH Auto-Reload Register High 00h R/W
0011h ATRL Auto-Reload Register Low 00h R/W
0012h PWMCR PWM Output Control Register 00h R/W
0013h PWM0CSR PWM 0 Control/Status Register 00h R/W
0014h PWM1CSR PWM 1 Control/Status Register 00h R/W
0015h PWM2CSR PWM 2 Control/Status Register 00h R/W
0016h AUTO- PWM3CSR PWM 3 Control/Status Register 00h R/W
0017h RELOAD DCR0H PWM 0 Duty Cycle Register High 00h R/W
0018h TIMER 2 DCR0L PWM 0 Duty Cycle Register Low 00h R/W
0019h DCR1H PWM 1 Duty Cycle Register High 00h R/W
001Ah DCR1L PWM 1 Duty Cycle Register Low 00h R/W
001Bh DCR2H PWM 2 Duty Cycle Register High 00h R/W
001Ch DCR2L PWM 2 Duty Cycle Register Low 00h R/W
001Dh DCR3H PWM 3 Duty Cycle Register High 00h R/W
001Eh DCR3L PWM 3 Duty Cycle Register Low 00h R/W
001Fh ATICRH Input Capture Register High 00h Read Only
0020h ATICRL Input Capture Register Low 00h Read Only
0021h TRANCR Transfer Control Register 01h R/W
0022h BREAKCR Break Control Register 00h R/W

0023h to
Reserved area (11 bytes)
002Dh

002Eh WDG WDGCR Watchdog Control Register 7Fh R/W

0002Fh FLASH FCSR Flash Control/Status Register 00h R/W

00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

0031h SPIDR SPI Data I/O Register xxh R/W

0032h SPI SPICR SPI Control Register 0xh R/W
0033h SPICSR SPI Control Status Register 00h R/W

0034h ADCCSR A/D Control Status Register 00h R/W

0035h ADC ADCDRH A/D Data Register High xxh Read Only
0036h ADCDRL A/D Amplifier Control/Data Low Register 0xh R/W

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Address Block Register Label Register Name Reset Status Remarks

0037h ITC EICR External Interrupt Control Register 00h R/W

0038h MCC MCCSR Main Clock Control/Status Register 00h R/W

0039h Clock and RCCR RC oscillator Control Register FFh R/W

003Ah Reset SICSR System Integrity Control/Status Register 0000 0XX0h R/W

003Bh Reserved area (1 byte)

003Ch ITC EISR External Interrupt Selection Register 0Ch R/W

003Dh to
Reserved area (12 bytes)
0048h

0049h AWUPR AWU Prescaler Register FFh R/W

AWU
004Ah AWUCSR AWU Control/Status Register 00h R/W

004Bh DMCR DM Control Register 00h R/W

004Ch DMSR DM Status Register 00h R/W
004Dh DMBK1H DM Breakpoint Register 1 High 00h R/W
DM3)
004Eh DMBK1L DM Breakpoint Register 1 Low 00h R/W
004Fh DMBK2H DM Breakpoint Register 2 High 00h R/W
0050h DMBK2L DM Breakpoint Register 2 Low 00h R/W

0051h to
Reserved area (47 bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC reference manual.

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4 FLASH PROGRAM MEMORY the device from the application board and
while the application is running.
4.3.1 In-Circuit Programming (ICP)
4.1 Introduction
ICP uses a protocol called ICC (In-Circuit Commu-
The ST7 single voltage extended Flash (XFlash) is nication) which allows an ST7 plugged on a print-
a non-volatile memory that can be electrically ed circuit board (PCB) to communicate with an ex-
erased and programmed either on a byte-by-byte ternal programming device connected via cable.
basis or up to 32 bytes in parallel. ICP is performed in three steps:
The XFlash devices can be programmed off-board Switch the ST7 to ICC mode (In-Circuit Communi-
(plugged in a programming tool) or on-board using cations). This is done by driving a specific signal
In-Circuit Programming or In-Application Program- sequence on the ICCCLK/DATA pins while the
ming. RESET pin is pulled low. When the ST7 enters
The array matrix organisation allows each sector ICC mode, it fetches a specific RESET vector
to be erased and reprogrammed without affecting which points to the ST7 System Memory contain-
other sectors. ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
4.2 Main Features – Download ICP Driver code in RAM from the
ICCDATA pin
■ ICP (In-Circuit Programming) – Execute ICP Driver code in RAM to program
■ IAP (In-Application Programming) the FLASH memory
■ ICT (In-Circuit Testing) for downloading and Depending on the ICP Driver code downloaded in
executing user application test patterns in RAM RAM, FLASH memory programming can be fully
■ Sector 0 size configurable by option byte customized (number of bytes to program, program
■ Read-out and write protection against piracy locations, or selection of the serial communication
interface for downloading).
4.3 PROGRAMMING MODES 4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
The ST7 can be programmed in three different programmed in Sector 0 by the user (in ICP
ways: mode).
– Insertion in a programming tool. In this mode, This mode is fully controlled by user software. This
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be pro- allows it to be adapted to the user application, (us-
grammed or erased. er-defined strategy for entering programming
– In-Circuit Programming. In this mode, FLASH mode, choice of communications protocol used to
sectors 0 and 1, option byte row and data fetch the data to be stored etc.)
EEPROM (if present) can be programmed or IAP mode can be used to program any memory ar-
erased without removing the device from the eas except Sector 0, which is write/erase protect-
application board.
ed to allow recovery in case errors occur during
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can the programming operation.
be programmed or erased without removing

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
ICP needs a minimum of 4 and up to 6 pins to be A schottky diode can be used to isolate the appli-
connected to the programming tool. These pins cation RESET circuit in this case. When using a
are: classical RC network with R>1K or a reset man-
– RESET: device reset agement IC with open drain output and pull-up re-
– VSS: device power supply ground sistor>1K, no additional components are needed.
– ICCCLK: ICC output serial clock pin In all cases the user must ensure that no external
– ICCDATA: ICC input serial data pin reset is generated by the application during the
– OSC1: main clock input for external source ICC session.
(not required on devices without OSC1/OSC2 3. The use of Pin 7 of the ICC connector depends
pins) on the Programming Tool architecture. This pin
– VDD: application board power supply (option- must be connected when using most ST Program-
al, see Note 3) ming Tools (it is used to monitor the application
Notes: power supply). Please refer to the Programming
1. If the ICCCLK or ICCDATA pins are only used Tool manual.
as outputs in the application, no signal isolation is 4. Pin 9 has to be connected to the OSC1 pin of
necessary. As soon as the Programming Tool is the ST7 when the clock is not available in the ap-
plugged to the board, even if an ICC session is not plication or if the selected clock option is not pro-
in progress, the ICCCLK and ICCDATA pins are grammed in the option byte. ST7 devices with mul-
not available for the application. If they are used as ti-oscillator capability need to have OSC2 ground-
inputs by the application, isolation such as a serial ed in this case.
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming 5. During reset, this pin must be held at high level
Tool documentation for recommended resistor val- to avoid entering ICC mode unexpectedly (this is
ues. guaranteed by the internal pull-up if the application
leaves the pin floating).
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
Figure 5. Typical ICC Interface
PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

OPTIONAL ICC CONNECTOR

(See Note 3) HE10 CONNECTOR TYPE

OPTIONAL APPLICATION BOARD

(See Note 4) 9 7 5 3 1

10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2

APPLICATION CL2 CL1 See Notes 1 and 5 APPLICATION

POWER SUPPLY
See Note 1 I/O
VDD

RESET

ICCCLK

ICCDATA
OSC1
OSC2

ST7

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FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection Write/erase protection is enabled through the

FMP_W bit in the option byte.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually. 4.6 Related Documentation
4.5.1 Read out Protection For details on Flash programming and ICC proto-
Read out protection, when selected, makes it im- col, refer to the ST7 Flash Programming Refer-
possible to extract the memory content from the ence Manual and to the ST7 ICC Protocol Refer-
microcontroller, thus preventing piracy. Both pro- ence Manual.
gram and data E2 memory are protected.
In flash devices, this protection is removed by re- 4.7 Register Description
programming the option. In this case, both pro- FLASH CONTROL/STATUS REGISTER (FCSR)
gram and data E2 memory are automatically Read /Write
erased and the device can be reprogrammed. Reset Value: 000 0000 (00h)
Read-out protection selection depends on the de- 1st RASS Key: 0101 0110 (56h)
vice type: 2nd RASS Key: 1010 1110 (AEh)
– In Flash devices it is enabled and removed
7 0
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option 0 0 0 0 0 OPT LAT PGM
specified in the Option List.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos- Note: This register is reserved for programming
sible to both overwrite and erase program memo- using ICP, IAP or other programming methods. It
ry. It does not apply to E2 data. Its purpose is to controls the XFlash programming and erasing op-
provide advanced security to applications and pre- erations.
vent any change being made to the memory con- When an EPB or another programming tool is
tent. used (in socket or ICP mode), the RASS keys are
Warning: Once set, Write/erase protection can sent automatically.
never be removed. A write-protected flash device
is no longer reprogrammable.

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5 DATA EEPROM

5.1 INTRODUCTION 5.2 MAIN FEATURES

The Electrically Erasable Programmable Read ■ Up to 32 Bytes programmed in the same cycle
Only Memory can be used as a non volatile back- ■ EEPROM mono-voltage (charge pump)
up for storing data. Using the EEPROM requires a
■ Chained erase and programming cycles
basic access protocol described in this chapter.
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection against piracy
Figure 6. EEPROM Block Diagram

HIGH VOLTAGE
PUMP

EECSR 0 0 0 0 0 0 E2LAT E2PGM

EEPROM
ADDRESS 4 ROW
MEMORY MATRIX
DECODER DECODER
(1 ROW = 32 x 8 BITS)

128 128

4 DATA 32 x 8 BITS
MULTIPLEXER DATA LATCHES

ADDRESS BUS DATA BUS

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DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP- When PGM bit is set by the software, all the previ-
ROM Control/Status register (EECSR). The flow- ous bytes written in the data latches (up to 32) are
chart in Figure 7 describes these different memory programmed in the EEPROM cells. The effective
access modes. high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
Read Operation (E2LAT=0) ming, the user must take care that all the bytes
The EEPROM can be read as a normal ROM loca- written between two programming sequences
tion when the E2LAT bit of the EECSR register is have the same high address: only the five Least
cleared. In a read cycle, the byte to be accessed is Significant Bits of the address can change.
put on the data bus in less than 1 CPU clock cycle. At the end of the programming cycle, the PGM and
This means that reading data from EEPROM LAT bits are cleared simultaneously.
takes the same time as reading data from Note: Care should be taken during the program-
EPROM, but this memory cannot be used to exe- ming cycle. Writing to the same memory location
cute machine code. will over-program the memory (logical AND be-
tween the two write access data result) because
Write Operation (E2LAT=1) the data latches are only cleared at the end of the
To access the write mode, the E2LAT bit has to be programming cycle and by the falling edge of the
set by software (the E2PGM bit remains cleared). E2LAT bit.
When a write access to the EEPROM area occurs, It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 7. Data EEPROM Programming Flowchart

READ MODE WRITE MODE

E2LAT=0 E2LAT=1
E2PGM=0 E2PGM=0

WRITE UP TO 32 BYTES
READ BYTES
IN EEPROM AREA
IN EEPROM AREA
(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1
E2PGM=1 (set by software)

0 1
E2LAT

CLEARED BY HARDWARE

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DATA EEPROM (Cont’d)

Figure 8. Data E2PROM Write Operation

⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address

ROW 0 00h...1Fh
DEFINITION 1 20h...3Fh
...
N Nx20h...Nx20h+1Fh

Read operation impossible Read operation possible

Byte 1 Byte 2 Byte 32 Programming cycle

PHASE 1 PHASE 2
Writing data latches Waiting E2PGM and E2LAT to fall

E2LAT bit
Set by USER application Cleared by hardware
E2PGM bit

Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem-
ory is not guaranteed.

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DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING

Wait mode If a read access occurs while E2LAT=1, then the

data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol- If a write access occurs while E2LAT=0, then the
ler or when the microcontroller enters Active-HALT data on the bus will not be latched.
mode.The DATA EEPROM will immediately enter If a programming cycle is interrupted (by software/
this mode if there is no programming in progress, RESET action), the memory data will not be guar-
otherwise the DATA EEPROM will finish the cycle anteed.
and then enter WAIT mode.
5.6 Data EEPROM Read-out Protection
Active-Halt mode The read-out protection is enabled through an op-
Refer to Wait mode. tion bit (see section 15.1 on page 123).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
Halt mode against read-out piracy (including a re-write pro-
The DATA EEPROM immediately enters HALT tection). In Flash devices, when this protection is
mode if the microcontroller executes the HALT in- removed by reprogramming the Option Byte, the
struction. Therefore the EEPROM will stop the entire Program memeory and EEPROM is first au-
function in progress, and data may be corrupted. tomatically erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.

Figure 9. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE

WRITE OF
DATA LATCHES
tPROG

LAT

PGM

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DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EEC-

SR)
Read /Write
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 E2LAT E2PGM

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress

Note: if the E2PGM bit is cleared during the pro-

gramming cycle, the memory data is not guaran-
teed
Table 3. DATA EEPROM Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

EECSR E2LAT E2PGM

0030h
Reset Value 0 0 0 0 0 0 0 0

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6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION Accumulator (A)

This CPU has a full 8-bit architecture and contains The Accumulator is an 8-bit general purpose reg-
six internal registers allowing efficient 8-bit data ister used to hold operands and the results of the
manipulation. arithmetic and logic calculations and to manipulate
data.
6.2 MAIN FEATURES Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
■ 63 basic instructions are used to create either effective addresses or
■ Fast 8-bit by 8-bit multiply temporary storage areas for data manipulation.
■ 17 main addressing modes (The Cross-Assembler generates a precede in-
■ Two 8-bit index registers struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
■ Low power modes matic procedures (not pushed to and popped from
■ Maskable hardware interrupts the stack).
■ Non-maskable software interrupt Program Counter (PC)
The program counter is a 16-bit register containing
6.3 CPU REGISTERS the address of the next instruction to be executed
The 6 CPU registers shown in Figure 10 are not by the CPU. It is made of two 8-bit registers PCL
present in the memory mapping and are accessed (Program Counter Low which is the LSB) and PCH
by specific instructions. (Program Counter High which is the MSB).

Figure 10. CPU Registers

7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 1 H I N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

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CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC) because the I bit is set by hardware at the start of
Read/Write the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
Reset Value: 111x1xxx in the interrupt routine, pending interrupts are
7 0 serviced regardless of the priority level of the cur-
rent interrupt routine.
1 1 1 H I N Z C

Bit 2 = N Negative.
The 8-bit Condition Code register contains the in- This bit is set and cleared by hardware. It is repre-
terrupt mask and four flags representative of the sentative of the result sign of the last arithmetic,
result of the instruction just executed. This register logical or data manipulation. It is a copy of the 7th
can also be handled by the PUSH and POP in- bit of the result.
structions. 0: The result of the last operation is positive or null.
These bits can be individually tested and/or con- 1: The result of the last operation is negative
trolled by specific instructions. (i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
Bit 4 = H Half carry. tions.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or Bit 1 = Z Zero.
ADC instruction. It is reset by hardware during the
same instructions. This bit is set and cleared by hardware. This bit in-
0: No half carry has occurred. dicates that the result of the last arithmetic, logical
1: A half carry has occurred. or data manipulation is zero.
0: The result of the last operation is different from
This bit is tested using the JRH or JRNH instruc- zero.
tion. The H bit is useful in BCD arithmetic subrou- 1: The result of the last operation is zero.
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
Bit 0 = C Carry/borrow.
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by This bit is set and cleared by hardware and soft-
software. ware. It indicates an overflow or an underflow has
0: Interrupts are enabled. occurred during the last arithmetic operation.
1: Interrupts are disabled. 0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in- This bit is driven by the SCF and RCF instructions
structions. and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
Note: Interrupts requested while I is set are rotate instructions.
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable

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CPU REGISTERS (Cont’d)

STACK POINTER (SP) Note: When the lower limit is exceeded, the Stack
Read/Write Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
Reset Value: 01FFh stored information is then overwritten and there-
15 8 fore lost. The stack also wraps in case of an under-
flow.
0 0 0 0 0 0 0 1 The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
7 0 an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
1 SP6 SP5 SP4 SP3 SP2 SP1 SP0
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
The Stack Pointer is a 16-bit register which is al- – When an interrupt is received, the SP is decre-
ways pointing to the next free location in the stack. mented and the context is pushed on the stack.
It is then decremented after data has been pushed – On return from interrupt, the SP is incremented
onto the stack and incremented before data is and the context is popped from the stack.
popped from the stack (see Figure 11).
A subroutine call occupies two locations and an in-
Since the stack is 128 bytes deep, the 9 most sig- terrupt five locations in the stack area.
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Figure 11. Stack Manipulation Example
CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP

@ 0180h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0180h

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7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for
securing the application in critical situations (for
ST7LITE29 ST7LITE25
example in case of a power brown-out), and re- RCCR Conditions
ducing the number of external components. Address Address
VDD=5V
Main features 1000h
RCCR0 TA=25°C FFDEh
and FFDEh
■ Clock Management fRC=1MHz
– 1 MHz internal RC oscillator (enabled by op- VDD=3V
1001h
tion byte, available on ST7LITE25 and RCCR1 TA=25°C FFDFh
and FFDFh
ST7LITE29 devices only) fRC=700KHz

– 1 to 16 MHz or 32kHz External crystal/ceramic Note:

resonator (selected by option byte)
– See “ELECTRICAL CHARACTERISTICS” on
– External Clock Input (enabled by option byte) page 91. for more information on the frequency
– PLL for multiplying the frequency by 8 or 4 and accuracy of the RC oscillator.
(enabled by option byte) – To improve clock stability, it is recommended to
– For clock ART counter only: PLL32 for multi- place a decoupling capacitor between the V DD
plying the 8 MHz frequency by 4 (enabled by and VSS pins.
option byte). The 8 MHz input frequency is – These two bytes are systematically programmed
mandatory and can be obtained in the follow- by ST, including on FASTROM devices. Conse-
ing ways: quently, customers intending to use FASTROM
–1 MHz RC + PLLx8 service must not use these two bytes.
–16 MHz external clock (internally divided – RCCR0 and RCCR1 calibration values will be
by 2) erased if the read-out protection bit is reset after
–2 MHz. external clock (internally divided by it has been set. See “Read out Protection” on
2) + PLLx8 page 14.
–Crystal oscillator with 16 MHz output fre- Caution: If the voltage or temperature conditions
quency (internally divided by 2) change in the application, the frequency may need
to be recalibrated.
■ Reset Sequence Manager (RSM) Refer to application note AN1324 for information
■ System Integrity Management (SI) on how to calibrate the RC frequency using an ex-
ternal reference signal.
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
7.2 PHASE LOCKED LOOP
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en- The PLL can be used to multiply a 1MHz frequen-
abled by option byte) cy from the RC oscillator or the external clock by 4
or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
The device contains an internal RC oscillator with – The x4 PLL is intended for operation with VDD in
an accuracy of 1% for a given device, temperature the 2.4V to 3.3V range
and voltage range (4.5V-5.5V). It must be calibrat-
ed to obtain the frequency required in the applica- – The x8 PLL is intended for operation with VDD in
tion. This is done by software writing a calibration the 3.3V to 5.5V range
value in the RCCR (RC Control Register). Refer to Section 15.1 for the option byte descrip-
Whenever the microcontroller is reset, the RCCR tion.
returns to its default value (FFh), i.e. each time the If the PLL is disabled and the RC oscillator is ena-
device is reset, the calibration value must be load- bled, then fOSC = 1MHz.
ed in the RCCR. Predefined calibration values are
stored in EEPROM for 3 and 5V VDD supply volt- If both the RC oscillator and the PLL are disabled,
ages at 25°C, as shown in the following table. fOSC is driven by the external clock.

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PHASE LOCKED LOOP (Cont’d)

Figure 12. PLL Output Frequency Timing 7.3 REGISTER DESCRIPTION
Diagram
MAIN CLOCK CONTROL/STATUS REGISTER
LOCKED bit set (MCCSR)
4/8 x Read / Write
Reset Value: 0000 0000 (00h)
input
freq.
7 0
tSTAB
0 0 0 0 0 0 MCO SMS
Output freq.

tLOCK
Bits 7:2 = Reserved, must be kept cleared.
tSTARTUP
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
t the MCO output clock.
When the PLL is started, after reset or wakeup 0: MCO clock disabled, I/O port free for general
from Halt mode or AWUFH mode, it outputs the purpose I/O.
clock after a delay of tSTARTUP. 1: MCO clock enabled.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC PLL) is reached after Bit 0 = SMS Slow Mode select
a stabilization time of tSTAB (see Figure 12 and This bit is read/write by software and cleared by
13.3.4 Internal RC Oscillator and PLL) hardware after a reset. This bit selects the input
Refer to section 7.6.4 on page 33 for a description clock fOSC or fOSC/32.
of the LOCKED bit in the SICSR register. 0: Normal mode (fCPU = fOSC
1: Slow mode (fCPU = fOSC/32)

RC CONTROL REGISTER (RCCR)

Read / Write
Reset Value: 1111 1111 (FFh)

7 0

CR70 CR60 CR50 CR40 CR30 CR20 CR10 CR0

Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-

justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.

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Figure 13. Clock Management Block Diagram

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RCCR

fCPU PLL 12-BIT

Tunable 8MHz -> 32MHz AT TIMER 2
1% RC Oscillator

OSC,PLLOFF,
RC OSC
OSCRANGE[2:0]
Option bits
PLLx4x8
CLKIN CLKIN PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz fOSC
CLKIN
/2 CLKIN/2
DIVIDER
CLKIN/2
CLKIN OSC
/OSC1 OSC /2 OSC/2
1-16 MHZ DIVIDER
OSC2 or 32kHz

OSC,PLLOFF,
OSCRANGE[2:0]
Option bits

8-BIT fLTIMER
LITE TIMER 2 COUNTER (1ms timebase @ 8 MHz fOSC)
fOSC fOSC/32
/32 DIVIDER 1
fCPU

fOSC TO CPU AND

0 PERIPHERALS

MCO SMS MCCSR

fCPU
MCO

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7.4 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by Table 4. ST7 Clock Sources
four different source types coming from the multi-
Hardware Configuration
oscillator block (1 to 16MHz or 32kHz):
■ an external source

■ 5 crystal or ceramic resonator oscillators ST7

External Clock
■ an internal high frequency RC oscillator OSC1 OSC2
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the EXTERNAL
electrical characteristics section for more details. SOURCE

External Clock Source

Crystal/Ceramic Resonators
In this external clock mode, a clock signal (square, ST7
sinus or triangle) with ~50% duty cycle has to drive OSC1 OSC2
the OSC1 pin while the OSC2 pin is tied to ground.
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
Crystal/Ceramic Oscillators
CL1 CL2
This family of oscillators has the advantage of pro- LOAD
ducing a very accurate rate on the main clock of CAPACITORS
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
Internal RC Oscillator

option byte in order to reduce consumption (refer ST7

to section 15.1 on page 123 for more details on the OSC1 OSC2
frequency ranges). In this mode of the multi-oscil-
lator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground.

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7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction The RESET vector fetch phase duration is 2 clock
The reset sequence manager includes three RE- cycles.
SET sources as shown in Figure 15: If the PLL is enabled by option byte, it outputs the
■ External RESET source pulse clock after an additional delay of tSTARTUP (see
Figure 12).
■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET Figure 14. RESET Sequence Phases

These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad- RESET
dresses FFFEh-FFFFh in the ST7 memory map. INTERNAL RESET FETCH
Active Phase
256 or 4096 CLOCK CYCLES VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
7.5.2 Asynchronous External RESET pin
■ 256 or 4096 CPU clock cycle delay (see table
The RESET pin is both an input and an open-drain
below)
output with integrated RON weak pull-up resistor.
■ RESET vector fetch This pull-up has no fixed value but varies in ac-
The 256 or 4096 CPU clock cycle delay allows the cordance with the input voltage. It can be pulled
oscillator to stabilise and ensures that recovery low by external circuitry to reset the device. See
has taken place from the Reset state. The shorter Electrical Characteristic section for more details.
or longer clock cycle delay is automatically select- A RESET signal originating from an external
ed depending on the clock source chosen by op- source must have a duration of at least th(RSTL)in in
tion byte: order to be recognized (see Figure 16). This de-
CPU clock tection is asynchronous and therefore the MCU
Clock Source can enter reset state even in HALT mode.
cycle delay
Internal RC Oscillator 256
External clock (connected to CLKIN pin) 256
External Crystal/Ceramic Oscillator
4096
(connected to OSC1/OSC2 pins)

Figure 15. Reset Block Diagram

VDD

RON

Filter INTERNAL
RESET
RESET

PULSE WATCHDOG RESET

GENERATOR LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which 7.5.4 Internal Low Voltage Detector (LVD)
plays a major role in EMS performance. In a noisy RESET
environment, it is recommended to follow the Two different RESET sequences caused by the in-
guidelines mentioned in the electrical characteris- ternal LVD circuitry can be distinguished:
tics section.
■ Power-On RESET
7.5.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
means of an external reset circuit that the reset
VDD<VIT- (falling edge) as shown in Figure 16.
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency. The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
A proper reset signal for a slow rising V DD supply
can generally be provided by an external RC net- 7.5.5 Internal Watchdog RESET
work connected to the RESET pin.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 16. RESET Sequences
VDD

VIT+(LVD)
VIT-(LVD)

LVD EXTERNAL WATCHDOG

RESET RESET RESET
RUN RUN ACTIVE
RUN ACTIVE
RUN
ACTIVE PHASE PHASE PHASE

th(RSTL)in tw(RSTL)out

EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains The voltage threshold can be configured by option
the Low voltage Detector (LVD) and Auxiliary Volt- byte to be low, medium or high.
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-(LVD), the
7.6.1 Low Voltage Detector (LVD) MCU can only be in two modes:
The Low Voltage Detector function (LVD) gener- – under full software control
ates a static reset when the VDD supply voltage is – in static safe reset
below a VIT-(LVD) reference value. This means that
it secures the power-up as well as the power-down In these conditions, secure operation is always en-
keeping the ST7 in reset. sured for the application without the need for ex-
ternal reset hardware.
The VIT-(LVD) reference value for a voltage drop is
lower than the V IT+(LVD) reference value for power- During a Low Voltage Detector Reset, the RESET
on in order to avoid a parasitic reset when the pin is held low, thus permitting the MCU to reset
MCU starts running and sinks current on the sup- other devices.
ply (hysteresis).
The LVD Reset circuitry generates a reset when Notes:
VDD is below:
The LVD allows the device to be used without any
– VIT+(LVD)when VDD is rising external RESET circuitry.
– VIT-(LVD) when VDD is falling The LVD is an optional function which can be se-
The LVD function is illustrated in Figure 17. lected by option byte.

Figure 17. Low Voltage Detector vs Reset

VDD

Vhys
VIT+(LVD)
VIT- (LVD)

RESET

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Figure 18. Reset and Supply Management Block Diagram

WATCHDOG
STATUS FLAG
TIMER (WDG)

SYSTEM INTEGRITY MANAGEMENT

RESET SEQUENCE AVD Interrupt Request
RESET MANAGER SICSR
(RSM)
0 0 0 WDGRF LOCKED LVDRF AVDF AVDIE

LOW VOLTAGE
VSS DETECTOR
VDD (LVD)

AUXILIARY VOLTAGE
DETECTOR
(AVD)

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.2 Auxiliary Voltage Detector (AVD) abled through the option byte.
The Voltage Detector function (AVD) is based on 7.6.2.1 Monitoring the VDD Main Supply
an analog comparison between a VIT-(AVD) and The AVD voltage threshold value is relative to the
VIT+(AVD) reference value and the VDD main sup- selected LVD threshold configured by option byte
ply voltage (VAVD). The VIT-(AVD) reference value (see section 15.1 on page 123).
for falling voltage is lower than the V IT+(AVD) refer-
ence value for rising voltage in order to avoid par- If the AVD interrupt is enabled, an interrupt is gen-
asitic detection (hysteresis). erated when the voltage crosses the VIT+(LVD) or
VIT-(AVD) threshold (AVDF bit is set).
The output of the AVD comparator is directly read-
able by the application software through a real In the case of a drop in voltage, the AVD interrupt
time status bit (AVDF) in the SICSR register. This acts as an early warning, allowing software to shut
bit is read only. down safely before the LVD resets the microcon-
troller. See Figure 19.
Caution: The AVD functions only if the LVD is en-
Figure 19. Using the AVD to Monitor VDD

VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)

VIT-(AVD)
VIT+(LVD)

VIT-(LVD)

AVDF bit 0 1 RESET 1 0

AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by INTERRUPT Cleared by
reset hardware
LVD RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.3 Low Power Modes set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode Description
Enable Exit Exit
No effect on SI. AVD interrupts cause the Event
WAIT Interrupt Event Control from from
device to exit from Wait mode. Flag
Bit Wait Halt
The CRSR register is frozen.
HALT AVD event AVDF AVDIE Yes No
The AVD remains active.

7.6.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read /Write Bit 2 = LVDRF LVD reset flag
Reset Value: 0000 0xx0 (0xh) This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
7 0 set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
WDG bit value is undefined.
0 0 0 LOCKED LVDRF AVDF AVDIE
RF

Bit 1 = AVDF Voltage Detector flag

Bit 7:5 = Reserved, must be kept cleared. This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
Bit 4 = WDGRF Watchdog reset flag 19 and to Section 7.6.2.1 for additional details.
This bit indicates that the last Reset was generat- 0: VDD over AVD threshold
ed by the Watchdog peripheral. It is set by hard- 1: VDD under AVD threshold
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU Bit 0 = AVDIE Voltage Detector interrupt enable
starts). This bit is set and cleared by software. It enables
Combined with the LVDRF flag information, the an interrupt to be generated when the AVDF flag is
flag description is given by the following table. set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
RESET Sources LVDRF WDGRF
rupt routine.
External RESET pin 0 0 0: AVD interrupt disabled
Watchdog 0 1 1: AVD interrupt enabled
LVD 1 X

Application notes
Bit 3 = LOCKED PLL Locked Flag The LVDRF flag is not cleared when another RE-
This bit is set and cleared by hardware. It is set au- SET type occurs (external or watchdog), the
tomatically when the PLL reaches its operating fre- LVDRF flag remains set to keep trace of the origi-
quency. nal failure.
0: PLL not locked In this case, a watchdog reset can be detected by
1: PLL locked software while an external reset can not.

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8 INTERRUPTS
The ST7 core may be interrupted by one of two dif- It will be serviced according to the flowchart on
ferent methods: maskable hardware interrupts as Figure 20.
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt 8.2 EXTERNAL INTERRUPTS
processing flowchart is shown in Figure 20.
The maskable interrupts must be enabled by External interrupt vectors can be loaded into the
clearing the I bit in order to be serviced. However, PC register if the corresponding external interrupt
disabled interrupts may be latched and processed occurred and if the I bit is cleared. These interrupts
when they are enabled (see external interrupts allow the processor to leave the Halt low power
subsection). mode.
Note: After reset, all interrupts are disabled. The external interrupt polarity is selected through
When an interrupt has to be serviced: the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution. An external interrupt triggered on edge will be
latched and the interrupt request automatically
– The PC, X, A and CC registers are saved onto cleared upon entering the interrupt service routine.
the stack.
If several input pins, connected to the same inter-
– The I bit of the CC register is set to prevent addi- rupt vector, are configured as interrupts, their sig-
tional interrupts. nals are logically NANDed before entering the
– The PC is then loaded with the interrupt vector of edge/level detection block.
the interrupt to service and the first instruction of Caution: The type of sensitivity defined in the Mis-
the interrupt service routine is fetched (refer to cellaneous or Interrupt register (if available) ap-
the Interrupt Mapping Table for vector address- plies to the ei source. In case of a NANDed source
es). (as described on the I/O ports section), a low level
The interrupt service routine should finish with the on an I/O pin configured as input with interrupt,
IRET instruction which causes the contents of the masks the interrupt request even in case of rising-
saved registers to be recovered from the stack. edge sensitivity.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will 8.3 PERIPHERAL INTERRUPTS
resume.
Different peripheral interrupt flags in the status
Priority Management register are able to cause an interrupt when they
By default, a servicing interrupt cannot be inter- are active if both:
rupted because the I bit is set by hardware enter- – The I bit of the CC register is cleared.
ing in interrupt routine.
– The corresponding enable bit is set in the control
In the case when several interrupts are simultane- register.
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map- If any of these two conditions is false, the interrupt
ping Table). is latched and thus remains pending.
Interrupts and Low Power Mode Clearing an interrupt request is done by:
All interrupts allow the processor to leave the – Writing “0” to the corresponding bit in the status
WAIT low power mode. Only external and specifi- register or
cally mentioned interrupts allow the processor to – Access to the status register while the flag is set
leave the HALT low power mode (refer to the “Exit followed by a read or write of an associated reg-
from HALT“ column in the Interrupt Mapping Ta- ister.
ble). Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
8.1 NON MASKABLE SOFTWARE INTERRUPT abled) will therefore be lost if the clear sequence is
executed.
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.

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INTERRUPTS (Cont’d)
Figure 20. Interrupt Processing Flowchart

FROM RESET

N
I BIT SET?

Y N INTERRUPT
PENDING?

FETCH NEXT INSTRUCTION Y

N
IRET?
STACK PC, X, A, CC
SET I BIT
Y LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 5. Interrupt Mapping

Exit Exit
Source Register Priority from from Address
N° Description
Block Label Order HALT or ACTIVE Vector
AWUFH -HALT
RESET Reset yes yes FFFEh-FFFFh
N/A Highest
TRAP Software Interrupt Priority no FFFCh-FFFDh
0 AWU Auto Wake Up Interrupt AWUCSR yes1) FFFAh-FFFBh
1 ei0 External Interrupt 0 FFF8h-FFF9h
2 ei1 External Interrupt 1 N/A no FFF6h-FFF7h
yes
3 ei2 External Interrupt 2 FFF4h-FFF5h
4 ei3 External Interrupt 3 FFF2h-FFF3h
5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SI AVD interrupt SICSR FFECh-FFEDh
AT TIMER Output Compare Interrupt PWMxCSR no
8 FFEAh-FFEBh
AT TIMER or Input Capture Interrupt or ATCSR
no
9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h
10 LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h
LITE TIMER
11 LITE TIMER RTC1 Interrupt LTCSR yes FFE4h-FFE5h
12 SPI SPI Peripheral Interrupts SPICSR Lowest yes no FFE2h-FFE3h
Priority
13 Not usedNot used FFE0h-FFE1h
Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.

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INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER EXTERNAL INTERRUPT SELECTION REGIS-
(EICR) TER (EISR)
Read /Write Read /Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 1100 (0Ch)

7 0 7 0

IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00 ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00

Bit 7:6 = IS3[1:0] ei3 sensitivity Bit 7:6 = ei3[1:0] ei3 pin selection
These bits define the interrupt sensitivity for ei3 These bits are written by software. They select the
(Port B0) according to Table 6. Port B I/O pin used for the ei3 external interrupt ac-
cording to the table below.
Bit 5:4 = IS2[1:0] ei2 sensitivity External Interrupt I/O pin selection
These bits define the interrupt sensitivity for ei2
ei31 ei30 I/O Pin
(Port B3) according to Table 6.
0 0 PB0 *
0 1 PB1
Bit 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1 1 0 PB2
(Port A7) according to Table 6.
* Reset State
Bit 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0 Bit 5:4 = ei2[1:0] ei2 pin selection
(Port A0) according to Table 6. These bits are written by software. They select the
Note: These 8 bits can be written only when the I Port B I/O pin used for the ei2 external interrupt ac-
bit in the CC register is set. cording to the table below.
External Interrupt I/O pin selection

Table 6. Interrupt Sensitivity Bits ei21 ei20 I/O Pin

0 0 PB3 *
ISx1 ISx0 External Interrupt Sensitivity
0 1 PB4
0 0 Falling edge & low level 1 0 PB5
0 1 Rising edge only 1 1 PB6
1 0 Falling edge only
1 1 Rising and falling edge * Reset State
.

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INTERRUPTS (Cont’d)
Bit 3:2 = ei1[1:0] ei1 pin selection Port A I/O pin used for the ei0 external interrupt ac-
These bits are written by software. They select the cording to the table below.
Port A I/O pin used for the ei1 external interrupt ac- External Interrupt I/O pin selection
cording to the table below.
External Interrupt I/O pin selection ei01 ei00 I/O Pin
0 0 PA0 *
ei11 ei10 I/O Pin
0 1 PA1
0 0 PA4
1 0 PA2
0 1 PA5
1 1 PA3
1 0 PA6
1 1 PA7*
* Reset State

* Reset State
Bits 1:0 = Reserved.

Bit 1:0 = ei0[1:0] ei0 pin selection

These bits are written by software. They select the

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9 POWER SAVING MODES

9.1 INTRODUCTION 9.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, five main pow- – To reduce power consumption by decreasing the
er saving modes are implemented in the ST7 (see internal clock in the device,
Figure 21):
– To adapt the internal clock frequency (fCPU) to
■ Slow
the available supply voltage.
■ Wait (and Slow-Wait)
SLOW mode is controlled by the SMS bit in the
■ Active Halt
MCCSR register which enables or disables Slow
■ Auto Wake up From Halt (AWUFH) mode.
■ Halt In this mode, the oscillator frequency is divided by
After a RESET the normal operating mode is se- 32. The CPU and peripherals are clocked at this
lected by default (RUN mode). This mode drives lower frequency.
the device (CPU and embedded peripherals) by
Note: SLOW-WAIT mode is activated when enter-
means of a master clock which is based on the ing WAIT mode while the device is already in
main oscillator frequency divided or multiplied by 2 SLOW mode.
(fOSC2).
From RUN mode, the different power saving Figure 22. SLOW Mode Clock Transition
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator fOSC/32 fOSC
status. fCPU

Figure 21. Power Saving Mode Transitions

fOSC

High

RUN SMS

NORMAL RUN MODE

SLOW
REQUEST

WAIT

SLOW WAIT

ACTIVE HALT

AUTO WAKE UP FROM HALT

HALT

Low
POWER CONSUMPTION

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POWER SAVING MODES (Cont’d)

9.3 WAIT MODE Figure 23. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I BIT 0
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until N
RESET
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of Y
the interrupt or Reset service routine. N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up. Y
Refer to Figure 23. OSCILLATOR ON
PERIPHERALS OFF
CPU ON
I BIT 0

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I BIT X 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

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POWER SAVING MODES (Cont’d)

9.4 HALT MODE Figure 25. HALT Mode Flow-chart

The HALT mode is the lowest power consumption HALT INSTRUCTION
mode of the MCU. It is entered by executing the (Active Halt disabled)
‘HALT’ instruction when ACTIVE-HALT is disabled (AWUCSR.AWUEN=0)
(see section 9.5 on page 41 for more details) and
ENABLE WATCHDOG
when the AWUEN bit in the AWUCSR register is
cleared. 0 DISABLE
WDGHALT 1)
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt 1
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, OSCILLATOR OFF
WATCHDOG PERIPHERALS 2) OFF
the oscillator is immediately turned on and the 256 RESET
or 4096 CPU cycle delay is used to stabilize the CPU OFF
oscillator. After the start up delay, the CPU I BIT 0
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
N RESET
ure 25).
When entering HALT mode, the I bit in the CC reg-
N Y
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im- INTERRUPT 3)
mediately.
Y OSCILLATOR ON
In HALT mode, the main oscillator is turned off PERIPHERALS OFF
causing all internal processing to be stopped, in- CPU ON
cluding the operation of the on-chip peripherals. I BIT X 4)
All peripherals are not clocked except the ones
which get their clock supply from another clock 256 OR 4096 CPU CLOCK
generator (such as an external or auxiliary oscilla- CYCLE DELAY5)
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op- OSCILLATOR ON
PERIPHERALS ON
tion bit of the option byte. The HALT instruction
CPU ON
when executed while the Watchdog system is en-
I BIT X 4)
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 123 for more details).
FETCH RESET VECTOR
Figure 24. HALT Timing Overview OR SERVICE INTERRUPT

Notes:
256 OR 4096 CPU
RUN HALT CYCLE DELAY RUN 1. WDGHALT is an option bit. See option byte sec-
tion for more details.
RESET 2. Peripheral clocked with an external clock source
OR can still be active.
HALT INTERRUPT 3. Only some specific interrupts can exit the MCU
INSTRUCTION FETCH from HALT mode (such as external interrupt). Re-
[Active Halt disabled] VECTOR fer to Table 5 Interrupt Mapping for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when-
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of tSTARTUP (see Figure 12).

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9.4.1 Halt Mode Recommendations 9.5 ACTIVE-HALT MODE
– Make sure that an external event is available to ACTIVE-HALT mode is the lowest power con-
wake up the microcontroller from Halt mode. sumption mode of the MCU with a real time clock
– When using an external interrupt to wake up the available. It is entered by executing the ‘HALT’ in-
microcontroller, reinitialize the corresponding I/O struction. The decision to enter either in ACTIVE-
as “Input Pull-up with Interrupt” before executing HALT or HALT mode is given by the LTCSR/ATC-
the HALT instruction. The main reason for this is SR register status as shown in the following table:
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical ATCSR
LTCSR1 ATCSR ATCSR
condition. OVFIE Meaning
TB1IE bit CK1 bit CK0 bit
bit
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau- 0 x x 0 ACTIVE-HALT
tionary measure. 0 0 x x mode disabled
– The opcode for the HALT instruction is 0x8E. To 1 x x x ACTIVE-HALT
avoid an unexpected HALT instruction due to a x 1 0 1 mode enabled
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro- The MCU can exit ACTIVE-HALT mode on recep-
gram memory with the value 0x8E. tion of a specific interrupt (see Table 5, “Interrupt
– As the HALT instruction clears the interrupt mask Mapping,” on page 35) or a RESET.
in the CC register to allow interrupts, the user – When exiting ACTIVE-HALT mode by means of
may choose to clear all pending interrupt bits be- a RESET, a 256 or 4096 CPU cycle delay oc-
fore executing the HALT instruction. This avoids curs. After the start up delay, the CPU resumes
entering other peripheral interrupt routines after operation by fetching the reset vector which
executing the external interrupt routine corre- woke it up (see Figure 27).
sponding to the wake-up event (reset or external – When exiting ACTIVE-HALT mode by means of
interrupt). an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 27).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately (see Note 3).
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).

Note: As soon as ACTIVE-HALT is enabled, exe-

cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.

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Figure 26. ACTIVE-HALT Timing Overview 9.6 AUTO WAKE UP FROM HALT MODE

ACTIVE 256 OR 4096 CPU Auto Wake Up From Halt (AWUFH) mode is simi-
RUN HALT RUN lar to Halt mode with the addition of a specific in-
CYCLE DELAY 1)
ternal RC oscillator for wake-up (Auto Wake Up
from Halt Oscillator). Compared to ACTIVE-HALT
RESET
OR
mode, AWUFH has lower power consumption (the
HALT main clock is not kept running, but there is no ac-
INTERRUPT FETCH
INSTRUCTION curate realtime clock available.
[Active Halt Enabled] VECTOR
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
Figure 27. ACTIVE-HALT Mode Flow-chart been set.
OSCILLATOR ON Figure 28. AWUFH Mode Block Diagram
HALT INSTRUCTION PERIPHERALS 2) OFF
(Active Halt enabled) CPU OFF
I BIT 0
AWU RC
(AWUCSR.AWUEN=0)
oscillator
to Timer input capture
fAWU_RC
N
RESET

N Y AWUFH
INTERRUPT 3) /64 AWUFH interrupt
divider prescaler/1 .. 255
Y OSCILLATOR ON (ei0 source)
PERIPHERALS 2) OFF
CPU ON As soon as HALT mode is entered, and if the
I BIT X 4) AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
256 OR 4096 CPU CLOCK (fAWU_RC). Its frequency is divided by a fixed divid-
CYCLE DELAY er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
OSCILLATOR ON the AWUF flag is set by hardware and an interrupt
PERIPHERALS ON wakes-up the MCU from Halt mode. At the same
CPU ON time the main oscillator is immediately turned on
I BIT X 4) and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
FETCH RESET VECTOR ation by servicing the AWUFH interrupt. The AWU
OR SERVICE INTERRUPT flag and its associated interrupt are cleared by
software reading the AWUCSR register.
Notes: To compensate for any frequency dispersion of
1. This delay occurs only if the MCU exits ACTIVE- the AWU RC oscillator, it can be calibrated by
HALT mode by means of a RESET. measuring the clock frequency fAWU_RC and then
2. Peripherals clocked with an external clock calculating the right prescaler value. Measurement
source can still be active. mode is enabled by setting the AWUM bit in the
3. Only the RTC1 interrupt and some specific inter- AWUCSR register in Run mode. This connects
rupts can exit the MCU from ACTIVE-HALT mode. fAWU_RC to the input capture of the 12-bit Auto-Re-
Refer to Table 5, “Interrupt Mapping,” on page 35 load timer, allowing the fAWU_RC to be measured
for more details. using the main oscillator clock as a reference time-
4. Before servicing an interrupt, the CC register is
base.
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

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Similarities with Halt mode – In AWUFH mode, the main oscillator is turned off
The following AWUFH mode behaviour is the causing all internal processing to be stopped, in-
same as normal Halt mode: cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
– The MCU can exit AWUFH mode by means of which get their clock supply from another clock
any interrupt with exit from Halt capability or a re- generator (such as an external or auxiliary oscil-
set (see Section 9.4 HALT MODE). lator like the AWU oscillator).
– When entering AWUFH mode, the I bit in the CC – The compatibility of Watchdog operation with
register is forced to 0 to enable interrupts. There- AWUFH mode is configured by the WDGHALT
fore, if an interrupt is pending, the MCU wakes option bit in the option byte. Depending on this
up immediately. setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
Figure 29. AWUF Halt Timing Diagram
tAWU

RUN MODE HALT MODE 256 OR 4096 tCPU RUN MODE

fCPU

fAWU_RC
Clear
by software
AWUFH interrupt

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Figure 30. AWUFH Mode Flow-chart Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT INSTRUCTION
(Active-Halt disabled)
2. Peripheral clocked with an external clock source
(AWUCSR.AWUEN=1)
can still be active.
3. Only an AWUFH interrupt and some specific in-
ENABLE
terrupts can exit the MCU from HALT mode (such
WATCHDOG as external interrupt). Refer to Table 5, “Interrupt
Mapping,” on page 35 for more details.
0 DISABLE
WDGHALT 1) 4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
1 ister are set to the current software priority level of
AWU RC OSC ON the interrupt routine and recovered when the CC
WATCHDOG MAIN OSC OFF register is popped.
RESET PERIPHERALS 2) OFF 5. If the PLL is enabled by option byte, it outputs
CPU OFF the clock after an additional delay of tSTARTUP (see
I[1:0] BITS 10 Figure 12).

N
RESET

N Y
INTERRUPT 3)
AWU RC OSC OFF
Y MAIN OSC ON
PERIPHERALS OFF
CPU ON
I[1:0] BITS XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY5)

AWU RC OSC OFF

MAIN OSC ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

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9.6.0.1 Register Description
7 0
AWUFH CONTROL/STATUS REGISTER
(AWUCSR) AWU AWU AWU AWU AWU AWU AWU AWU
Read /Write PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Reset Value: 0000 0000 (00h)
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
7 0 These 8 bits define the AWUPR Dividing factor (as
explained below:
AWU AWU AWU
0 0 0 0 0 AWUPR[7:0] Dividing factor
F M EN
00h Forbidden
Bits 7:3 = Reserved. 01h 1
... ...
Bit 1= AWUF Auto Wake Up Flag FEh 254
This bit is set by hardware when the AWU module FFh 255
generates an interrupt and cleared by software on
reading AWUCSR. Writing to this bit does not In AWU mode, the period that the MCU stays in
change its value. Halt Mode (tAWU in Figure 29 on page 43) is de-
0: No AWU interrupt occurred fined by
1: AWU interrupt occurred
1
t = 64 × AWUPR × -------------------------- + t
AWU f RCSTRT
AWURC
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con- This prescaler register can be programmed to
nects its output to the inputcapture of the 12-bit modify the time that the MCU stays in Halt mode
Auto-Reload timer. This allows the timer to be before waking up automatically.
used to measure the AWU RC oscillator disper-
Note: If 00h is written to AWUPR, depending on
sion and then compensate this dispersion by pro-
the product, an interrupt is generated immediately
viding the right value in the AWUPRE register.
after a HALT instruction, or the AWUPR remains
0: Measurement disabled
inchanged.
1: Measurement enabled

Bit 0 = AWUEN Auto Wake Up From Halt Enabled

This bit enables the Auto Wake Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
pendent on the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
AWUFH PRESCALER REGISTER (AWUPR)
Read /Write
Table 7. AWU Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
Reset Value 1 1 1 1 1 1 1 1
AWUCSR
004Ah 0 0 0 0 0 AWUF AWUM AWUEN
Reset Value

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10 I/O PORTS

10.1 INTRODUCTION If several I/O interrupt pins on the same interrupt

vector are selected simultaneously, they are logi-
The I/O ports allow data transfer. An I/O port can cally combined. For this reason if one of the inter-
contain up to 8 pins. Each pin can be programmed rupt pins is tied low, it may mask the others.
independently either as a digital input or digital
output. In addition, specific pins may have several External interrupts are hardware interrupts. Fetch-
other functions. These functions can include exter- ing the corresponding interrupt vector automatical-
nal interrupt, alternate signal input/output for on- ly clears the request latch. Modifying the sensitivity
chip peripherals or analog input. bits will clear any pending interrupts.
10.2.2 Output Modes
10.2 FUNCTIONAL DESCRIPTION Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
A Data Register (DR) and a Data Direction Regis- through the latch. Reading the DR bits returns the
ter (DDR) are always associated with each port. previously stored value.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The If an OR bit is available, different output modes
following description takes into account the OR can be selected by software: push-pull or open-
register. Refer to the Port Configuration table for drain. Refer to I/O Port Implementation section for
device specific information. configuration.
An I/O pin is programmed using the corresponding DR Value and Output Pin Status
bits in the DDR, DR and OR registers: bit x corre-
DR Push-Pull Open-Drain
sponding to pin x of the port.
0 VOL VOL
Figure 31 shows the generic I/O block diagram.
1 VOH Floating
10.2.1 Input Modes
Clearing the DDRx bit selects input mode. In this 10.2.3 Alternate Functions
mode, reading its DR bit returns the digital value Many ST7s I/Os have one or more alternate func-
from that I/O pin. tions. These may include output signals from, or
If an OR bit is available, different input modes can input signals to, on-chip peripherals. The Device
be configured by software: floating or pull-up. Re- Pin Description table describes which peripheral
fer to I/O Port Implementation section for configu- signals can be input/output to which ports.
ration. A signal coming from an on-chip peripheral can be
Notes: output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
1. Writing to the DR modifies the latch value but al’s control register). The peripheral configures the
does not change the state of the input pin.
2. Do not use read/modify/write instructions I/O as an output and takes priority over standard I/
(BSET/BRES) to modify the DR register. O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
External Interrupt Function
Depending on the device, setting the ORx bit while Configuring an I/O as floating enables alternate
in input mode can configure an I/O as an input with function input. It is not recommended to configure
interrupt. In this configuration, a signal edge or lev- an I/O as pull-up as this will increase current con-
el input on the I/O generates an interrupt request sumption. Before using an I/O as an alternate in-
via the corresponding interrupt vector (eix). put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter- Configure an I/O as input floating for an on-chip
nal Interrupt Control Register (EICR) or the Miscel- peripheral signal which can be input and output.
laneous Register controls this sensitivity, depend- Caution:
ing on the device. I/Os which can be configured as both an analog
A device may have up to 7 external interrupts. and digital alternate function need special atten-
tion. The user must control the peripherals so that
Several pins may be tied to one external interrupt the signals do not arrive at the same time on the
vector. Refer to Pin Description to see which ports same pin. If an external clock is used, only the
have external interrupts. clock alternate function should be employed on
that I/O pin and not the other alternate function.

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I/O PORTS (Cont’d)

Figure 31. I/O Port General Block Diagram

ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS From on-chip peripheral (see table below)
0
ALTERNATE
PULL-UP
ENABLE
(see table below)
BIT
DR VDD

DDR
PULL-UP
PAD
CONDITION
DATA BUS

OR
If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL Combinational To on-chip peripheral
INTERRUPT Logic FROM
REQUEST (eix) OTHER
SENSITIVITY BITS Note: Refer to the Port Configuration
SELECTION table for device specific information.

Table 8. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend: NI - not implemented Note: The diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VOL is implemented to protect the de-
vice against positive stress.

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I/O PORTS (Cont’d)

Table 9. I/O Configurations
Hardware Configuration

DR REGISTER ACCESS
VDD NOTE 3

RPU PULL-UP
CONDITION DR W
REGISTER DATA BUS
PAD R
INPUT 1)

ALTERNATE INPUT
FROM To on-chip peripheral
OTHER
PINS EXTERNAL INTERRUPT
SOURCE (eix)

INTERRUPT COMBINATIONAL POLARITY

CONDITION LOGIC SELECTION

ANALOG INPUT

VDD NOTE 3
OPEN-DRAIN OUTPUT 2)

DR REGISTER ACCESS

RPU

PAD DR R/W
REGISTER DATA BUS

NOTE 3 DR REGISTER ACCESS

VDD
PUSH-PULL OUTPUT 2)

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT
BIT From on-chip periphera l

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
3. For true open drain, these elements are not implemented.

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Analog alternate function Figure 32. Interrupt I/O Port State Transitions
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
01 00 10 11
ADC registers) switches the analog voltage
present on the selected pin to the common analog INPUT INPUT OUTPUT OUTPUT
rail, connected to the ADC input. floating/pull-up floating open-drain push-pull
Analog Recommendations interrupt (reset state)

Do not change the voltage level or loading on any XX = DDR, OR

I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin. 10.4 UNUSED I/O PINS
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi- Unused I/O pins must be connected to fixed volt-
mum ratings. age levels. Refer to Section 13.8.

10.3 I/O PORT IMPLEMENTATION 10.5 LOW POWER MODES

The hardware implementation on each I/O port de- Mode Description

pends on the settings in the DDR and OR registers No effect on I/O ports. External interrupts
and specific I/O port features such as ADC input or WAIT
cause the device to exit from WAIT mode.
open drain. No effect on I/O ports. External interrupts
HALT
Switching these I/O ports from one state to anoth- cause the device to exit from HALT mode.
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 32. Other transitions 10.6 INTERRUPTS
are potentially risky and should be avoided, since The external interrupt event generates an interrupt
they may present unwanted side-effects such as if the corresponding configuration is selected with
spurious interrupt generation. DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
External interrupt on
DDRx
selected external - Yes Yes
ORx
event

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I/O PORTS (Cont’d)

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

The I/O port register configurations are summa- Interrupt Ports
rised as follows. Ports where the external interrupt capability is
Standard Ports selected using the EISR register
PA7:0, PB6:0 MODE DDR OR
floating input 0 0
MODE DDR OR
pull-up interrupt input 0 1
floating input 0 0
open drain output 1 0
pull-up input 0 1
push-pull output 1 1
open drain output 1 0
push-pull output 1 1

Table 10. Port Configuration (Standard ports)

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
Port A PA7:0 floating pull-up open drain push-pull
Port B PB6:0 floating pull-up open drain push-pull

Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
Port A PA7:0 floating pull-up interrupt open drain push-pull
Port B PB6:0 floating pull-up interrupt open drain push-pull

Table 11. I/O Port Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

PADR MSB LSB

0000h
Reset Value 1 1 1 1 1 1 1 1
PADDR MSB LSB
0001h
Reset Value 0 0 0 0 0 0 0 0
PAOR MSB LSB
0002h
Reset Value 0 1 0 0 0 0 0 0
PBDR MSB LSB
0003h
Reset Value 1 1 1 1 1 1 1 1
PBDDR MSB LSB
0004h
Reset Value 0 0 0 0 0 0 0 0
PBOR MSB LSB
0005h
Reset Value 0 0 0 0 0 0 0 0

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11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction ■ Optional reset on HALT instruction
The Watchdog timer is used to detect the occur- (configurable by option byte)
rence of a software fault, usually generated by ex- ■ Hardware Watchdog selectable by option byte
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir- 11.1.3 Functional Description
cuit generates an MCU reset on expiry of a pro- The counter value stored in the CR register (bits
grammed time period, unless the program refresh- T[6:0]), is decremented every 16000 machine cy-
es the counter’s contents before the T6 bit be- cles, and the length of the timeout period can be
comes cleared. programmed by the user in 64 increments.
11.1.2 Main Features If the watchdog is activated (the WDGA bit is set)
■ Programmable free-running downcounter (64 and when the 7-bit timer (bits T[6:0]) rolls over
increments of 16000 CPU cycles) from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
■ Programmable reset
36µs.
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 33. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA T6 T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU CLOCK DIVIDER

÷16000

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WATCHDOG TIMER (Cont’d)

The application program must write in the CR reg- Notes:
ister at regular intervals during normal operation to 1. The timing variation shown in Table 12 is due to
prevent an MCU reset. This downcounter is free- the unknown status of the prescaler when writing
running: it counts down even if the watchdog is to the CR register.
disabled. The value to be stored in the CR register 2. The number of CPU clock cycles applied during
must be between FFh and C0h (see Table 12 the RESET phase (256 or 4096) must be taken
.Watchdog Timing): into account in addition to these timings.
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme- 11.1.4 Hardware Watchdog Option
diate reset If Hardware Watchdog is selected by option byte,
– The T[5:0] bits contain the number of increments the watchdog is always active and the WDGA bit in
which represents the time delay before the the CR is not used.
watchdog produces a reset. Refer to the Option Byte description in section 15
Following a reset, the watchdog is disabled. Once on page 123.
activated it cannot be disabled, except by a reset. 11.1.4.1 Using Halt Mode with the WDG
The T6 bit can be used to generate a software re- (WDGHALT option)
set (the WDGA bit is set and the T6 bit is cleared). If Halt mode with Watchdog is enabled by option
If the watchdog is activated, the HALT instruction byte (No watchdog reset on HALT instruction), it is
will generate a Reset. recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
Table 12.Watchdog Timing pected WDG reset immediately after waking up
fCPU = 8MHz
the microcontroller. Same behavior in active-halt
mode.
WDG
min max
Counter
[ms] [ms]
Code
C0h 1 2
FFh 127 128

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WATCHDOG TIMER (Cont’d)

11.1.5 Interrupts Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

None. These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
11.1.6 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7 0

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.

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WATCHDOG TIMER (Cont’d)

Table 13. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
002Eh
Reset Value 0 1 1 1 1 1 1 1

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11.2 12-BIT AUTORELOAD TIMER 2 (AT2)

11.2.1 Introduction ■ Maskable overflow interrupt
The 12-bit Autoreload Timer can be used for gen- ■ Generation of four independent PWMx signals
eral-purpose timing functions. It is based on a free- ■ Frequency 2KHz-4MHz (@ 8 MHz fCPU)
running 12-bit upcounter with an input capture reg- – Programmable duty-cycles
ister and four PWM output channels. There are 6
external pins: – Polarity control
– Programmable output modes
– Four PWM outputs
– Maskable Compare interrupt
– ATIC pin for the Input Capture function ■ Input Capture
– BREAK pin for forcing a break condition on the – 12-bit input capture register (ATICR)
PWM outputs – Triggered by rising and falling edges
11.2.2 Main Features – Maskable IC interrupt
■ 12-bit upcounter with 12-bit autoreload register
(ATR)
Figure 34. Block Diagram

ATIC 12-BIT INPUT CAPTURE REGISTER

ATICR IC INTERRUPT
REQUEST OVF INTERRUPT
ATCSR REQUEST

0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE

CMP
INTERRUPT
fLTIMER CMPF0 REQUEST
(1 ms CMPF1
CMPF2
timebase CMPF3
@ 8MHz) fCOUNTER
12-BIT UPCOUNTER
fCPU
CNTR
32 MHz
12-BIT AUTORELOAD REGISTER
ATR

OEx bit
DCR0H DCR0L
OUTPUT CONTROL
PWM GENERATION

CMPFx bit OPx bit

Preload Preload
fPWM POL- PWMx
COMP-
on OVF Event PARE ARITY
IF TRAN=1
12-BIT DUTY CYCLE VALUE (shadow)
4 PWM Channels

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.3 Functional Description contents of the corresponding DCRx register must
PWM Mode be greater than the contents of the ATR register.
This mode allows up to four Pulse Width Modulat- The polarity bits can be used to invert any of the
ed signals to be generated on the PWMx output four output signals. The inversion is synchronized
pins. The PWMx output signals can be enabled or with the counter overflow if the TRAN bit in the
disabled using the OEx bits in the PWMCR regis- TRANCR register is set (reset value). See Figure
ter. 35.
PWM Frequency and Duty Cycle Figure 35. PWM Inversion Diagram
The four PWM signals have the same frequency inverter
(fPWM) which is controlled by the counter period PWMx PWMx
and the ATR register value. PIN

fPWM = fCOUNTER / (4096 - ATR)

Following the above formula, PWMxCSR Register
– If fCOUNTER is 32 MHz, the maximum value of OPx
fPWM is 8 MHz (ATR register value = 4092), the
minimum value is 8 KHz (ATR register value = 0)
– If fCOUNTER is 4 Mhz, the maximum value of fPWM TRAN DFF
is 2 MHz (ATR register value = 4094),the mini-
TRANCR Register
mum value is 1 KHz (ATR register value = 0).
counter
Note: The maximum value of ATR is 4094 be- overflow
cause it must be lower than the DCR value which
must be 4095 in this case.
The maximum available resolution for the PWMx
At reset, the counter starts counting from 0. duty cycle is:
When a upcounter overflow occurs (OVF event), Resolution = 1 / (4096 - ATR)
the preloaded Duty cycle values are transferred to Note: To get the maximum resolution (1/4096), the
the Duty Cycle registers and the PWMx signals ATR register must be 0. With this maximum reso-
are set to a high level. When the upcounter match- lution, 0% and 100% can be obtained by changing
es the DCRx value the PWMx signals are set to a the polarity.
low level. To obtain a signal on a PWMx pin, the
Figure 36. PWM Function

4095
DUTY CYCLE
REGISTER
COUNTER

(DCRx)

AUTO-RELOAD
REGISTER
(ATR)

000
t
PWMx OUTPUT

WITH OE=1
AND OPx=0

WITH OE=1
AND OPx=1

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12-BIT AUTORELOAD TIMER (Cont’d)

Figure 37. PWM Signal from 0% to 100% Duty Cycle

fCOUNTER

ATR= FFDh

COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh

WITH MOD00=1
PWMx OUTPUT

DCRx=000h
AND OPx=0

DCRx=FFDh

DCRx=FFEh
WITH MOD00=1
PWMx OUTPUT

AND OPx=1

DCRx=000h

t
Output Compare Mode When a low level is detected on the BREAK pin,
This mode is always available. the BA bit is set and the break function is activat-
ed.
To use this function, load a 12-bit value in the
DCRxH and DCRxL registers. Software can set the BA bit to activate the break
function without using the BREAK pin.
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCRxH and DCRxL registers, When the break function is activated (BA bit =1):
the CMPF bit in the PWMxCSR register is set and – The break pattern (PWM[3:0] bits in the BREAK-
an interrupt request is generated if the CMPIE bit CR) is forced directly on the PWMx output pins
is set. (after the inverter).
Note: The output compare function is only availa- – The 12-bit PWM counter is set to its reset value.
ble for DCRx values other than 0 (reset value). – The ARR, DCRx and the corresponding shadow
registers are set to their reset values.
Break Function – The PWMCR register is reset.
When the break function is deactivated after ap-
The break function is used to perform an emergen- plying the break (BA bit goes from 1 to 0 by soft-
cy shutdown of the power converter. ware):
The break function is activated by the external – The control of PWM outputs is transferred to the
BREAK pin (active low). In order to use the port registers.
BREAK pin it must be previously enabled by soft-
ware setting the BPEN bit in the BREAKCR regis-
ter.

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Figure 38. Block Diagram of Break Function

BREAK pin (Active Low)

BREAKCR Register
BA BPEN PWM3 PWM2 PWM1 PWM0

PWM0
1

PWM1

PWM2
PWM0
PWM1 PWM3
PWM2 0

PWM3
(Inverters)
When BA is set:
PWM counter -> Reset value
Note: ARR & DCRx -> Reset value
The BREAK pin value is latched by the BA bit. PWM Mode -> Reset value

free running upcounter. An IC interrupt is generat-

11.2.3.1 Input Capture ed if the ICIE bit is set. The ICF bit is reset by read-
ing the ATICR register when the ICF bit is set. The
The 12-bit ATICR register is used to latch the val- ATICR is a read only register and always contains
ue of the 12-bit free running upcounter after a ris- the free running upcounter value which corre-
ing or falling edge is detected on the ATIC pin. sponds to the most recent input capture. Any fur-
When an input capture occurs, the ICF bit is set ther input capture is inhibited while the ICF bit is
and the ATICR register contains the value of the set.

Figure 39. Input Capture Timing Diagram

fCOUNTER

COUNTER
01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah

ATIC PIN

INTERRUPT ATICR READ INTERRUPT

ICF FLAG

ICR REGISTER xxh 04h 09h

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.4 Low Power Modes The OVF event is mapped on a separate vector
(see Interrupts chapter).
Mode Description They generate an interrupt if the enable bit is set in
The input frequency is divided the ATCSR register and the interrupt mask in the
SLOW
by 32 CC register is reset (RIM instruction).
WAIT No effect on AT timer Note 2: Only if CK0=1 and CK1=0
AT timer halted except if CK0=1,
ACTIVE-HALT
CK1=0 and OVFIE=1
HALT AT timer halted

11.2.5 Interrupts

Exit
Enable Exit Exit
Interrupt Event from
Control from from
Event1) Flag Active-
Bit Wait Halt
Halt
Overflow
OVF OVIE Yes No Yes2)
Event
IC Event ICF ICIE Yes No No
CMP Event CMPF0 CMPIE Yes No No

Note 1: The CMP and IC events are connected to

the same interrupt vector.

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.6 Register Description Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
TIMER CONTROL STATUS REGISTER by reading the TCSR register. It indicates the tran-
(ATCSR) sition of the counter from FFh to ATR value.
Read / Write 0: No counter overflow occurred
Reset Value: 0x00 0000 (x0h) 1: Counter overflow occurred
7 6 0

Bit 1 = OVFIE Overflow Interrupt Enable.

0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE
This bit is read/write by software and cleared by
hardware after a reset.
0: OVF interrupt disabled.
Bit 7 = Reserved. 1: OVF interrupt enabled.

Bit 6 = ICF Input Capture Flag. Bit 0 = CMPIE Compare Interrupt Enable.
This bit is set by hardware and cleared by software This bit is read/write by software and cleared by
by reading the ATICR register (a read access to hardware after a reset. It can be used to mask the
ATICRH or ATICRL will clear this flag). Writing to interrupt generated when the CMPF bit is set.
this bit does not change the bit value. 0: CMPF interrupt disabled.
0: No input capture 1: CMPF interrupt enabled.
1: An input capture has occurred

COUNTER REGISTER HIGH (CNTRH)

Bit 5 = ICIE IC Interrupt Enable. Read only
This bit is set and cleared by software. Reset Value: 0000 0000 (000h)
0: Input capture interrupt disabled
1: Input capture interrupt enabled 15 8

CNTR CNTR
0 0 0 0 CNTR9 CNTR8
Bits 4:3 = CK[1:0] Counter Clock Selection. 11 10
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter. The change be-
comes effective after an overflow. COUNTER REGISTER LOW (CNTRL)
Read only
Counter Clock Selection CK1 CK0 Reset Value: 0000 0000 (000h)
OFF 0 0
7 0
fLTIMER (1 ms timebase @ 8 MHz) 1) 0 1
fCPU 1 0 CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0
2)
32 MHz 1 1

Note 1: PWM mode is not available at this fre- Bits 15:12 = Reserved.
quency.
Bits 11:0 = CNTR[11:0] Counter Value.
Note 2: ATICR counter may return inaccurate re- This 12-bit register is read by software and cleared
sults when read. It is therefore not recommended by hardware after a reset. The counter is incre-
to use Input Capture mode at this frequency. mented continuously as soon as a counter clok is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations, LSB first. When a counter over-
flow occurs, the counter restarts from the value
specified in the ATR register.

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12-BIT AUTORELOAD TIMER (Cont’d)

AUTORELOAD REGISTER (ATRH) PWMx CONTROL STATUS REGISTER
Read / Write (PWMxCSR)
Reset Value: 0000 0000 (00h) Read / Write
Reset Value: 0000 0000 (00h)
15 8
7 6 0
0 0 0 0 ATR11 ATR10 ATR9 ATR8
0 0 0 0 0 0 OPx CMPFx

AUTORELOAD REGISTER (ATRL)

Read / Write Bits 7:2= Reserved, must be kept cleared.
Reset Value: 0000 0000 (00h)

7 0 Bit 1 = OPx PWMx Output Polarity.

This bit is read/write by software and cleared by
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 hardware after a reset. This bit selects the polarity
of the PWM signal.
0: The PWM signal is not inverted.
Bits 11:0 = ATR[11:0] Autoreload Register. 1: The PWM signal is inverted.
This is a 12-bit register which is written by soft-
ware. The ATR register value is automatically
loaded into the upcounter when an overflow oc- Bit 0 = CMPFx PWMx Compare Flag.
curs. The register value is used to set the PWM This bit is set by hardware and cleared by software
frequency. by reading the PWMxCSR register. It indicates
that the upcounter value matches the DCRx regis-
ter value.
0: Upcounter value does not match DCR value.
PWM OUTPUT CONTROL REGISTER 1: Upcounter value matches DCR value.
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
BREAK CONTROL REGISTER (BREAKCR)
7 0 Read/Write
Reset Value: 0000 0000 (00h)
0 OE3 0 OE2 0 OE1 0 OE0
7 0

Bits 7:0 = OE[3:0] PWMx output enable. 0 0 BA BPEN PWM3 PWM2 PWM1 PWM0
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate Bits 7:6 = Reserved. Forced by hardware to 0.
Function disabled (I/O pin free for general pur-
pose I/O)
1: PWM mode enabled Bit 5 = BA Break Active.
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active

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12-BIT AUTORELOAD TIMER (Cont’d)

Bit 4 = BPEN Break Pin Enable. INPUT CAPTURE REGISTER HIGH (ATICRH)
This bit is read/write by software and cleared by Read only
hardware after Reset. Reset Value: 0000 0000 (00h)
0: Break pin disabled
1: Break pin enabled 15 8

0 0 0 0 ICR11 ICR10 ICR9 ICR8

Bit 3:0 = PWM[3:0] Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active. INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)

7 0
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h) ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

15 8
Bits 15:12 = Reserved.
0 0 0 0 DCR11 DCR10 DCR9 DCR8 Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR register when a rising or falling edge
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
occurs on the ATIC pin. Capture will only be per-
Read / Write
formed when the ICF flag is cleared.
Reset Value: 0000 0000 (00h)

7 0 TRANSFER CONTROL REGISTER (TRANCR)

Read/Write
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 Reset Value: 0000 0001 (01h)

7 0
Bits 15:12 = Reserved.
0 0 0 0 0 0 0 TRAN
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defin-
esthe duty cycle of the corresponding PWM output
Bits 7:1 Reserved. Forced by hardware to 0.
signal (see Figure 36).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the Bit 0 = TRAN Transfer enable
PWMx output signal (see Figure 36). In Output This bit is read/write by software, cleared by hard-
Compare mode, they define the value to be com- ware after each completed transfer and set by
pared with the 12-bit upcounter value. hardware after reset.
It allows the value of the DCRx registers to be
transferred to the DCRx shadow registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.

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12-BIT AUTORELOAD TIMER (Cont’d)

Table 14. Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ATCSR ICF ICIE CK1 CK0 OVF OVFIE CMPIE

0D 0
Reset Value 0 0 0 0 0 0 0
CNTRH CNTR11 CNTR10 CNTR9 CNTR8
0E 0 0 0 0
Reset Value 0 0 0 0
CNTRL CNTR7 CNTR8 CNTR7 CNTR6 CNTR3 CNTR2 CNTR1 CNTR0
0F
Reset Value 0 0 0 0 0 0 0 0
ATRH ATR11 ATR10 ATR9 ATR8
10 0 0 0 0
Reset Value 0 0 0 0
ATRL ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
11
Reset Value 0 0 0 0 0 0 0 0
PWMCR OE3 OE2 OE1 OE0
12 0 0 0 0
Reset Value 0 0 0 0
PWM0CSR OP0 CMPF0
13 0 0 0 0 0 0
Reset Value 0 0
PWM1CSR OP1 CMPF1
14 0 0 0 0 0 0
Reset Value 0 0
PWM2CSR OP2 CMPF2
15 0 0 0 0 0 0
Reset Value 0 0
PWM3CSR OP3 CMPF3
16 0 0 0 0 0 0
Reset Value 0 0
DCR0H DCR11 DCR10 DCR9 DCR8
17 0 0 0 0
Reset Value 0 0 0 0
DCR0L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
18
Reset Value 0 0 0 0 0 0 0 0
DCR1H DCR11 DCR10 DCR9 DCR8
19 0 0 0 0
Reset Value 0 0 0 0
DCR1L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
1A
Reset Value 0 0 0 0 0 0 0 0
DCR2H DCR11 DCR10 DCR9 DCR8
1B 0 0 0 0
Reset Value 0 0 0 0
DCR2L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
1C
Reset Value 0 0 0 0 0 0 0 0
DCR3H DCR11 DCR10 DCR9 DCR8
1D 0 0 0 0
Reset Value 0 0 0 0
DCR3L DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
1E
Reset Value 0 0 0 0 0 0 0 0
ATICRH ICR11 ICR10 ICR9 ICR8
1F 0 0 0 0
Reset Value 0 0 0 0
ATICRL ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
20
Reset Value 0 0 0 0 0 0 0 0

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Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

TRANCR TRAN
21 0 0 0 0 0 0 0
Reset Value 1
BREAKCR BA BPEN PWM3 PWM2 PWM1 PWM0
22 0 0
Reset Value 0 0 0 0 0 0

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11.3 LITE TIMER 2 (LT2)

11.3.1 Introduction – One 8-bit upcounter with autoreload and pro-
grammable timebase period from 4µs to
The Lite Timer can be used for general-purpose 1.024ms in 4µs increments (@ 8 MHz fOSC)
timing functions. It is based on two free-running 8- – 2 Maskable timebase interrupts
bit upcounters, an 8-bit input capture register. ■ Input Capture
– 8-bit input capture register (LTICR)
11.3.2 Main Features – Maskable interrupt with wakeup from Halt
Mode capability
■ Realtime Clock

– One 8-bit upcounter 1 ms or 2 ms timebase

period (@ 8 MHz fOSC)
Figure 40. Lite Timer 2 Block Diagram
fOSC/32
LTTB2
LTCNTR
Interrupt request
8-bit TIMEBASE LTCSR2
COUNTER 2
0 0 0 0 0 0 TB2IE TB2F

8
LTARR
fLTIMER
8-bit AUTORELOAD To 12-bit AT TImer
REGISTER

/2 1
8-bit TIMEBASE
COUNTER 1 0 Timebase
fLTIMER
1 or 2 ms
(@ 8MHz
fOSC)
8
LTICR
8-bit
LTIC INPUT CAPTURE
REGISTER

LTCSR1

ICIE ICF TB TB1IE TB1F

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

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LITE TIMER (Cont’d)

11.3.3 Functional Description LTARR reload value. Software can write a new
11.3.3.1 Timebase Counter 1 value at anytime in the LTARR register, this value
will be automatically loaded in the counter when
The 8-bit value of Counter 1 cannot be read or the next overflow occurs.
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of fOSC/32. An When Counter 2 overflows, the TB2F bit in the
overflow event occurs when the counter rolls over LTCSR2 register is set by hardware and an inter-
from F9h to 00h. If fOSC = 8 MHz, then the time pe- rupt request is generated if the TB2IE bit is set.
riod between two counter overflow events is 1 ms. The TB2F bit is cleared by software reading the
This period can be doubled by setting the TB bit in LTCSR2 register.
the LTCSR1 register. 11.3.3.3 Input Capture
When Counter 1 overflows, the TB1F bit is set by The 8-bit input capture register is used to latch the
hardware and an interrupt request is generated if free-running upcounter (Counter 1) 1 after a rising
the TB1IE bit is set. The TB1F bit is cleared by or falling edge is detected on the ICAP1 pin. When
software reading the LTCSR1 register. an input capture occurs, the ICF bit is set and the
11.3.3.2 Timebase Counter 2 LTICR1 register contains the MSB of Counter 1.
An interrupt is generated if the ICIE bit is set. The
Counter 2 is an 8-bit autoreload upcounter. It can ICF bit is cleared by reading the LTICR register.
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of The LTICR is a read-only register and always con-
fOSC/32 starting from the value stored in the tains the data from the last input capture. Input
LTARR register. A counter overflow event occurs capture is inhibited if the ICF bit is set.
when the counter rolls over from FFh to the
Figure 41. Input Capture Timing Diagram.

4µs
(@ 8MHz fOSC)
fCPU

f OSC/32
CLEARED
BY S/W
READING
8-bit COUNTER 1 01h 02h 03h 04h 05h 06h 07h LTIC REGISTER

LTIC PIN

ICF FLAG

LTICR REGISTER xxh 04h 07h

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LITE TIMER (Cont’d)

– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo- 11.3.6 Register Description
ry. For example, avoid defining a constant in LITE TIMER CONTROL/STATUS REGISTER 2
ROM with the value 0x8E. (LTCSR2)
– As the HALT instruction clears the I bit in the CC Read / Write
register to allow interrupts, the user may choose Reset Value: 0x00 0000 (x0h)
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering 7 0
other peripheral interrupt routines after executing
the external interrupt routine corresponding to 0 0 0 0 0 0 TB2IE TB2F
the wake-up event (reset or external interrupt).

11.3.4 Low Power Modes Bits 7:2 = Reserved, must be kept cleared.

Mode Description
No effect on Lite timer Bit 1 = TB2IE Timebase 2 Interrupt enable.
SLOW (this peripheral is driven directly This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
by f OSC/32) 1: Timebase (TB2) interrupt enabled
WAIT No effect on Lite timer
ACTIVE-HALT No effect on Lite timer
HALT Lite timer stops counting Bit 0 = TB2F Timebase 2 Interrupt Flag .
This bit is set by hardware and cleared by software
11.3.5 Interrupts reading the LTCSR register. Writing to this bit has
no effect.
Exit
0: No Counter 2 overflow
Interrupt Event
Enable Exit
from
Exit 1: A Counter 2 overflow has occurred
Control from from
Event Flag Active
Bit Wait Halt
Halt
Timebase 1 LITE TIMER AUTORELOAD REGISTER
TB1F TB1IE Yes Yes No (LTARR)
Event
Read / Write
Timebase 2
Event
TB2F TB2IE Yes No No Reset Value: 0000 0000 (00h)
IC Event ICF ICIE Yes No No 7 0

Note: The TBxF and ICF interrupt events are con-

nected to separate interrupt vectors (see Inter- AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0
rupts chapter).
Bits 7:0 = AR[7:0] Counter 2 Reload Value.
They generate an interrupt if the enable bit is set in These bits register is read/write by software. The
the LTCSR1 or LTCSR2 register and the interrupt LTARR value is automatically loaded into Counter
mask in the CC register is reset (RIM instruction). 2 (LTCNTR) when an overflow occurs.

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LITE TIMER (Cont’d)

LITE TIMER COUNTER 2 (LTCNTR) Bit 5 = TB Timebase period selection.
Read only This bit is set and cleared by software.
Reset Value: 0000 0000 (00h) 0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
7 0 MHz)

CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0

Bit 4 = TB1IE Timebase Interrupt enable.
This bit is set and cleared by software.
Bits 7:0 = CNT[7:0] Counter 2 Reload Value. 0: Timebase (TB1) interrupt disabled
This register is read by software. The LTARR val- 1: Timebase (TB1) interrupt enabled
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
Bit 3 = TB1F Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
LITE TIMER CONTROL/STATUS REGISTER reading the LTCSR register. Writing to this bit has
(LTCSR1) no effect.
Read / Write 0: No counter overflow
Reset Value: 0x00 0000 (x0h) 1: A counter overflow has occurred

7 0
Bits 2:0 = Reserved
ICIE ICF TB TB1IE TB1F - - - LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Bit 7 = ICIE Interrupt Enable. Reset Value: 0000 0000 (00h)
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled 7 0
1: Input Capture (IC) interrupt enabled
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

Bit 6 = ICF Input Capture Flag.

This bit is set by hardware and cleared by software Bits 7:0 = ICR[7:0] Input Capture Value
by reading the LTICR register. Writing to this bit These bits are read by software and cleared by
does not change the bit value. hardware after a reset. If the ICF bit in the LTCSR
0: No input capture is cleared, the value of the 8-bit up-counter will be
1: An input capture has occurred captured when a rising or falling edge occurs on
Note: After an MCU reset, software must initialise the LTIC pin.
the ICF bit by reading the LTICR register

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LITE TIMER (Cont’d)

Table 15. Lite Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

LTCSR2 TB2IE TB2F

08 0 0 0 0 0 0
Reset Value 0 0
LTARR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
09
Reset Value 0 0 0 0 0 0 0 0
LTCNTR CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
0A
Reset Value 0 0 0 0 0 0 0 0
LTCSR1 ICIE ICF TB TB1IE TB1F
0B 0 0 0
Reset Value 0 x 0 0 0
LTICR ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
0C
Reset Value 0 0 0 0 0 0 0 0

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11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction 11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full- Figure 42 shows the serial peripheral interface
duplex, synchronous, serial communication with (SPI) block diagram. There are 3 registers:
external devices. An SPI system may consist of a – SPI Control Register (SPICR)
master and one or more slaves or a system in
which devices may be either masters or slaves. – SPI Control/Status Register (SPICSR)
11.4.2 Main Features – SPI Data Register (SPIDR)
■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines) The SPI is connected to external devices through
■ Master or slave operation
3 pins:
■ Six master mode frequencies (fCPU /4 max.) – MISO: Master In / Slave Out data
■ fCPU/2 max. slave mode frequency – MOSI: Master Out / Slave In data
■ SS Management by software or hardware – SCK: Serial Clock out by SPI masters and in-
■ Programmable clock polarity and phase
put by SPI slaves
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
■ Write collision, Master Mode Fault and Overrun
the SPI master communicate with slaves indi-
flags vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
Figure 42. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR Read
Interrupt
request
Read Buffer

MOSI
7 SPICSR 0
MISO 8-Bit Shift Register
SPIF WCOL OVR MODF 0 SOD SSM SSI

Write
SOD
bit 1
SS
SPI 0
SCK STATE
CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL CLOCK
GENERATOR
SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.1 Functional Description sponds by sending data to the master device via
A basic example of interconnections between a the MISO pin. This implies full duplex communica-
single master and a single slave is illustrated in tion with both data out and data in synchronized
Figure 43. with the same clock signal (which is provided by
the master device via the SCK pin).
The MOSI pins are connected together and the
MISO pins are connected together. In this way To use a single data line, the MISO and MOSI pins
data is transferred serially between master and must be connected at each node ( in this case only
slave (most significant bit first). simplex communication is possible).
The communication is always initiated by the mas- Four possible data/clock timing relationships may
ter. When the master device transmits data to a be chosen (see Figure 46) but master and slave
slave device via MOSI pin, the slave device re- must be programmed with the same timing mode.

Figure 43. Single Master/ Single Slave Application

MASTER SLAVE

MSBit LSBit MSBit LSBit

MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS SS
+5V
Not used if SS is managed
by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.2 Slave Select Management In Slave Mode:
As an alternative to using the SS pin to control the There are two cases depending on the data/clock
Slave Select signal, the application can choose to timing relationship (see Figure 44):
manage the Slave Select signal by software. This If CPHA=1 (data latched on 2nd clock edge):
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 45) – SS internal must be held low during the entire
transmission. This implies that in single slave
In software management, the external SS pin is applications the SS pin either can be tied to
free for other application uses and the internal SS VSS, or made free for standard I/O by manag-
signal level is driven by writing to the SSI bit in the ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
SPICSR register.
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
– SS internal must be held high continuously transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.4.5.3).
Figure 44. Generic SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(if CPHA=0)

Slave SS
(if CPHA=1)

Figure 45. Hardware/Software Slave Select Management

SSM bit

SSI bit 1
SS internal
SS external pin 0

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11.4.3.3 Master Mode Operation 11.4.3.5 Slave Mode Operation
In master mode, the serial clock is output on the In slave mode, the serial clock is received on the
SCK pin. The clock frequency, polarity and phase SCK pin from the master device.
are configured by software (refer to the description To operate the SPI in slave mode:
of the SPICSR register).
1. Write to the SPICSR register to perform the fol-
Note: The idle state of SCK must correspond to lowing actions:
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if – Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
CPOL=0). Figure 46).
To operate the SPI in master mode, perform the Note: The slave must have the same CPOL
following two steps in order (if the SPICSR register and CPHA settings as the master.
is not written first, the SPICR register setting may – Manage the SS pin as described in Section
11.4.3.2 and Figure 44. If CPHA=1 SS must
be not taken into account): be held low continuously. If CPHA=0 SS must
1. Write to the SPICSR register: be held low during byte transmission and
pulled up between each byte to let the slave
– Select the clock frequency by configuring the write in the shift register.
SPR[2:0] bits.
2. Write to the SPICR register to clear the MSTR
– Select the clock polarity and clock phase by bit and set the SPE bit to enable the SPI I/O
configuring the CPOL and CPHA bits. Figure
46 shows the four possible configurations. functions.
Note: The slave must have the same CPOL 11.4.3.6 Slave Mode Transmit Sequence
and CPHA settings as the master.
– Either set the SSM bit and set the SSI bit or When software writes to the SPIDR register, the
clear the SSM bit and tie the SS pin high for data byte is loaded into the 8-bit shift register and
the complete byte transmit sequence. then shifted out serially to the MISO pin most sig-
2. Write to the SPICR register: nificant bit first.
– Set the MSTR and SPE bits The transmit sequence begins when the slave de-
Note: MSTR and SPE bits remain set only if vice receives the clock signal and the most signifi-
SS is high). cant bit of the data on its MOSI pin.
The transmit sequence begins when software
When data transfer is complete:
writes a byte in the SPIDR register.
– The SPIF bit is set by hardware
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
When software writes to the SPIDR register, the
set and interrupt mask in the CCR register is
data byte is loaded into the 8-bit shift register and
cleared.
then shifted out serially to the MOSI pin most sig-
nificant bit first. Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
1. An access to the SPICSR register while the
– The SPIF bit is set by hardware SPIF bit is set.
– An interrupt request is generated if the SPIE
2. A write or a read to the SPIDR register.
bit is set and the interrupt mask in the CCR
register is cleared. Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
Clearing the SPIF bit is performed by the following
ister is read.
software sequence:
The SPIF bit can be cleared during a second
1. An access to the SPICSR register while the
transmission; however, it must be cleared before
SPIF bit is set
the second SPIF bit in order to prevent an Overrun
2. A read to the SPIDR register. condition (see Section 11.4.5.2).
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.

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11.4.4 Clock Phase and Clock Polarity Figure 46, shows an SPI transfer with the four
Four possible timing relationships may be chosen combinations of the CPHA and CPOL bits. The di-
by software, using the CPOL and CPHA bits (See agram may be interpreted as a master or slave
Figure 46). timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
Note: The idle state of SCK must correspond to master and the slave device.
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if Note: If CPOL is changed at the communication
CPOL=0). byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 46. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA =0
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.

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11.4.5 Error Flags 11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF) An overrun condition occurs, when the master de-
Master mode fault occurs when the master device vice has sent a data byte and the slave device has
has its SS pin pulled low. not cleared the SPIF bit issued from the previously
transmitted byte.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set. – The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the Device and disables the SPI periph- In this case, the receiver buffer contains the byte
eral. sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
– The MSTR bit is reset, thus forcing the Device bytes are lost.
into slave mode.
The OVR bit is cleared by reading the SPICSR
Clearing the MODF bit is done through a software register.
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set. A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
2. A write to the SPICR register. taking place with an external device. When this
Notes: To avoid any conflicts in an application happens, the transfer continues uninterrupted;
with multiple slaves, the SS pin must be pulled and the software write will be unsuccessful.
high during the MODF bit clearing sequence. The Write collisions can occur both in master and slave
SPE and MSTR bits may be restored to their orig- mode. See also Section 11.4.3.2 Slave Select
inal state during or after this clearing sequence. Management.
Hardware does not allow the user to set the SPE Note: a "read collision" will never occur since the
and MSTR bits while the MODF bit is set except in received data byte is placed in a buffer in which
the MODF bit clearing sequence. access is always synchronous with the CPU oper-
In a slave device, the MODF bit can not be set, but ation.
in a multi master configuration the Device can be in The WCOL bit in the SPICSR register is set if a
slave mode with the MODF bit set. write collision occurs.
The MODF bit indicates that there might have No SPI interrupt is generated when the WCOL bit
been a multi-master conflict and allows software to is set (the WCOL bit is a status flag only).
handle this using an interrupt routine and either
perform to a reset or return to an application de- Clearing the WCOL bit is done through a software
fault state. sequence (see Figure 47).

Figure 47. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step

RESULT
2nd Step Read SPIDR SPIF =0
WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR
1st Step
RESULT Note: Writing to the SPIDR regis-
ter instead of reading it does not
2nd Step Read SPIDR WCOL=0 reset the WCOL bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5.4 Single Master and Multimaster For more security, the slave device may respond
Configurations to the master with the received data byte. Then the
There are two types of SPI systems: master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
– Single Master System nected and the slave has not written to its SPIDR
– Multimaster System register.
Single Master System Other transmission security methods can use
ports for handshake lines or data bytes with com-
A typical single master system may be configured,
using a device as the master and four devices as mand fields.
slaves (see Figure 48). Multi-Master System
The master device selects the individual slave de- A multi-master system may also be configured by
vices by using four pins of a parallel port to control the user. Transfer of master control could be im-
the four SS pins of the slave devices. plemented using a handshake method through the
I/O ports or by an exchange of code messages
The SS pins are pulled high during reset since the
through the serial peripheral interface system.
master device ports will be forced to be inputs at
that time, thus disabling the slave devices. The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
Note: To prevent a bus conflict on the MISO line
bit in the SPICSR register.
the master allows only one active slave device
during a transmission.
Figure 48. Single Master / Multiple Slave Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
Device Device Device Device

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
Device

5V SS

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11.4.6 Low Power Modes SS pin or the SSI bit in the SPICSR register) is low
when the Device enters Halt mode. So if Slave se-
Mode Description
lection is configured as external (see Section
No effect on SPI. 11.4.3.2), make sure the master drives a low level
WAIT SPI interrupt events cause the Device to exit on the SS pin when the slave enters Halt mode.
from WAIT mode.
SPI registers are frozen.
11.4.7 Interrupts
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the Device is woken up Enable Exit Exit
Event
Interrupt Event Control from from
by an interrupt with “exit from HALT mode” Flag
Bit Wait Halt
capability. The data received is subsequently
HALT read from the SPIDR register when the soft- SPI End of Trans-
SPIF Yes Yes
ware is running (interrupt vector fetching). If fer Event
several data are received before the wake- Master Mode SPIE
MODF Yes No
up event, then an overrun error is generated. Fault Event
This error can be detected after the fetch of Overrun Error OVR Yes No
the interrupt routine that woke up the Device.
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
11.4.6.1 Using the SPI to wake-up the Device
They generate an interrupt if the corresponding
from Halt mode
Enable Control Bit is set and the interrupt mask in
In slave configuration, the SPI is able to wake-up the CC register is reset (RIM instruction).
the Device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the Device from
Halt mode only if the Slave Select signal (external

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11.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write Bit 3 = CPOL Clock Polarity.
Reset Value: 0000 xxxx (0xh) This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
7 0
CPOL bit affects both the master and slave
modes.
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
Bit 7 = SPIE Serial Peripheral Interrupt Enable. byte boundaries, the SPI must be disabled by re-
This bit is set and cleared by software. setting the SPE bit.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End Bit 2 = CPHA Clock Phase.
of Transfer event, Master Mode Fault or Over- This bit is set and cleared by software.
run error occurs (SPIF=1, MODF=1 or OVR=1 0: The first clock transition is the first data capture
in the SPICSR register) edge.
1: The second clock transition is the first capture
Bit 6 = SPE Serial Peripheral Output Enable. edge.
This bit is set and cleared by software. It is also Note: The slave must have the same CPOL and
cleared by hardware when, in master mode, SS=0 CPHA settings as the master.
(see Section 11.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex- Bits 1:0 = SPR[1:0] Serial Clock Frequency.
ternal pins. These bits are set and cleared by software. Used
0: I/O pins free for general purpose I/O with the SPR2 bit, they select the baud rate of the
1: SPI I/O pin alternate functions enabled SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is Table 16. SPI Master mode SCK Frequency
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16 SPI Master Serial Clock SPR2 SPR1 SPR0
mode SCK Frequency. fCPU/4 1 0 0
0: Divider by 2 enabled
1: Divider by 2 disabled fCPU/8 0 0 0
Note: This bit has no effect in slave mode. fCPU/16 0 0 1
fCPU/32 1 1 0
Bit 4 = MSTR Master Mode. fCPU/64 0 1 0
This bit is set and cleared by software. It is also fCPU/128 0 1 1
cleared by hardware when, in master mode, SS=0
(see Section 11.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.

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CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only) Bit 2 = SOD SPI Output Disable.
Reset Value: 0000 0000 (00h) This bit is set and cleared by software. When set, it
7 0 disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
SPIF WCOL OVR MODF - SOD SSM SSI
0: SPI output enabled (if SPE=1)
1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag Bit 1 = SSM SS Management.
(Read only). This bit is set and cleared by software. When set, it
This bit is set by hardware when a transfer has
disables the alternate function of the SPI SS pin
been completed. An interrupt is generated if
and uses the SSI bit value instead. See Section
SPIE=1 in the SPICR register. It is cleared by a 11.4.3.2 Slave Select Management.
software sequence (an access to the SPICSR
0: Hardware management (SS managed by exter-
register followed by a write or a read to the
nal pin)
SPIDR register). 1: Software management (internal SS signal con-
0: Data transfer is in progress or the flag has been
trolled by SSI bit. External SS pin free for gener-
cleared.
al-purpose I/O)
1: Data transfer between the Device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the Bit 0 = SSI SS Internal Mode.
SPIDR register are inhibited until the SPICSR reg- This bit is set and cleared by software. It acts as a
ister is read. ‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only). 1 : Slave deselected
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
DATA I/O REGISTER (SPIDR)
quence. It is cleared by a software sequence (see
Read/Write
Figure 47). Reset Value: Undefined
0: No write collision occurred
1: A write collision has been detected 7 0

Bit 5 = OVR S PI Overrun error (Read only). D7 D6 D5 D4 D3 D2 D1 D0

This bit is set by hardware when the byte currently
being received in the shift register is ready to be The SPIDR register is used to transmit and receive
transferred into the SPIDR register while SPIF = 1 data on the serial bus. In a master device, a write
(See Section 11.4.5.2). An interrupt is generated if to this register will initiate transmission/reception
SPIE = 1 in SPICSR register. The OVR bit is of another byte.
cleared by software reading the SPICSR register.
0: No overrun error Notes: During the last clock cycle the SPIF bit is
1: Overrun error detected set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
Bit 4 = MODF Mode Fault flag (Read only). actually being read.
This bit is set by hardware when the SS pin is While the SPIF bit is set, all writes to the SPIDR
pulled low in master mode (see Section 11.4.5.1 register are inhibited until the SPICSR register is
Master Mode Fault (MODF)). An SPI interrupt can read.
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac- Warning: A write to the SPIDR register places
cess to the SPICSR register while MODF=1 fol- data directly into the shift register for transmission.
lowed by a write to the SPICR register). A read to the SPIDR register returns the value lo-
0: No master mode fault detected cated in the buffer and not the content of the shift
1: A fault in master mode has been detected register (see Figure 42).
Bit 3 = Reserved, must be kept cleared.

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Table 17. SPI Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

SPIDR MSB LSB

0031h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0032h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OVR MODF SOD SSM SSI
0033h
Reset Value 0 0 0 0 0 0 0 0

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11.5 10-BIT A/D CONVERTER (ADC)

11.5.1 Introduction ■ Data register (DR) which contains the results

The on-chip Analog to Digital Converter (ADC) pe- ■ Conversion complete status flag
ripheral is a 10-bit, successive approximation con- ■ On/off bit (to reduce consumption)
verter with internal sample and hold circuitry. This
peripheral has up to 7 multiplexed analog input The block diagram is shown in Figure 49.
channels (refer to device pin out description) that 11.5.3 Functional Description
allow the peripheral to convert the analog voltage
levels from up to 7 different sources. 11.5.3.1 Analog Power Supply
The result of the conversion is stored in a 10-bit VDDA and VSSA are the high and low level refer-
Data Register. The A/D converter is controlled ence voltage pins. In some devices (refer to device
through a Control/Status Register. pin out description) they are internally connected
to the VDD and V SS pins.
11.5.2 Main Features Conversion accuracy may therefore be impacted
■ 10-bit conversion by voltage drops and noise in the event of heavily
■ Up to 7 channels with multiplexed input loaded or badly decoupled power supply lines.
■ Linear successive approximation

Figure 49. ADC Block Diagram

DIV 4
fCPU 1 fADC
DIV 2
0
0
1
SLOW
bit

EOC SPEED ADON 0 0 CH2 CH1 CH0 ADCCSR

AIN0
HOLD CONTROL

AIN1 RADC
x 1 or ANALOG TO DIGITAL
ANALOG
MUX x8 CONVERTER

AINx CADC
AMPSEL
bit

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

AMP AMP
ADCDRL 0 0 0
CAL
SLOW D1 D0
SEL

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11.5.3.2 Input Voltage Amplifier ADC Conversion mode
The input voltage can be amplified by a factor of 8 In the ADCCSR register:
by enabling the AMPSEL bit in the ADCDRL regis- Set the ADON bit to enable the A/D converter and
ter. to start the conversion. From this time on, the
When the amplifier is enabled, the input range is ADC performs a continuous conversion of the
0V to V DD/8. selected channel.
For example, if VDD = 5V, then the ADC can con-
vert voltages in the range 0V to 430mV with an When a conversion is complete:
ideal resolution of 0.6mV (equivalent to 13-bit res-
olution with reference to a V SS to VDD range). – The EOC bit is set by hardware.
For more details, refer to the Electrical character- – The result is in the ADCDR registers.
istics section. A read to the ADCDRH resets the EOC bit.
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start- To read the 10 bits, perform the following steps:
up time is required when the amplifier is selected
1. Poll EOC bit
by the AMPSEL bit.
2. Read ADCDRL
11.5.3.3 Digital A/D Conversion Result
3. Read ADCDRH. This clears EOC automati-
The conversion is monotonic, meaning that the re-
cally.
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA To read only 8 bits, perform the following steps:
(high-level voltage reference) then the conversion 1. Poll EOC bit
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication). 2. Read ADCDRH. This clears EOC automati-
cally.
If the input voltage (VAIN) is lower than VSSA (low-
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h. 11.5.4 Low Power Modes
The A/D converter is linear and the digital result of Note: The A/D converter may be disabled by re-
the conversion is stored in the ADCDRH and AD- setting the ADON bit. This feature allows reduced
CDRL registers. The accuracy of the conversion is power consumption when no conversion is need-
described in the Electrical Characteristics Section. ed and between single shot conversions.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too Mode Description
high, this will result in a loss of accuracy due to WAIT No effect on A/D Converter
leakage and sampling not being completed in the A/D Converter disabled.
alloted time.
After wakeup from Halt mode, the A/D
11.5.3.4 A/D Conversion Converter requires a stabilization time
HALT
The analog input ports must be configured as in- tSTAB (see Electrical Characteristics)
put, no pull-up, no interrupt. Refer to the «I/O before accurate conversions can be
ports» chapter. Using these pins as analog inputs
performed.
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
11.5.5 Interrupts
– Select the CS[2:0] bits to assign the analog
channel to convert. None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR) DATA REGISTER HIGH (ADCDRH)
Read /Write (Except bit 7 read only) Read Only
Reset Value: 0000 0000 (00h) Reset Value: xxxx xxxx (xxh)

7 0 7 0

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 D9 D8 D7 D6 D5 D4 D3 D2

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by soft- Bit 7:0 = D[9:2] MSB of Analog Converted Value
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Bit 6 = SPEED ADC clock selection Read /Write
This bit is set and cleared by software. It is used Reset Value: 0000 00xx (0xh)
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de- 7 0
scription.
AMP AMP-
0 0 0 SLOW D1 D0
CAL SEL
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software. Bit 7:5 = Reserved. Forced by hardware to 0.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software.
Bit 4:3 = Reserved. Must be kept cleared. 0: Calibration off
1: Calibration on. The input voltage of the amp is
set to 0V.
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert. Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
Channel Pin* CH2 CH1 CH0 together with the SPEED bit to configure the ADC
AIN0 0 0 0 clock speed as shown on the table below.
AIN1 0 0 1
fADC SLOW SPEED
AIN2 0 1 0
AIN3 0 1 1 fCPU/2 0 0
AIN4 1 0 0 fCPU 0 1
AIN5 1 0 1 fCPU/4 1 x
AIN6 1 1 0
*The number of channels is device dependent. Refer to Bit 2 = AMPSEL Amplifier Selection Bit
the device pinout description. This bit is set and cleared by software.
0: Amplifier is not selected
1: Amplifier is selected
Note: When AMPSEL=1 it is mandatory that fADC
be less than or equal to 2 MHz.

Bit 1:0 = D[1:0] LSB of Analog Converted Value

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Table 18. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCCSR EOC SPEED ADON 0 0 CH2 CH1 CH0

0034h
Reset Value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0035h
Reset Value x x x x x x x x
ADCDRL 0 0 0 AMPCAL SLOW AMPSEL D1 D0
0036h
Reset Value 0 0 0 0 0 0 x x

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12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups: – Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
Addressing Mode Example however it uses more bytes and more CPU cy-
Inherent nop cles.
Immediate ld A,#$55 – Short addressing mode is less powerful because
it can generally only access page zero (0000h -
Direct ld A,$55 00FFh range), but the instruction size is more
Indexed ld A,($55,X) compact, and faster. All memory to memory in-
Indirect ld A,([$55],X) structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
Relative jrne loop INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Bit operation bset byte,#5 The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 19. ST7 Addressing Mode Overview

Pointer Pointer
Destination/ Length
Mode Syntax Address Size
Source (Bytes)
(Hex.) (Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
1)
Relative Direct jrne loop PC-128/PC+127 +1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.

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ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent 12.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (short)
TRAP S/W Interrupt The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
Wait For Interrupt (Low Power ing space.
WFI
Mode)
Direct (long)
Halt Oscillator (Lowest Power
HALT The address is a word, thus allowing 64 Kbyte ad-
Mode)
dressing space, but requires 2 bytes after the op-
RET Sub-routine Return code.
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
12.1.4 Indexed (No Offset, Short, Long)
RIM Reset Interrupt Mask
In this mode, the operand is referenced by its
SCF Set Carry Flag memory address, which is defined by the unsigned
RCF Reset Carry Flag addition of an index register (X or Y) with an offset.
RSP Reset Stack Pointer The indirect addressing mode consists of three
sub-modes:
LD Load
Indexed (No Offset)
CLR Clear
There is no offset, (no extra byte after the opcode),
PUSH/POP Push/Pop to/from the stack
and allows 00 - FF addressing space.
INC/DEC Increment/Decrement
Indexed (Short)
TNZ Test Negative or Zero
The offset is a byte, thus requires only one byte af-
CPL, NEG 1 or 2 Complement ter the opcode and allows 00 - 1FE addressing
MUL Byte Multiplication space.
SLL, SRL, SRA, RLC, Indexed (long)
Shift and Rotate Operations
RRC The offset is a word, thus allowing 64 Kbyte ad-
SWAP Swap Nibbles dressing space and requires 2 bytes after the op-
code.
12.1.2 Immediate
Immediate instructions have two bytes, the first 12.1.5 Indirect (Short, Long)
byte contains the opcode, the second byte con- The required data byte to do the operation is found
tains the operand value.
by its memory address, located in memory (point-
Immediate Instruction Function er).
LD Load The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP Compare
Indirect (short)
BCP Bit Compare
The pointer address is a byte, the pointer size is a
AND, OR, XOR Logical Operations
byte, thus allowing 00 - FF addressing space, and
ADC, ADD, SUB, SBC Arithmetic Operations requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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ST7 ADDRESSING MODES (Cont’d)

12.1.6 Indirect Indexed (Short, Long) SWAP Swap Nibbles
This is a combination of indirect and short indexed CALL, JP Call or Jump subroutine
addressing modes. The operand is referenced by
its memory address, which is defined by the un- 12.1.7 Relative Mode (Direct, Indirect)
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point- This addressing mode is used to modify the PC
er address follows the opcode. register value by adding an 8-bit signed offset to it.
The indirect indexed addressing mode consists of Available Relative Direct/
Function
two sub-modes: Indirect Instructions
Indirect Indexed (Short) JRxx Conditional Jump
The pointer address is a byte, the pointer size is a CALLR Call Relative
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode. The relative addressing mode consists of two sub-
Indirect Indexed (Long) modes:
The pointer address is a byte, the pointer size is a Relative (Direct)
word, thus allowing 64 Kbyte addressing space, The offset follows the opcode.
and requires 1 byte after the opcode. Relative (Indirect)
Table 20. Instructions Supporting Direct, The offset is defined in memory, of which the ad-
Indexed, Indirect and Indirect Indexed dress follows the opcode.
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Addition/subtrac-
ADC, ADD, SUB, SBC
tion operations
BCP Bit Compare

Short Instructions Only Function

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC

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12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF

Using a pre-byte
The instructions are described with one to four These prebytes enable instruction in Y as well as
bytes. indirect addressing modes to be implemented.
In order to extend the number of available op- They precede the opcode of the instruction in X or
codes for an 8-bit CPU (256 opcodes), three differ- the instruction using direct addressing mode. The
ent prebyte opcodes are defined. These prebytes prebytes are:
modify the meaning of the instruction they pre- PDY 90 Replace an X based instruction using
cede. immediate, direct, indexed, or inherent
The whole instruction becomes: addressing mode by a Y one.
PC-2 End of previous instruction PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
PC-1 Prebyte mode to an instruction using the corre-
PC Opcode sponding indirect addressing mode.
It also changes an instruction using X
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the indexed addressing mode to an instruc-
tion using indirect X indexed addressing
effective address
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I = 1 I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2’s compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A=A+M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C=0 0

RET Subroutine Return

RIM Enable Interrupts I=0 0

RLC Rotate left true C C <= Dst <= C reg, M N Z C

RRC Rotate right true C C => Dst => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Subtract with Carry A=A-M-C A M N Z C

SCF Set carry flag C=1 1

SIM Disable Interrupts I=1 1

SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C

SLL Shift left Logic C <= Dst <= 0 reg, M N Z C

SRL Shift right Logic 0 => Dst => C reg, M 0 Z C

SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C

SUB Subtraction A=A-M A M N Z C

SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

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13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re- 13.1.5 Pin input voltage
ferred to V SS. The input voltage measurement on a pin of the de-
13.1.1 Minimum and Maximum values vice is described in Figure 51.
Unless otherwise specified the minimum and max-
Figure 51. Pin input voltage
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C ST7 PIN
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design VIN
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
13.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range) and V DD=3.3V (for the 3V≤VDD≤4V
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 50.
Figure 50. Pin loading conditions

ST7 PIN

CL

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13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
13.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 7.0
V
VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3
VESD(HBM) Electrostatic discharge voltage (Human Body Model)
see section 13.7.3 on page 104
VESD(MM) Electrostatic discharge voltage (Machine Model)

13.2.2 Current Characteristics

Symbol Ratings Maximum value Unit
3)
IVDD Total current into VDD power lines (source) 150
3)
IVSS Total current out of VSS ground lines (sink) 150
Output current sunk by any standard I/O and control pin 25
IIO Output current sunk by any high sink I/O pin 50
Output current source by any I/Os and control pin - 25
mA
Injected current on ISPSEL pin ±5
Injected current on RESET pin ±5
IINJ(PIN) 2) & 4)
Injected current on OSC1 and OSC2 pins ±5
Injected current on any other pin 5) ±5
ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 20

13.2.3 Thermal Characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
Maximum junction temperature (see Table 21, “THERMAL CHARACTERISTICS,” on
TJ
page 121)

Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.

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13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions: Suffix 6 Devices
TA = -40 to +85°C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
fOSC = 8 MHz. max., TA = 0 to 70°C 2.4 5.5
VDD Supply voltage fOSC = 8 MHz. max. 2.7 5.5 V
fOSC = 16 MHz. max. 3.3 5.5
VDD≥3.3V 0 16
External clock frequency on
fCLKIN VDD≥2.4V, TA = 0 to +70°C MHz
CLKIN pin 0 8
VDD≥2.7V

Figure 52. fCLKIN Maximum Operating Frequency Versus VDD Supply Voltage
FUNCTIONALITY
GUARANTEED
fCLKIN [MHz] IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
16 PARAMETRIC DATA)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA

FUNCTIONALITY
GUARANTEED 4
IN THIS AREA
1
AT TA 0 to 70°C 0 SUPPLY VOLTAGE [V]
2.0 2.4 2.7 3.3 3.5 4.0 4.5 5.0 5.5

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13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to 125°C, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
1)
High Threshold 4.00 4.25 4.50
Reset release threshold
VIT+(LVD) Med. Threshold 3.40 1) 3.60 3.80
(VDD rise)
Low Threshold 2.65 1) 2.90 3.15
V
High Threshold 3.80 4.05 4.30 1)
Reset generation threshold
VIT-(LVD) Med. Threshold 3.20 3.40 3.65 1)
(VDD fall)
Low Threshold 2.40 2.70 2.901)
Vhys LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV
VtPOR VDD rise time rate 2) 20 20000 µs/V
tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150 ns
IDD(LVD) LVD/AVD current consumption 245 µA

Note:
1. Not tested in production.
2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset.
When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 125°C, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
High Threshold 4.401) 4.70 5.00
1=>0 AVDF flag toggle threshold
VIT+(AVD) Med. Threshold 3.901) 4.10 4.30
(VDD rise)
Low Threshold 3.201) 3.40 3.60
V
High Threshold 4.30 4.60 4.901)
0=>1 AVDF flag toggle threshold
VIT-(AVD) Med. Threshold 3.70 3.90 4.101)
(VDD fall)
Low Threshold 2.90 3.20 3.401)
Vhys AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 150 mV
Voltage drop between AVD flag set
∆VIT- VDD fall 0.45 V
and LVD reset activation
Note:
1. Not tested in production.

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol Parameter Conditions Min Typ Max Unit
VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5
VDD(x4PLL) x4 PLL operating voltage 2.4 3.3 V
VDD(x8PLL) x8 PLL operating voltage 3.3 5.5
PLL
input
tSTARTUP PLL Startup time 60 clock
(fPLL)
cycles

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OPERATING CONDITIONS (Cont’d)

The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.
13.3.4.1 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5V
Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C,VDD=5V 760
fRC kHz
quency RCCR = RCCR02 ),TA=25°C,VDD=5V 1000
Accuracy of Internal RC TA=25°C,VDD=4.5 to 5.5V -1 +1 %
ACCRC oscillator with TA=-40 to +85°C,VDD=5V -5 +2 %
RCCR=RCCR02) TA=0 to +85°C,VDD=4.5 to 5.5V -21) +21) %
RC oscillator current con-
IDD(RC) TA=25°C,VDD=5V 9701) µA
sumption
tsu(RC) RC oscillator setup time TA=25°C,VDD=5V 102) µs
fPLL x8 PLL input clock 11) MHz
tLOCK PLL Lock time5) 2 ms
tSTAB PLL Stabilization time5) 4 ms
fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.14) %
ACCPLL x8 PLL Accuracy
fRC = 1MHz@TA=-40 to +85°C,VDD=5V 0.14) %
tw(JIT) PLL jitter period fRC = 1MHz 83) kHz
JITPLL PLL jitter (∆fCPU/fCPU) 13) %
IDD(PLL) PLL current consumption TA=25°C 6001) µA

Notes:
1. Data based on characterization results, not tested in production
2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ TA =25°C, VDD=5V. See “INTERNAL RC OS-
CILLATOR ADJUSTMENT” on page 23
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy.
5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.

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OPERATING CONDITIONS (Cont’d)

13.3.4.2 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V
Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.0V 560
fRC kHz
quency RCCR=RCCR12) ,TA=25°C,VDD= 3V 700
Accuracy of Internal RC TA=25°C,VDD=3V -2 +2 %
ACCRC oscillator when calibrated TA=25°C,VDD=2.7 to 3.3V -25 +25 %
with RCCR=RCCR11)2) TA=-40 to +85°C,VDD=3V -15 15 %
RC oscillator current con-
IDD(RC) TA=25°C,VDD=3V 7001) µA
sumption
tsu(RC) RC oscillator setup time TA=25°C,VDD=3V 102) µs
1)
fPLL x4 PLL input clock 1 MHz
tLOCK PLL Lock time5) 2 ms
tSTAB PLL Stabilization time5) 4 ms
fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V 0.14) %
ACCPLL x4 PLL Accuracy
fRC = 1MHz@TA=40 to +85°C,VDD= 3V 0.14) %
tw(JIT) PLL jitter period fRC = 1MHz 83) kHz
JITPLL PLL jitter (∆fCPU/fCPU) 13) %
IDD(PLL) PLL current consumption TA=25°C 1901) µA

Notes:
1. Data based on characterization results, not tested in production
2. RCCR1 is a factory-calibrated setting for 700MHz with ±0.2 accuracy @ TA =25°C, VDD=3V. See “INTERNAL RC OS-
CILLATOR ADJUSTMENT” on page 23.
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy
5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.

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OPERATING CONDITIONS (Cont’d)

Figure 53. RC Osc Freq vs VDD @ TA=25°C Figure 54. RC Osc Freq vs VDD
(Calibrated with RCCR1: 3V @ 25°C) (Calibrated with RCCR0: 5V@ 25°C)

1.00 1.10
0.95 1.00
0.90 0.90
Output Freq (MHz)

-45°

Output Freq. (MHz)

0.85 0.80
0.80 0.70 0°

0.75 0.60 25°

0.70 0.50 90°

0.40 105°
0.65
0.30 130°
0.60
0.20
0.55
0.10
0.50 0.00
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 2.5 3 3.5 4 4.5 5 5.5 6
VDD (V) Vdd (V)

Figure 55. Typical RC oscillator Accuracy vs

temperature @ V DD=5V
(Calibrated with RCCR0: 5V @ 25°C Figure 56. RC Osc Freq vs V DD and RCCR Value

1.80
2
( ) 1.60
1 *
1.40
RC Accuracy

Output Freq. (MHz)

0 ( )
* 1.20
-1
-2 1.00 rccr=00h
-3 0.80 rccr=64h
-4 rccr=80h
( ) 0.60
-5 *
0.40 rccr=C0h
-45 0 25 85 125
0.20 rccr=FFh
Temperature (°C)
( ) tested in production 0.00
*
2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6

Vdd (V)

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OPERATING CONDITIONS (Cont’d)

Figure 57. PLL ∆fCPU/fCPU versus time
∆fCPU/fCPU

Max

t
0

Min
tw(JIT) tw(JIT)

Figure 58. PLLx4 Output vs CLKIN frequency Figure 59. PLLx8 Output vs CLKIN frequency

7.00
11.00
Output Frequency (MHz)
Output Frequency (MHz)

6.00
9.00
5.00
3.3 7.00 5.5
4.00
3 5
2.7 5.00 4.5
3.00
4
2.00 3.00

1.00 1.00
1 1.5 2 2.5 3 0.85 0.9 1 1.5 2 2.5

External Input Clock Frequency (MHz) External Input Clock Frequency (MHz)

Note: fOSC = fCLKIN/2*PLL4

Note: fOSC = fCLKIN/2*PLL8
13.3.4.3 32MHz PLL
TA = -40 to 125°C, unless otherwise specified
Symbol Parameter Min Typ Max Unit
VDD Voltage 1) 4.5 5 5.5 V
fPLL32 Frequency 1) 32 MHz
fINPUT Input Frequency 7 8 9 MHz

Note 1: 32 MHz is guaranteed within this voltage range.

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13.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for vice consumption, the two current values must be
the ST7 functional operating modes over tempera- added (except for HALT mode for which the clock
ture range does not take into account the clock is stopped).
source current consumption. To get the total de-
13.4.1 Supply Current
TA = -40 to +125°C unless otherwise specified
Symbol Parameter Conditions Typ Max Unit
Supply current in RUN mode fCPU=8MHz 1) 7.5 12
Supply current in WAIT mode fCPU=8MHz 2) 3.7 6
mA
fCPU=500kHz 3)

VDD=5.5V
Supply current in SLOW mode 1.6 2.5
IDD Supply current in SLOW WAIT mode fCPU=500kHz 4) 1.6 2.5
-40°C≤TA≤+85°C 1 10
Supply current in HALT mode
TA= +125°C 15 50 µA
Supply current in AWUFH mode 5)6) TA= +25°C 20 30

Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
6. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 60. Typical IDD in RUN vs. fCPU Figure 61. Typical IDD in SLOW vs. fCPU

9.0
1.6
8.0 8 MHz
1.4 250 KHz
7.0 4 MHz
1.2 125 KHz
6.0
1 MHz
Idd (mA)

1.0 62.5 Khz

Idd (mA)

5.0
D

4.0 0.8
TB
TB

3.0 0.6
2.0 0.4
1.0 0.2
0.0 0.0
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd (V) Vdd (V)

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SUPPLY CURRENT CHARACTERISITCS (Cont’d)

Figure 62. Typical IDD in WAIT vs. f CPU Figure 64. Typical IDD in AWUFH mode
at TA=25°C
1.4
250 KHz 0.035
1.2
0.030 fawu_rc ~125 KHz
125 KHz
1.0 0.025
62.5 Khz

Idd(mA)
0.8 0.020
Idd (mA)

0.6 0.015
0.010
0.4
0.005
0.2 0.000
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V)

Vdd (V)

Figure 65. Typical IDD vs. Temperature

Figure 63. Typical IDD in SLOW-WAIT vs. fCPU at VDD = 5V and fCPU = 8MHz

1.4 8.0
250 KHz
1.2
125 KHz
1.0 25°
D

7.0
62.5 Khz
Idd (mA)

0.8
-45°
90°
TB

0.6 130°
6.0
0.4
0.2
Idd (mA)

0.0 5.0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd (V)
4.0

3.0

2.0
2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6
Vdd (V)

13.4.2 On-chip peripherals

Symbol Parameter Conditions Typ Unit
fCPU=4MHz VDD=3.0V 50
IDD(AT) 12-bit Auto-Reload Timer supply current 1)
fCPU=8MHz VDD=5.0V 150
fCPU=4MHz VDD=3.0V 50
IDD(SPI) SPI supply current 2) µA
fCPU=8MHz VDD=5.0V 300
VDD=3.0V TBD
IDD(ADC) ADC supply current when converting 3) fADC=4MHz
VDD=5.0V TBD

1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM
mode at fcpu=8MHz.
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-
tion (data sent equal to 55h).
3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with am-
plifier off.

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13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V DD, fOSC, and TA.
13.5.1 General Timings
Symbol Parameter 1) Conditions Min Typ 2) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time fCPU=8MHz
250 375 1500 ns
Interrupt reaction time 3) 10 22 tCPU
tv(IT) fCPU=8MHz
tv(IT) = ∆tc(INST) + 10 1.25 2.75 µs

Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to fin-
ish the current instruction execution.

13.5.2 Auto Wakeup from Halt Oscillator (AWU)

Symbol Parameter Conditions Min Typ Max Unit
fAWU AWU Oscillator Frequency 50 125 250 kHz
tRCSRT AWU Oscillator startup time 50 µs

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13.6 MEMORY CHARACTERISTICS

TA = -40°C to 125°C, unless otherwise specified
13.6.1 RAM and Hardware Registers
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) HALT mode (or RESET) 1.6 V

13.6.2 FLASH Program Memory

Symbol Parameter Conditions Min Typ Max Unit
VDD Operating voltage for Flash write/erase 2.4 5.5 V
Programming time for 1~32 bytes 2) TA=−40 to +85°C 5 10 ms
tprog
Programming time for 1.5 kBytes TA=+25°C 0.24 0.48 s
tRET Data retention 4) TA =+55°C3) 20 years
NRW Write erase cycles TA=+25°C 10K7) cycles
Read / Write / Erase
modes 2.66) mA
IDD Supply current fCPU = 8MHz, VDD = 5.5V
No Read/No Write Mode 100 µA
Power down mode / HALT 0 0.1 µA

13.6.3 EEPROM Data Memory

Symbol Parameter Conditions Min Typ Max Unit
tprog Programming time for 1~32 bytes TA=−40 to +85°C 5 10 ms
tret Data retention 4) TA=+55°C 3) 20 years
NRW Write erase cycles TA=+25°C 300K7) cycles

Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the TA decreases.
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.

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13.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba- ■ ESD: Electro-Static Discharge (positive and
sis during product characterization. negative) is applied on all pins of the device until
13.7.1 Functional EMS a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the and negative) is applied to V DD and VSS through
product (toggling 2 LEDs through I/O ports), the a 100pF capacitor, until a functional disturbance
product is stressed by two electro magnetic events occurs. This test conforms with the IEC 1000-4-
until a failure occurs (indicated by the LEDs). 4 standard.
A device reset allows normal operations to be re-
sumed.
Symbol Parameter Conditions Neg 1) Pos 1) Unit
Voltage limits to be applied on any I/O pin VDD=5V, TA=+25°C, fOSC=8MHz
VFESD -1.2 >1.5
to induce a functional disturbance conforms to IEC 1000-4-2
Fast transient voltage burst limits to be ap- kV
VDD=5V, TA=+25°C, fOSC=8MHz
VFFTB plied through 100pF on VDD and VDD pins -1 1
conforms to IEC 1000-4-4
to induce a functional disturbance

Figure 66. EMC Recommended power supply connection 2)

ST72XXX
10µF 0.1µF VDD

ST7
DIGITAL NOISE
FILTERING
VSS

VDD

Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

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EMC CHARACTERISTICS (Cont’d)

13.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Note 1. Data based on characterization results, not tested in production.

13.7.3 7Absolute Electrical Sensitivity Machine Model Test Sequence

Based on three different tests (ESD, LU and DLU) – CL is loaded through S1 by the HV pulse gener-
using specific measurement methods, the product ator.
is stressed in order to determine its performance in – S1 switches position from generator to ST7.
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note. – A discharge from C L to the ST7 occurs.
13.7.3.1 Electro-Static Discharge (ESD) – S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
Electro-Static Discharges (3 positive then 3 nega- charge state. S2 must be opened at least 10ms
tive pulses separated by 1 second) are applied to prior to the delivery of the next pulse.
the pins of each sample according to each pin
combination. The sample size depends of the – R (machine resistance), in series with S2, en-
number of supply pins of the device (3 parts*(n+1) sures a slow discharge of the ST7.
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 67 and the following test sequences.
Human Body Model Test Sequence
– CL is loaded through S1 by the HV pulse gener-
ator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C 4000
(Human Body Model)
V
Electro-static discharge voltage
VESD(MM) TA=+25°C TBD
(Machine Model)

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Figure 67. Typical Equivalent ESD Circuits

S1 R=1500Ω S1

R=10k~10MΩ
HIGH VOLTAGE HIGH VOLTAGE
PULSE CL=100pF
ST7 S2 PULSE ST7
GENERATOR GENERATOR

CL=200pF S2

HUMAN BODY MODEL MACHINE MODEL

Notes:
1. Data based on characterization results, not tested in production.

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ST7LITE2

EMC CHARACTERISTICS (Cont’d)

13.7.3.2 Static and Dynamic Latch-Up ■ DLU: Electro-Static Discharges (one positive
■ LU: 3 complementary static tests are required then one negative test) are applied to each pin
on 10 parts to assess the latch-up performance. of 3 samples when the micro is running to
A supply overvoltage (applied to each power assess the latch-up performance in dynamic
supply pin), a current injection (applied to each mode. Power supplies are set to the typical
input, output and configurable I/O pin) and a values, the oscillator is connected as near as
power supply switch sequence are performed possible to the pins of the micro and the
on each sample. This test conforms to the EIA/ component is put in reset mode. This test
JESD 78 IC latch-up standard. For more details, conforms to the IEC1000-4-2 and SAEJ1752/3
refer to the AN1181 ST7 application note. standards and is described in Figure 68. For
more details, refer to the AN1181 ST7
application note.
Electrical Sensitivities
Symbol Parameter Conditions Class 1)
TA=+25°C A
LU Static latch-up class
TA=+85°C TBD
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

Figure 68. Simplified Diagram of the ESD Generator for DLU

RCH=50MΩ RD=330Ω DISCHARGE TIP VDD

VSS
CS=150pF HV RELAY
ST7
ESD
GENERATOR 2) DISCHARGE
RETURN CONNECTION

Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.

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EMC CHARACTERISTICS (Cont’d)

13.7.4 ESD Pin Protection Strategy Standard Pin Protection
To protect an integrated circuit against Electro- To protect the output structure the following ele-
Static Discharge the stress must be controlled to ments are added:
prevent degradation or destruction of the circuit el- – A diode to VDD (3a) and a diode from VSS (3b)
ements. The stress generally affects the circuit el- – A protection device between VDD and V SS (4)
ements which are connected to the pads but can
also affect the internal devices when the supply To protect the input structure the following ele-
pads receive the stress. The elements to be pro- ments are added:
tected must not receive excessive current, voltage – A resistor in series with the pad (1)
or heating within their structure. – A diode to VDD (2a) and a diode from VSS (2b)
An ESD network combines the different input and – A protection device between VDD and V SS (4)
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 69 and Figure 70 for standard
pins.
Figure 69. Positive Stress on a Standard Pad vs. VSS
VDD VDD

(3a) (2a)

(1)
OUT (4) IN

Main path
(3b) (2b)
Path to avoid

VSS VSS

Figure 70. Negative Stress on a Standard Pad vs. VDD

VDD VDD

(3a) (2a)

(1)
OUT (4) IN

Main path
(3b) (2b)

VSS VSS

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13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics
Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage 0.3xVDD
V
VIH Input high level voltage 0.7xVDD
Schmitt trigger voltage
Vhys 400 mV
hysteresis 1)
IL Input leakage current VSS≤VIN≤VDD ±1
µA
IS Static current consumption 2) Floating input mode 200
Weak pull-up equivalent VDD=5V 50 120 250
RPU VIN=VSS kΩ
resistor3) VDD=3V 160
CIO I/O pin capacitance 5 pF
Output high to low level fall
tf(IO)out 25
time 1) CL=50pF
ns
Output low to high level rise Between 10% and 90%
tr(IO)out 25
time 1)
tw(IT)in External interrupt pulse time 4) 1 tCPU

Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 71). Data based on design simulation and/or technology
characteristics, not tested in production.
3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 72).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

Figure 71. Two typical Applications with unused I/O Pin

VDD ST7XXX
UNUSED I/O PORT
10kΩ 10kΩ
UNUSED I/O PORT
ST7XXX
Note: only external pull-up allowed on ICCCLK pin

Figure 72. Typical IPU vs. VDD with V IN=VSS

90

80 Ta=1 40°C
Ta=9 5°C
70 Ta=2 5°C
Ta=-45 °C
60
Ipu (uA)

50

40
TO BE CHARACTERIZED
30

20

10

0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

13.8.2 Output Driving Current
Subject to general operating conditions for V DD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
IIO=+5mA TA≤85°C 1.0
Output low level voltage for a standard I/O pin TA≥85°C 1.2
when 8 pins are sunk at same time
(see Figure 76) IIO=+2mA TA≤85°C 0.4
TA≥85°C 0.5
VOL 1)
IIO=+20mA,TA≤85°C 1.3

VDD=5V
Output low level voltage for a high sink I/O pin TA≥85°C 1.5
when 4 pins are sunk at same time
(see Figure 78) IIO=+8mA TA≤85°C 0.75
TA≥85°C 0.85
IIO=-5mA, TA≤85°C VDD-1.5
Output high level voltage for an I/O pin TA≥85°C VDD-1.6
VOH 2) when 4 pins are sourced at same time
(see Figure 84) IIO=-2mA T A≤85°C VDD-0.8
TA≥85°C VDD-1.0
Output low level voltage for a standard I/O pin
IIO=+2mA TA≤85°C 0.5
when 8 pins are sunk at same time V
TA≥85°C 0.6
VOL 1)3) (see Figure 75)
Output low level voltage for a high sink I/O pin IIO=+8mA TA≤85°C 0.5
VDD=3.3V

when 4 pins are sunk at same time TA≥85°C 0.6

Output high level voltage for an I/O pin IIO=-2mA T A≤85°C VDD-0.8
VOH 2)3)
when 4 pins are sourced at same time TA≥85°C VDD-1.0
Output low level voltage for a standard I/O pin
IIO=+2mA TA≤85°C 0.6
when 8 pins are sunk at same time
TA≥85°C 0.7
VOL 1)3) (see Figure 74)
Output low level voltage for a high sink I/O pin IIO=+8mA TA≤85°C 0.6
when 4 pins are sunk at same time TA≥85°C 0.7
VDD=2.7V

Output high level voltage for an I/O pin

IIO=-2mA T A≤85°C VDD-0.9
VOH 2)3) when 4 pins are sourced at same time
TA≥85°C VDD-1.0
(see Figure 81)

Notes:

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD.
3. Not tested in production, based on characterization results.

Figure 73. Typical VOL at VDD=2.4V (standard) Figure 74. Typical VOL at VDD=2.7V (standard)
0.70 0.60

0.60 0.50
VOL at VDD=2.7V

0.50 -45
VOL at VDD=2.4V

0.40 -45°C
0°C 0°C
0.40
TO BE CHARACTERIZED 25°C 0.30 25°C
0.30 90°C
90°C
0.20 130°C
0.20 130°C

0.10
0.10

0.00 0.00
0.01 1 2 0.01 1 2
lio (mA) lio (mA)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 75. Typical VOL at VDD=3.3V (standard) Figure 76. Typical VOL at VDD=5V (standard)

0.70

0.80
0.60
0.70
0.50 0.60 -45°C
VOL at VDD=3.3V

VOL at VDD=5V
-45°C 0.50 0°C
0.40 0°C
0.40 25°C
25°C
90°C
0.30 90°C 0.30
130°C
130°C 0.20
0.20
0.10

0.10 0.00
0.01 1 2 3 4 5
0.00 lio (mA)
0.01 1 2 3
lio (mA)

Figure 77. Typical VOL at VDD=2.4V (high-sink) Figure 79. Typical VOL at VDD=3V (high-sink)

1.00 1.20
0.90
1.00
0.80
Vol (V) at VDD=3V (HS)
VOL at VDD=2.4V (HS)

0.70
0.80 -45
-45
0.60 0°C
0°C
0.50 25°C 0.60
25°C
0.40 90°C
90°C
130°C 0.40
0.30 130°C
0.20 0.20
0.10
0.00
0.00
6 7 8 9 10
6 7 8 9 10 15

lio (mA) lio (mA)

Figure 78. Typical VOL at VDD=5V (high-sink)

2.50

2.00
Vol (V) at VDD=5V (HS)

1.50 -45
0°C
25°C
1.00 90°C
130°C

0.50

0.00
6 7 8 9 10 15 20 25 30 35 40

lio (mA)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 80. Typical VDD-VOH at VDD=2.4V Figure 82. Typical VDD-VOH at VDD=3V

1.60
1.60
1.40
1.40

VDD-VOH at VDD=3V
1.20
VDD-VOH at VDD=2.4V

1.20
-45°C
-45°C 1.00
1.00 0°C
0°C
0.80 25°C
0.80 25°C
90°C
90°C 0.60
0.60 130°C
130°C
0.40
0.40
0.20
0.20
0.00
0.00
-0.01 -1 -2 -3
-0.01 -1 -2
lio (mA)
lio (mA)

Figure 81. Typical VDD-VOH at VDD=2.7V Figure 83. Typical VDD-VOH at VDD=4V

1.20 2.50

1.00 2.00
VDD-VOH at VDD=4V
VDD-VOH at VDD=2.7V

0.80 -45°C
-45°C
1.50
0°C 0°C
0.60 25°C 25°C
90°C 1.00 90°C
0.40 130°C 130°C

0.50
0.20

0.00 0.00
-0.01 -1 -2 -0.01 -1 -2 -3 -4 -5
lio(mA) lio (mA)

Figure 84. Typical VDD-VOH at VDD=5V

2.00
1.80
1.60
VDD-VOH at VDD=5V

1.40
-45°C
1.20 0°C
1.00 25°C
90°C
0.80 TO BE CHARACTERIZED 130°C
0.60
0.40
0.20
0.00
-0.01 -1 -2 -3 -4 -5
lio (mA)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 85. Typical VOL vs. VDD (standard I/Os)

0.70 0.06

0.60 0.05

Vol (V) at lio=0.01mA

Vol (V) at lio=2mA

0.50 -45 -45

0.04
0.40 0°C 0°C
25°C 0.03 25°C
0.30
90°C 90°C
0.02
0.20 130°C 130°C

0.10 0.01

0.00 0.00
2.4 2.7 3.3 5 2.4 2.7 3.3 5
VDD (V) VDD (V)

Figure 86. Typical VOL vs. VDD (high-sink I/Os)

0.70 1.00
VOL vs VDD (HS) at lio=20mA
VOL vs VDD (HS) at lio=8mA

0.90
0.60
0.80
0.50 -45 0.70 -45
0°C 0.60 0°C
0.40
25°C 0.50 25°C
0.30 0.40 90°C
90°C
0.20 130°C 0.30 130°C
0.20
0.10 0.10
0.00 0.00
2.4 3 5 2.4 3 5

VDD (V) VDD (V)

Figure 87. Typical VDD-VOH vs. VDD

1.80
1.10
1.70
1.00
VDD-VOH (V) at lio=-2mA

1.60
VDD-VOH at lio=-5mA

1.50 0.90 -45°C

1.40 -45°C 0°C
0°C 0.80
1.30
25°C
25°C
0.70
1.20 90°C 90°C
130°C 0.60 130°C
1.10

1.00
0.50
0.90
0.40
0.80
4 5 2.4 2.7 3 4 5
VDD VDD (V)

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 ST7LITE2

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin
TA = -40°C to 125°C, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage 0.3xVDD
V
VIH Input high level voltage 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 1) 2 V
IIO=+5mA TA≤85°C 1.0
0.5
TA≥85°C 1.2
VOL Output low level voltage 2) VDD=5V V
IIO=+2mA TA≤85°C 0.4
0.2
TA≥85°C 0.5
VDD=5V 20 40 80
RON Pull-up equivalent resistor 3) 1) kΩ
VDD=3V. 40 70 120
tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs
th(RSTL)in External reset pulse hold time 4) 20 µs
tg(RSTL)in Filtered glitch duration 5) 200 ns

Figure 88. Typical Application with RESET pin 6)7)8)

Recommended VDD ST72XXX

if LVD is disabled
VDD VDD
RON

USER 0.01µF 4.7kΩ INTERNAL

EXTERNAL RESET
RESET Filter
CIRCUIT 5)
0.01µF
PULSE
WATCHDOG
GENERATOR
LVD RESET
Required if LVD is disabled

Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 113. Otherwise the reset will not be taken into account internally.
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for IINJ(RESET) in section 13.2.2 on page 92.

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13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface Refer to I/O port characteristics for more details on
Subject to general operating conditions for V DD, the input/output alternate function characteristics
fOSC, and TA unless otherwise specified. (SS, SCK, MOSI, MISO).

Symbol Parameter Conditions Min Max Unit

Master fCPU/128
fCPU/42
fSCK fCPU=8MHz 0.0625
SPI clock frequency MHz
1/tc(SCK) Slave
0 fCPU/24
fCPU=8MHz
tr(SCK)
SPI clock rise and fall time see I/O port pin description
tf(SCK)
tsu(SS) SS setup time Slave 120
th(SS) SS hold time Slave 120
tw(SCKH) Master 100
SCK high and low time
tw(SCKL) Slave 90
tsu(MI) Master 100
Data input setup time
tsu(SI) Slave 100
ns
th(MI) Master 100
Data input hold time
th(SI) Slave 100
ta(SO) Data output access time Slave 0 120
tdis(SO) Data output disable time Slave 240
tv(SO) Data output valid time 120
Slave (after enable edge)
th(SO) Data output hold time 0
tv(MO) Data output valid time 0.25
Master (before capture edge) tCPU
th(MO) Data output hold time 0.25

Figure 89. SPI Slave Timing Diagram with CPHA=0 3)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tf(SCK)
MISO OUTPUT see
see note 2 MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 90. SPI Slave Timing Diagram with CPHA=11)

SS INPUT
tsu(SS) tc(SCK) th(SS)

CPHA=0
SCK INPUT

CPOL=0
CPHA=0
CPOL=1

ta(SO) tw(SCKH) tdis(SO)

tw(SCKL) tv(SO) th(SO)
tr(SCK)
tf(SCK)
MISO OUTPUT see see
note 2 HZ MSB OUT BIT6 OUT LSB OUT note 2

tsu(SI) th(SI)

MOSI INPUT MSB IN BIT1 IN LSB IN

Figure 91. SPI Master Timing Diagram 1)

SS INPUT
tc(SCK)

CPHA=0
CPOL=0
CPHA=0
SCK INPUT

CPOL=1

CPHA=1
CPOL=0

CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tw(SCKL) tf(SCK)

tsu(MI) th(MI)

MISO INPUT MSB IN BIT6 IN LSB IN

tv(MO) th(MO)

MOSI OUTPUT see note 2 MSB OUT BIT6 OUT LSB OUT see note 2

Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

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ST7LITE2

13.11 10-BIT ADC CHARACTERISTICS

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
fADC ADC clock frequency 4 MHz
2)
VAIN Conversion voltage range VSSA VDDA V
3)
RAIN External input resistor 10 kΩ
CADC Internal sample and hold capacitor 6 pF
tSTAB Stabilization time after ADC enable 0 4)
µs
Conversion time (Sample+Hold) 3.5
fCPU=8MHz, fADC=4MHz
tADC - Sample capacitor loading time 4
1/fADC
- Hold conversion time 10
Analog Part 1
IADC mA
Digital Part 0.2

Figure 92. Typical Application with ADC

VDD

VT
0.6V
RAIN AINx 10-Bit A/D
VAIN Conversion

VT
0.6V IL CADC
±1µA 6pF

ST72XXX

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.

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 ST7LITE2

ADC CHARACTERISTICS (Cont’d)

ADC Accuracy with V DD=5.0V

Symbol Parameter Conditions Typ Max Unit
ET Total unadjusted error 2) TBD 4.5
EO Offset error 2) TBD 2
EG Gain Error 2) fCPU=8MHz, fADC=4MHz 1) TBD 3.5 LSB
ED Differential linearity error 2) TBD 3
EL Integral linearity error 2) TBD 4

Notes:
1) Data based on characterization results over the whole temperature range, monitored in production.
2) Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.8 does not affect the ADC
accuracy.

Figure 93. ADC Accuracy Characteristics with amplifier disabled

Digital Result ADCDR EG

(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
DD SS
1LSB = --------------------------------
1021 I DE AL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0 1 2 3 4 5 6 7 1021 1022 1023 1024
VSS VDD

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ADC CHARACTERISTICS (Cont’d)

Figure 94. ADC Accuracy Characteristics with amplifier enabled

Digital Result ADCDR EG

(1) Example of an actual transfer curve
704
(2) The ideal transfer curve
V –V (3) End point correlation line
DD SS
1LSB = --------------------------------
I DE AL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
(3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
correlation line.
1 LSBIDEAL
108
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 701 702 703 704
VSS Vin (OPAMP)
62.5mV 430mV

Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that fADC be less than or equal
to 2 MHz. (if fCPU=8MHz. then SPEED=0, SLOW=1).

Vout (ADC input)

Vmax

Noise
Vmin

Vin
0V 430mV (OPAMP input)

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 ST7LITE2

ADC CHARACTERISTICS (Cont’d)

Symbol Parameter Conditions Min Typ Max Unit

VDD(AMP) Amplifier operating voltage 4.5 5.5 V
VIN Amplifier input voltage VDD=5V 62.5 430 mV
VOFFSET Amplifier offset voltage 175 mV
VSTEP Step size for monotonicity3) 5 mV
Linearity Output Voltage Response Linear
Gain factor Amplified Analog input Gain2) 8
Vmax Output Linearity Max Voltage VINmax = 430mV, V
Vmin Output Linearity Min Voltage VDD=5V V

Notes:
1) Data based on characterization results over the whole temperature range, not tested in production.
2) For precise conversion results it is recommended to calibrate the amplifier at the following two points:
– offset at VINmin = 0V
– gain at full scale (for example VIN=250mV)
3) Monotonicity guaranteed if VIN increases or decreases in steps of min. 5mV.

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ST7LITE2

14 PACKAGE CHARACTERISTICS

14.1 PACKAGE MECHANICAL DATA

Figure 95. 20-Pin Plastic Small Outline Package, 300-mil Width

D
mm inches
h x 45× Dim.
L
Min Typ Max Min Typ Max
A A 2.35 2.65 0.093 0.104
A1 c
A1 0.10 0.30 0.004 0.012
a
B e B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.60 13.00 0.496 0.512
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
E H
α 0° 8° 0° 8°
L 0.40 1.27 0.016 0.050
Number of Pins
N 20

Figure 96. 20-Pin Plastic Dual In-Line Package, 300-mil Width

mm inches
Dim.
A2 A Min Typ Max Min Typ Max
A 5.33 0.210
A1 L c A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b eB
D1 b2 e b 0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D D 24.89 26.16 26.92 0.980 1.030 1.060
D1 0.13 0.005
e 2.54 0.100
20 11
eB 10.92 0.430
E1
E1 6.10 6.35 7.11 0.240 0.250 0.280
1 10
L 2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
N 20

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 ST7LITE2

PACKAGE CHARACTERISTICS (Cont’d)

Table 21. THERMAL CHARACTERISTICS

Symbol Ratings Value Unit

RthJA Package thermal resistance (junction to ambient) TBD °C/W
PD Power dissipation 1) 500 mW
TJmax Maximum junction temperature 2) 150 °C

Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.

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14.2 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only as design guidelines.
Figure 97. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)

250
COOLING PHASE
200 5 sec (ROOM TEMPERATURE)

SOLDERING
150 80°C PHASE
Temp. [°C]
100
PREHEATING
PHASE
50

0 Time [sec]
20 40 60 80 100 120 140 160

Figure 98. Recommended Reflow Soldering Oven Profile (MID JEDEC)

250
Tmax=220+/-5°C
for 25 sec
200

150 sec above 183°C

150 90 sec at 125°C
Temp. [°C]
100 ramp down natural
ramp up 2°C/sec max
50 2°C/sec for 50sec

0 Time [sec]
100 200 300 400

Recommended glue for SMD plastic packages:

■ Heraeus: PD945, PD955

■ Loctite: 3615, 3298

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 ST7LITE2

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in a user (FFh). This implies that FLASH devices have to be
programmable version (FLASH). FLASH devices configured by the customer using the Option
are shipped to customers with a default content Bytes.

15.1 OPTION BYTES

The two option bytes allow the hardware configu- OPT3:2 = SEC[1:0] Sector 0 size definition
ration of the microcontroller to be selected. These option bits indicate the size of sector 0 ac-
The option bytes can be accessed only in pro- cording to the following table.
gramming mode (for example using a standard Sector 0 Size SEC1 SEC0
ST7 programming tool).
0.5k 0 0
1k 0 1
OPTION BYTE 0
2k 1 0
OPT7 = Reserved, must always be 1.
4k 1 1

OPT6:4 = OSCRANGE[2:0] Oscillator range OPT1 = FMP_R Read-out protection

When the internal RC oscillator is not selected This option indicates if the FLASH program mem-
(Option OSC=1), these option bits select the range ory and Data EEPROM is protected against pira-
of the resonator oscillator current source or the ex- cy. The read-out protection blocks access to the
ternal clock source. program and data areas in any mode except user
OSCRANGE mode and IAP mode. Erasing the option bytes
when the FMP_R option is selected will cause the
2 1 0 whole memory to be erased first and the device
LP 1~2MHz 0 0 0 can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and section 4.5
Typ. MP 2~4MHz 0 0 1 on page 14 for more details
frequency 0: Read-out protection off
MS 4~8MHz 0 1 0
range with 1: Read-out protection on
Resonator HS 8~16MHz 0 1 1
VLP 32.768kHz 1 0 0
OPT0 = FMP_W FLASH write protection
External on OSC1 1 0 1 This option indicates if the FLASH program mem-
Clock source: ory is write protected.
CLKIN on PB4 1 1 1 Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
Reserved 1 1 0
be erased or programmed again.
Note: When the internal RC oscillator is selected, 0: Write protection off
the OSCRANGE option bits must be kept at their 1: Write protection on
default value in order to select the 256 clock cycle
delay (see Section 7.5).

OPTION BYTE 0 OPTION BYTE 1

7 0 7 0
OSCRANGE FMP FMP PLL PLL PLL32 WDG WDG
Res. SEC1 SEC0 OSC LVD1 LVD0
2:0 R W x4x8 OFF OFF SW HALT
Default
1 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1
Value

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ST7LITE2

OPTION BYTES (Cont’d)

OPTION BYTE 1
Table 22. LVD Threshold Configuration
OPT7 = PLLx4x8 PLL Factor selection. Configuration LVD1 LVD0
0: PLLx4 LVD Off 1 1
1: PLLx8
Highest Voltage Threshold (∼4.1V) 1 0
Medium Voltage Threshold (∼3.5V) 0 1
OPT6 = PLLOFF PLL disable.
Lowest Voltage Threshold (∼2.8V) 0 0
0: PLL enabled
1: PLL disabled (by-passed) Each device is available for production in a user
programmable version (FLASH). FLASH devices
OPT5 = PLL32OFF 32MHz PLL disable. are shipped to customers with a default content
0: PLL32 enabled (FFh). This implies that FLASH devices have to be
1: PLL32 disabled (by-passed) configured by the customer using the Option
Bytes.

OPT4 = OSC RC Oscillator selection

0: RC oscillator on OPT1 = WDG SW Hardware or Software
1: RC oscillator off Watchdog
This option bit selects the watchdog type.
Note: 1% RC oscillator available on ST7LITE25
and ST7LITE29 devices only 0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)

OPT3:2 = LVD[1:0] Low voltage detection selec-

tion OPT0 = WDG HALT Watchdog Reset on Halt
These option bits enable the LVD block with a se- This option bit determines if a RESET is generated
lected threshold as shown in Table 22. when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Table 23. List of valid option combinations
Operating conditions Option Bits
VDD range Clock Source PLL Typ fCPU OSC PLLOFF PLLx4x8
off 0.7MHz @3V 0 1 x
Internal RC 1%1) x4 2.8MHz @3V 0 0 0
x8 - - - -
2.4V - 3.3V
External clock or oscillator off 0-4MHz 1 1 x
(depending on OPT6:4 selec- x4 4MHz 1 0 0
tion) x8 - - - -
off 1MHz @5V 0 1 x
Internal RC 1% 1) x4 - - - -
x8 8MHz @5V 0 0 1
3.3V - 5.5V
External clock or oscillator off 0-8MHz 1 1 x
(depending on OPT6:4 selec- x4 - - - -
tion) x8 8 MHz 1 0 1

Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only

Note: see Clock Management Block diagram in Figure 13

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 ST7LITE2

15.2 DEVICE ORDERING INFORMATION

Contact ST sales office for product availability

Table 24. Supported part numbers

Program Data
RAM Temp.
Part Number Memory EEPROM Package
(Bytes) Range
(Bytes) (Bytes)
ST7FLITE20F2B6 DIP20
-
ST7FLITE20F2M6 SO20
ST7FLITE25F2B6 DIP20
8K FLASH 384 - -40°C to 85°C
ST7FLITE25F2M6 SO20
ST7FLITE29F2B6 DIP20
256
ST7FLITE29F2M6 SO20

Contact ST sales office for product availability

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ST7LITE2

15.3 DEVELOPMENT TOOLS

STmicroelectronics offers a range of hardware ST Emulators
and software development tools for the ST7 micro- The emulator is delivered with everything (probes,
controller family. Full details of tools available for TEB, adapters etc.) needed to start emulating the
the ST7 from third party manufacturers can be ob- devices. To configure the emulator to emulate dif-
tain from the STMicroelectronics Internet site: ferent ST7 subfamily devices, the active probe for
➟ http//mcu.st.com. the ST7 EMU3 can be changed and the ST7EMU3
Tools from these manufacturers include C compli- probe is designed for easy interchange of TEBs
ers, emulators and gang programmers. (Target Emulation Board). See Table 26 for more
STMicroelectronics Tools details.
Two types of development tool are offered by ST,
all of them connect to a PC via a parallel (LPT) or
USB port: see Table 25 and Table 26 for more de-
tails.
Table 25. STMicroelectronics Tools Features
In-Circuit Emulation Programming Capability1) Software Included
Yes, powerful emulation ST7 CD-ROM with:
ST7 EMU3 Emulator features including trace/ No – ST7 Assembly toolchain
logic analyzer – STVD7 powerful Source Level
Debugger for Win 9x, Win 2000,
ME and NT4.0
– C compiler demo versions
ST7 Programming Board No Yes (All packages)
– ST Realizer for Win 95.
Windows Programming Tools for
Win 9x, NT4.0, 2000 and ME

Note:
1. In-Circuit Programming (ICP) interface for FLASH devices.
Table 26. Dedicated STMicroelectronics Development Tools
Active Probe
Supported Products ST7 Development Kit ST7 Emulator ST7 Programming Board
& TEB
ST7MDT10-EPB/EU
ST7MDT10-EPB/US
ST7FLITE20
ST7FLITE25 ST7MDT10-EPB/UK
N/A ST7MDT10-EMU3 ST7MDT10-TEB
ST7FLITE29 ST7-STICK/EU
ST7-STICK/US
ST7-STICK/UK

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 ST7LITE2

15.4 ST7 APPLICATION NOTES

IDENTIFICATION DESCRIPTION
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION

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ST7LITE2

IDENTIFICATION DESCRIPTION
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
AN1530
LATOR
PROGRAMMING AND TOOLS
AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039 ST7 MATH UTILITY ROUTINES
AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
AN1179
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

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16 IMPORTANT NOTES

16.1 EXECUTION OF BTJX INSTRUCTION

When testing the address $FF with the 16.3 A/ D CONVERTER ACCURACY FOR FIRST
"BTJT" or "BTJF" instructions, the CPU may CONVERSION

perform an incorrect operation when the rel- When the ADC is enabled after being pow-
ative jump is negative and performs an ad- ered down (for example when waking up
dress page change. from HALT, ACTIVE-HALT or setting the
ADON bit in the ADCCSR register), the first
To avoid this issue, including when using a C
conversion (8-bit or 10-bit) accuracy does
compiler, it is recommended to never use ad-
not meet the accuracy specified in the da-
dress $00FF as a variable (using the linker
tasheet.
parameter for example).
Workaround
16.2 ADC CONVERSION SPURIOUS RESULTS
In order to have the accuracy specified in the
Spurious conversions occur with a rate lower datasheet, the first conversion after a ADC
than 50 per m illi on. Such convers ions switch-on has to be ignored.
happen when the measured voltage is just
between 2 consecutive digital values.
Workaround
A software filter should be implemented to
remove erratic conversion results whenever
they may cause unwanted consequences.

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17 SUMMARY OF CHANGES
Revision Main changes Date
Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) in Table 1, “Device Pin Description,”
on page 7
Modified note 5 in section 4.4 on page 13
Added “and the device can be reprogrammed” in section 4.5.1 on page 14
Added note on RC oscillator in section 7 on page 23 (main features) and changed section
7.1 on page 23: removed reference to ST7LITE20 in RCCR table
Changed Figure 13 on page 25 (CLKIN/2, OSC/2)
Added note in section 7.4 on page 26 (external clock source paragraph)
Added note in the description of AWUPR[7:0] bits in section 9.6.0.1 on page 45
2.0 August-03
Added text specifying that the watchdog counter is a free-running downcounter: Section
11.1.2 and section 11.1.3 on page 51
Added note in the description of OSC option bit and in Table 23, “List of valid option combi-
nations,” on page 124
Changed section 13.7 on page 103
Changed section 13.3.1 on page 93: fCLKIN instead of fOSC
Changed description of WDG HALT option bit (section 15.1 on page 123)
Changed description of FMP_R option bit (section 15.1 on page 123)
Changed Table 26, “Dedicated STMicroelectronics Development Tools,” on page 126

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 ST7LITE2

Notes:

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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
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2003 STMicroelectronics - All Rights Reserved.
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