ST62T53C/T60C/T63C

ST62E60C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 128 bytes
■ Data EEPROM: 64/128 bytes (none on ST62T53C) PDIP20
■ User Programmable Options
■ 13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 6 I/O lines can sink up to 30mA to drive LEDs or PSO20
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■ Digital Watchdog
■ Oscillator Safe Guard
■ Low Voltage Detector for Safe Reset
■ 8-bit A/D Converter with 7 analog inputs CDIP20W
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscillator can be driven by Quartz (See end of Datasheet for Ordering Information)
Crystal Ceramic resonator or RC network
■ User configurable Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development DEVICE SUMMARY
System (connects to an MS-DOS PC via a
parallel port). EPROM
DEVICE OTP (Bytes) EEPROM
(Bytes)
ST62T53C 1836 - -
ST62T60C 3884 - 128
ST62T63C 1836 - 64
ST62E60C - 3884 128

Rev. 2.8

July 2001 1/84

 Table of Contents Document
Page
ST62T53C/T60C/T63C
ST62E60C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Data RAM/EEPROM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 AR Timer Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.4 SPI Alternate function Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.1 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.6 SPI TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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ST62P53C/P60C/P63C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ST6253C/60B/63B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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 ST62T53C/T60C/T63C ST62E60C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION
The ST62T53C, ST62T60C, ST62T63C and fined in the programmable option byte of the OTP/
ST62E60C devices are low cost members of the EPROM versions.
ST62xx 8-bit HCMOS family of microcontrollers,
which is targeted at low to medium complexity ap- OTP devices offer all the advantages of user pro-
plications. All ST62xx devices are based on a grammability at low cost, which make them the
building block approach: a common core is sur- ideal choice in a wide range of applications where
rounded by a number of on-chip peripherals. frequent code changes, multiple code versions or
last minute programmability are required.
The ST62E60C is the erasable EPROM version of
the ST62T60C device, which may be used to em- These compact low-cost devices feature a Timer
ulate the ST62T53C, ST62T60C and ST62T63C comprising an 8-bit counter and a 7-bit program-
devices, as well as the respective ST6253C, mable prescaler, an 8-bit Auto-Reload Timer,
ST6260B and ST6263B ROM devices. EEPROM data capability (except ST62T53C), a
serial port communication interface, an 8-bit A/D
OTP and EPROM devices are functionally identi- Converter with 7 analog inputs and a Digital
cal. The ROM based versions offer the same func- Watchdog timer, making them well suited for a
tionality selecting as ROM options the options de- wide range of automotive, appliance and industrial
applications.
Figure 1. Block Diagram

8-BIT PA0..PA3 / Ain

PORT A
A/D CONVERTER
TEST/V PP TEST
PB0..PB3 / 30 mA Sink
PORT B PB6 / ARTimin / 30 mA Sink
PB7 / ARTimout / 30 mA Sink
NMI INTERRUPT
DATA ROM
USER PORT C PC2 / Sin / Ain
SELECTABLE PC3 / Sout / Ain
PROGRAM PC4 / Sck / Ain
MEMORY
1836 bytes OTP DATA RAM AUTORELOAD
(ST62T53C,T63C)
128 Bytes TIMER
3884 bytes OTP
(ST62T60C)
3884 bytes EPROM
(ST62E60C) DATA EEPROM
64 Bytes TIMER
(ST62T63C)
128 Bytes
(ST62T60C/E60C)
SPI (SERIAL
PERIPHERAL
PC INTERFACE)

STACK LEVEL 1
STACK LEVEL 2 DIGITAL
STACK LEVEL 3 8 BIT CORE WATCHDOG
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6

POWER OSCILLATOR RESET

SUPPLY

VDD VSS OSCin OSCout RESET

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ST62T53C/T60C/T63C ST62E60C

1.2 PIN DESCRIPTIONS

VDD and VSS. Power is supplied to the MCU via PB6/ARTIMin, PB7/ARTIMout. These pins are ei-
these two pins. VDD is the power connection and ther Port B I/O bits or the Input and Output pins of
VSS is the ground connection. the AR TIMER. To be used as timer input function
PB6 has to be programmed as input with or with-
OSCin and OSCout. These pins are internally out pull-up. A dedicated bit in the AR TIMER Mode
connected to the on-chip oscillator circuit. A quartz Control Register sets PB7 as timer output function.
crystal, a ceramic resonator or an external clock PB6-PB7 can also sink 30mA for direct LED driv-
signal can be connected between these two pins. ing.
The OSCin pin is the input pin, the OSCout pin is
the output pin. PC2-PC4. These 3 lines are organized as one I/O
port (C). Each line may be configured under soft-
RESET. The active-low RESET pin is used to re- ware control as input with or without internal pull-
start the microcontroller. up resistor, interrupt generating input with pull-up
TEST/VPP. The TEST must be held at VSS for nor- resistor, analog input for the A/D converter, open-
mal operation. If TEST pin is connected to a drain or push-pull output.
+12.5V level during the reset phase, the EPROM/ PC2-PC4 can also be used as respectively Data
OTP programming Mode is entered. in, Data out and Clock I/O pins for the on-chip SPI
to carry the synchronous serial I/O signals.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non Figure 2ST62T53C/T60C/T63C/E60C Pin
maskable interrupt to the MCU. It is provided with Configuration
an on-chip pullup resistor (if option has been ena-
bled), and Schmitt trigger characteristics.
PA0-PA3. These 4 lines are organized as one I/O PB0 1 20 PC2 / Sin / Ain
port (A). Each line may be configured under soft- PB1 2 19 PC3 / Sout / Ain
ware control as inputs with or without internal pull- VPP/TEST 3 18 PC4 / Sck / Ain
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, ana- PB2 4 17 NMI
log inputs for the A/D converter. PB3 5 16 RESET
PB0-PB3. These 4 lines are organized as one I/O ARTIMin/PB6 6 15 OSCout
port (B). Each line may be configured under soft- ARTIMout/PB7 7 14 OSCin
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull- Ain/PA0 8 13 PA3/Ain
up resistors, open-drain or push-pull outputs. VDD 9 12 PA2/Ain
PB0-PB3 can also sink 30mA for direct LED VSS 10 11 PA1/Ain
driving.

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 ST62T53C/T60C/T63C ST62E60C

1.3 MEMORY MAP

1.3.1 Introduction Briefly, Program space contains user program
The MCU operates in three separate memory code in OTP and user vectors; Data space con-
spaces: Program space, Data space, and Stack tains user data in RAM and in OTP, and Stack
space. Operation in these three memory spaces is space accommodates six levels of stack for sub-
described in the following paragraphs. routine and interrupt service routine nesting.

Figure 3Memory Addressing Diagram

PROGRAM SPACE DATA SPACE

0000h 000h

RAM / EEPROM
BANKING AREA

0-63 03Fh
040h
DATA READ-ONLY
PROGRAM MEMORY WINDOW
MEMORY 07Fh
080h X REGISTER
081h Y REGISTER
082h V REGISTER
083h W REGISTER
084h
RAM

0C0h DATA READ-ONLY

MEMORY
0FF0h WINDOW SELECT
DATA RAM
INTERRUPT & BANK SELECT
RESET VECTORS
0FFFh 0FFh ACCUMULATOR

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP (Cont’d)

1.3.2 Program Space
Program Space comprises the instructions to be In the EPROM parts, READOUT PROTECTION
executed, the data required for immediate ad- option can be disactivated only by U.V. erasure
dressing mode instructions, the reserved factory that also results into the whole EPROM context
test area and the user vectors. Program Space is erasure.
addressed via the 12-bit Program Counter register Note: Once the Readout Protection is activated, it
(PC register). is no longer possible, even for STMicroelectronics,
1.3.2.1 Program Memory Protection to gain access to the OTP contents. Returned
The Program Memory in OTP or EPROM devices parts with a protection set can therefore not be ac-
can be protected against external readout of mem- cepted.
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
Figure 4ST62E60C/T60C Program Figure 5ST62T53C/T63C Program
Memory Map Memory Map
0000h
0000h
RESERVED*
007Fh
0080h

RESERVED*

087Fh
USER 0880h
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES

USER
PROGRAM MEMORY
(OTP)
1824 BYTES

0F9Fh
0F9Fh 0FA0h
0FA0h 0FEFh
RESERVED*
0FEFh RESERVED*
0FF0h
0FF0h 0FF7h INTERRUPT VECTORS
0FF7h INTERRUPT VECTORS
0FF8h
0FF8h RESERVED
RESERVED 0FFBh
0FFBh 0FFCh
0FFCh NMI VECTOR
NMI VECTOR 0FFDh
0FFDh 0FFEh
0FFEh USER RESET VECTOR
USER RESET VECTOR 0FFFh
0FFFh

(*) Reserved areas should be filled with 0FFh (*) Reserved areas should be filled with 0FFh

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 ST62T53C/T60C/T63C ST62E60C

MEMORY MAP (Cont’d)

1.3.3 Data Space Table 2ST62T53C, T60C, T63C and ST62E60C
Data Space accommodates all the data necessary Data Memory Space
for processing the user program. This space com- 000h
prises the RAM resource, the processor core and RAM and EEPROM
03Fh
peripheral registers, as well as read-only data 040h
such as constants and look-up tables in OTP/ DATA ROM WINDOW AREA
EPROM.
07Fh
1.3.3.1 Data ROM X REGISTER 080h
All read-only data is physically stored in program Y REGISTER 081h
V REGISTER 082h
memory, which also accommodates the Program
W REGISTER 083h
Space. The program memory consequently con-
084h
tains the program code to be executed, as well as DATA RAM 60 BYTES
0BFh
the constants and look-up tables required by the PORT A DATA REGISTER 0C0h
application. PORT B DATA REGISTER 0C1h
The Data Space locations in which the different PORT C DATA REGISTER 0C2h
constants and look-up tables are addressed by the RESERVED 0C3h
processor core may be thought of as a 64-byte PORT A DIRECTION REGISTER 0C4h
window through which it is possible to access the PORT B DIRECTION REGISTER 0C5h
PORT C DIRECTION REGISTER 0C6h
read-only data stored in OTP/EPROM.
RESERVED 0C7h
1.3.3.2 Data RAM/EEPROM INTERRUPT OPTION REGISTER 0C8h*
In ST62T53C, T60C, T63C and ST62E60C devic- DATA ROM WINDOW REGISTER 0C9h*
es, the data space includes 60 bytes of RAM, the 0CAh
RESERVED
0CBh
accumulator (A), the indirect registers (X), (Y), the
PORT A OPTION REGISTER 0CCh
short direct registers (V), (W), the I/O port regis-
PORT B OPTION REGISTER 0CDh
ters, the peripheral data and control registers, the PORT C OPTION REGISTER 0CEh
interrupt option register and the Data ROM Win- RESERVED 0CFh
dow register (DRW register). A/D DATA REGISTER 0D0h
Additional RAM and EEPROM pages can also be A/D CONTROL REGISTER 0D1h
addressed using banks of 64 bytes located be- TIMER PRESCALER REGISTER 0D2h
tween addresses 00h and 3Fh. TIMER COUNTER REGISTER 0D3h
TIMER STATUS CONTROL REGISTER 0D4h
AR TIMER MODE CONTROL REGISTER 0D5h
1.3.4 Stack Space
AR TIMER STATUS/CONTROL REGISTER1 0D6h
Stack space consists of six 12-bit registers which AR TIMER STATUS/CONTROL REGISTER2 0D7h
are used to stack subroutine and interrupt return WATCHDOG REGISTER 0D8h
addresses, as well as the current program counter AR TIMER RELOAD/CAPTURE REGISTER 0D9h
contents. AR TIMER COMPARE REGISTER 0DAh
AR TIMER LOAD REGISTER 0DBh
Table 1. Additional RAM/EEPROM Banks OSCILLATOR CONTROL REGISTER 0DCh*
MISCELLANEOUS 0DDh
Device RAM EEPROM 0DEh
RESERVED
0DFh
ST62T53C 1 x 64 bytes - SPI DATA REGISTER 0E0h
SPI DIVIDER REGISTER 0E1h
ST62T60C/E60C 1 x 64 bytes 2 x 64 bytes SPI MODE REGISTER 0E2h
0E3h
RESERVED
ST62T63C 1 x 64 bytes 1 x 64 bytes 0E7h
DATA RAM/EEPROM REGISTER 0E8h*
RESERVED 0E9h
EEPROM CONTROL REGISTER
0EAh
(except ST62T53C)
0EBh
RESERVED
0FEh
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR) Data Window Register (DWR)
The Data read-only memory window is located from Address: 0C9h — Write Only
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat- 7 0
ed anywhere in program memory, between ad-
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window Bits 6, 7 = Not used.
can be moved in steps of 64 bytes along the pro- Bit 5-0 = DWR6-DWR0: Data read-only memory
gram memory by writing the appropriate code in the Window Register Bits. These are the Data read-
Data Window Register (DWR). only memory Window bits that correspond to the
The DWR can be addressed like any RAM location upper bits of the data read-only memory space.
in the Data Space, it is however a write-only regis- Caution: This register is undefined on reset. Nei-
ter and therefore cannot be accessed using single- ther read nor single bit instructions may be used to
bit operations. This register is used to position the address this register.
64-byte read-only data window (from address 40h Note: Care is required when handling the DWR
to address 7Fh of the Data space) in program register as it is write only. For this reason, the
memory in 64-byte steps. The effective address of DWR contents should not be changed while exe-
the byte to be read as data in program memory is cuting an interrupt service routine, as the service
obtained by concatenating the 6 least significant routine cannot save and then restore the register’s
bits of the register address given in the instruction previous contents. If it is impossible to avoid writ-
(as least significant bits) and the content of the ing to the DWR during the interrupt service routine,
DWR register (as most significant bits), as illustrat- an image of the register must be saved in a RAM
ed in Figure 6 below. For instance, when address- location, and each time the program writes to the
ing location 0040h of the Data Space, with 0 load- DWR, it must also write to the image register. The
ed in the DWR register, the physical location ad- image register must be written first so that, if an in-
dressed in program memory is 00h. The DWR reg- terrupt occurs between the two instructions, the
ister is not cleared on reset, therefore it must be DWR is not affected.
written to prior to the first access to the Data read-
only memory window area.
Figure 6Data read-only memory Window Memory Addressing

DATA ROM 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAM SPACE ADDRESS

WINDOW REGISTER 7 READ
6 5 4 3 2 1 0
CONTENTS
5 4 3 2 1 0 DATA SPACE ADDRESS
(DWR) :
0 1 40h-7Fh
IN INSTRUCTION

Example:

DWR=28h 1 0 1 0 0 0
DATA SPACE ADDRESS
0 1 0 1 1 0 0 1 :
59h

ROM
1 0 1 0 0 0 0 1 1 0 0 1
ADDRESS:A19h
VR01573C

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 ST62T53C/T60C/T63C ST62E60C

MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register to the selected location as if it was in bank 0 (from
(DRBR) 00h address to 3Fh address).
Address: E8h — Write only This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
7 0 access to the Data Space bank region. Refer to
DRBR DRBR DRBR the Data Space description for additional informa-
- - - - -
4 1 0 tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Bit 7-5 = These bits are not used Notes :
Bit 4 - DRBR4. This bit, when set, selects RAM Care is required when handling the DRBR register
Page 2. as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
Bit 3-2 - Reserved. These bits are not used.
terrupt service routine, as the service routine can-
Bit 1 - DRBR1. This bit, when set, selects not save and then restore its previous content. If it
EEPROM Page 1, when available. is impossible to avoid the writing of this register in
Bit 0 - DRBR0. This bit, when set, selects interrupt service routine, an image of this register
EEPROM Page 0, when available. must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
The selection of the bank is made by programming the image register. The image register must be
the Data RAM Bank Switch register (DRBR regis- written first, so if an interrupt occurs between the
ter) located at address E8h of the Data Space ac- two instructions the DRBR is not affected.
cording to Table 1. No more than one bank should
be set at a time. In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
The DRBR register can be addressed like a RAM producing errors.
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with Care must also be taken not to change the
single-bit operations. This register is used to select E²PROM page (when available) when the parallel
the desired 64-byte RAM/EEPROM bank of the writing mode is set for the E²PROM, as defined in
Data Space. The bank number has to be loaded in EECTL register.
the DRBR register and the instruction has to point
Table 3Data RAM Bank Register Set-up
DRBR ST62T53C ST62T60C/E60C ST62T63C

00 None None None

01 Not Available EEPROM Page 0 EEPROM Page 0

02 Not Available EEPROM Page 1 Not Available

08 Not Available Not Available Not Available

10h RAM Page 2 RAM Page 2 RAM Page 2

other Reserved Reserved Reserved

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ST62T53C/T60C/T63C ST62E60C

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description (PMODE). In BMODE, one byte is accessed at a
EEPROM memory is located in 64-byte pages in time, while in PMODE up to 8 bytes in the same
data space. This memory may be used by the user row are programmed simultaneously (with conse-
program for non-volatile data storage. quent speed and power consumption advantages,
the latter being particularly important in battery
Data space from 00h to 3Fh is paged as described powered circuits).
in Table 4. EEPROM locations are accessed di-
rectly by addressing these paged sections of data General Notes:
space. Data should be written directly to the intended ad-
The EEPROM does not require dedicated instruc- dress in EEPROM space. There is no buffer mem-
tions for read or write access. Once selected via the ory between data RAM and the EEPROM space.
Data RAM Bank Register, the active EEPROM When the EEPROM is busy (E2BUSY = “1”)
page is controlled by the EEPROM Control Regis- EECTL cannot be accessed in write mode, it is
ter (EECTL), which is described below. only possible to read the status of E2BUSY. This
Bit E20FF of the EECTL register must be reset prior implies that as long as the EEPROM is busy, it is
to any write or read access to the EEPROM. If no not possible to change the status of the EEPROM
bank has been selected, or if E2OFF is set, any ac- Control Register. EECTL bits 4 and 5 are reserved
cess is meaningless. and must never be set.
Programming must be enabled by setting the Care is required when dealing with the EECTL reg-
E2ENA bit of the EECTL register. ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
The E2BUSY bit of the EECTL register is set when ecuting an interrupt service routine.
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set If it is impossible to avoid writing to this register
is meaningless. within an interrupt service routine, an image of the
register must be saved in a RAM location, and
Provided E2OFF and E2BUSY are reset, an EEP- each time the program writes to EECTL it must
ROM location is read just like any other data loca- also write to the image register. The image register
tion, also in terms of access time. must be written to first so that, if an interrupt oc-
Writing to the EEPROM may be carried out in two curs between the two instructions, the EECTL will
modes: Byte Mode (BMODE) and Parallel Mode not be affected.

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Dataspace
addresses.
Banks 0 and 1.
Byte 0 1 2 3 4 5 6 7
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest
power-consumption.

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MEMORY MAP (Cont’d)

Additional Notes on Parallel Mode: EEPROM Control Register (EECTL)
If the user wishes to perform parallel program- Address: EAh — Read/Write
ming, the first step should be to set the E2PAR2 Reset status: 00h
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address and the 7 0
data will be latched and it will be possible to
E2O E2PA E2PA E2BU E2E
change them only at the end of the programming D7
FF
D5 D4
R1 R2 SY NA
cycle or by resetting E2PAR2 without program-
ming the EEPROM. After the ROW address is
latched, the MCU can only “see” the selected Bit 7 = D7: Unused.
EEPROM row and any attempt to write or read Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.
other rows will produce errors. If this bit is set the EEPROM is disabled (any access
The EEPROM should not be read while E2PAR2 will be meaningless) and the power consumption of
is set. the EEPROM is reduced to its lowest value.
As soon as the E2PAR2 bit is set, the 8 volatile Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
ROW latches are cleared. From this moment on, Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.
the user can load data in all or in part of the ROW. Once in Parallel Mode, as soon as the user software
Setting E2PAR1 will modify the EEPROM regis- sets the E2PAR1 bit, parallel writing of the 8 adja-
ters corresponding to the ROW latches accessed cent registers will start. This bit is internally reset at
after E2PAR2. For example, if the software sets the end of the programming procedure. Note that
E2PAR2 and accesses the EEPROM by writing to less than 8 bytes can be written if required, the un-
addresses 18h, 1Ah and 1Bh, and then sets defined bytes being unaffected by the parallel pro-
E2PAR1, these three registers will be modified si- gramming cycle; this is explained in greater detail in
multaneously; the remaining bytes in the row will the Additional Notes on Parallel Mode overleaf.
be unaffected. Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
Note that E2PAR2 is internally reset at the end of ONLY. This bit must be set by the user program in
the programming cycle. This implies that the user order to perform parallel programming. If E2PAR2
must set the E2PAR2 bit between two parallel pro- is set and the parallel start bit (E2PAR1) is reset,
gramming cycles. Note that if the user tries to set up to 8 adjacent bytes can be written simultane-
E2PAR1 while E2PAR2 is not set, there will be no ously. These 8 adjacent bytes are considered as a
programming cycle and the E2PAR1 bit will be un- row, whose address lines A7, A6, A5, A4, A3 are
affected. Consequently, the E2PAR1 bit cannot be fixed while A2, A1 and A0 are the changing bits, as
set if E2ENA is low. The E2PAR1 bit can be set by illustrated in Table 4. E2PAR2 is automatically re-
the user, only if the E2ENA and E2PAR2 bits are set at the end of any parallel programming proce-
also set. dure. It can be reset by the user software before
Notes: The EEPROM page shall not be changed starting the programming procedure, thus leaving
through the DRBR register when the E2PAR2 bit the EEPROM registers unchanged.
is set. Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.
The EEPROM is disabled as soon as a STOP in-
struction is executed in order to achieve the lowest
power-consumption.

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ST62T53C/T60C/T63C ST62E60C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes voltage is too low. When this bit is cleared, only
The two Option Bytes allow configuration capabili- power-on reset or external RESET are active.
ty to the MCUs. Option byte’s content is automati- PROTECT. Readout Protection. This bit allows the
cally read, and the selected options enabled, when protection of the software contents against piracy.
the chip reset is activated. When the bit PROTECT is set high, readout of the
It can only be accessed during the programming OTP contents is prevented by hardware.. When
mode. This access is made either automatically this bit is low, the user program can be read.
(copy from a master device) or by selecting the EXTCNTL. External STOP MODE control.. When
OPTION BYTE PROGRAMMING mode of the pro- EXTCNTL is high, STOP mode is available with
grammer. watchdog active by setting NMI pin to one. When
The option bytes are located in a non-user map. EXTCNTL is low, STOP mode is not available with
No address has to be specified. the watchdog active.
PB2-3 PULL. When set this bit removes pull-up at
reset on PB2-PB3 pins. When cleared PB2-PB3
EPROM Code Option Byte (LSB) pins have an internal pull-up resistor at reset.
7 0 PB0-1 PULL. When set this bit removes pull-up at
reset on PB0-PB1 pins. When cleared PB0-PB1
PRO- EXTC- PB2-3 PB0-1 DE-
TECT NTL PULL PULL
WDACT
LAY
OSCIL OSGEN pins have an internal pull-up resistor at reset.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
EPROM Code Option Byte (MSB) The software activation is selected when WDACT
is low.
15 8 DELAY. This bit enables the selection of the delay
ADC NMI internally generated after the internal reset (exter-
- - - - - LVD
SYNCHRO PULL nal pin, LVD, or watchdog activated) is released.
When DELAY is low, the delay is 2048 cycles of
D15-D13. Reserved. Must be cleared. the oscillator, it is of 32768 cycles when DELAY is
high.
ADC SYNCHRO. When set, an A/D conversion is
started upon WAIT instruction execution, in order OSCIL. Oscillator selection. When this bit is low,
to reduce supply noise. When this bit is low, an A/ the oscillator must be controlled by a quartz crys-
D conversion is started as soon as the STA bit of tal, a ceramic resonator or an external frequency.
the A/D Converter Control Register is set. When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
D11. Reserved, must be set to one.
externally provided.
D10. Reserved, must be cleared.
OSGEN. Oscillator Safe Guard. This bit must be
NMI PULL. NMI Pull-Up. This bit must be set high set high to enable the Oscillator Safe Guard.
to configure the NMI pin with a pull-up resistor. When this bit is low, the OSG is disabled.
When it is low, no pull-up is provided.
The Option byte is written during programming ei-
LVD. LVD RESET enable.When this bit is set, safe ther by using the PC menu (PC driven Mode) or
RESET is performed by MCU when the supply automatically (stand-alone mode).

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 ST62T53C/T60C/T63C ST62E60C

PROGRAMMING MODES (Cont’d)

1.4.2 EPROM Erasing prevent unintentional erasure problems when test-
The EPROM of the windowed package of the ing the application in such an environment.
MCUs may be erased by exposure to Ultra Violet The recommended erasure procedure of the
light. The erasure characteristic of the MCUs is MCUs EPROM is the exposure to short wave ul-
such that erasure begins when the memory is ex- traviolet light which have a wave-length 2537A.
posed to light with a wave lengths shorter than ap- The integrated dose (i.e. U.V. intensity x exposure
proximately 4000Å. It should be noted that sun- time) for erasure should be a minimum of 15W-
lights and some types of fluorescent lamps have sec/cm2. The erasure time with this dosage is ap-
wavelengths in the range 3000-4000Å. proximately 15 to 20 minutes using an ultraviolet
It is thus recommended that the window of the lamp with 12000µW/cm2 power rating. The
MCUs packages be covered by an opaque label to ST62E60C should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.

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ST62T53C/T60C/T63C ST62E60C

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the Indirect Registers (X, Y). These two indirect reg-
I/O or Memory configuration. As such, it may be isters are used as pointers to memory locations in
thought of as an independent central processor Data space. They are used in the register-indirect
communicating with on-chip I/O, Memory and Pe- addressing mode. These registers can be ad-
ripherals via internal address, data, and control dressed in the data space as RAM locations at ad-
buses. In-core communication is arranged as dresses 80h (X) and 81h (Y). They can also be ac-
shown in Figure 7; the controller being externally cessed with the direct, short direct, or bit direct ad-
linked to both the Reset and Oscillator circuits, dressing modes. Accordingly, the ST6 instruction
while the core is linked to the dedicated on-chip pe- set can use the indirect registers as any other reg-
ripherals via the serial data bus and indirectly, for ister of the data space.
interrupt purposes, through the control registers. Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
2.2 CPU REGISTERS dressing mode. They can be addressed in Data
The ST6 Family CPU core features six registers and space as RAM locations at addresses 82h (V) and
three pairs of flags available to the programmer. 83h (W). They can also be accessed using the di-
These are described in the following paragraphs. rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
Accumulator (A). The accumulator is an 8-bit ters as any other register of the data space.
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula- Program Counter (PC). The program counter is a
tions. The accumulator can be addressed in Data 12-bit register which contains the address of the
next ROM location to be processed by the core.
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any This ROM location may be an opcode, an oper-
other register in Data space. and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 7. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin OSCout

INTERRUPTS
CONTROLLER
DATA SPACE

CONTROL
FLAG SIGNALS DATA
OPCODE VALUES ADDRESS/READ LINE
2 RAM/EEPROM

PROGRAM
DATA
ROM/EPROM ADDRESS 256
DECODER ROM/EPROM

A-DATA B-DATA
DEDICATIONS

ACCUMULATOR
Program Counter
12 and FLAGS
6 LAYER STACK ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811

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 ST62T53C/T60C/T63C ST62E60C

CPU REGISTERS (Cont’d)

However, if the program space contains more than automatically selected after the reset of the MCU,
4096 bytes, the additional memory in program the ST6 core uses at first the NMI flags.
space can be addressed by using the Program Stack. The ST6 CPU includes a true LIFO hard-
Bank Switch register. ware stack which eliminates the need for a stack
The PC value is incremented after reading the ad- pointer. The stack consists of six separate 12-bit
dress of the current instruction. To execute relative RAM locations that do not belong to the data
jumps, the PC and the offset are shifted through space RAM area. When a subroutine call (or inter-
the ALU, where they are added; the result is then rupt request) occurs, the contents of each level are
shifted back into the PC. The program counter can shifted into the next higher level, while the content
be changed in the following ways: of the PC is shifted into the first level (the original
- JP (Jump) instructionPC=Jump address contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
- CALL instructionPC= Call address instructions), the first level register is shifted back
- Relative Branch Instruction.PC= PC +/- offset into the PC and the value of each level is popped
- Interrupt PC=Interrupt vector back into the previous level. Since the accumula-
tor, in common with all other data space registers,
- Reset PC= Reset vector is not stored in this stack, management of these
- RET & RETI instructionsPC= Pop (stack) registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
- Normal instructionPC= PC + 1 if more than 6 nested calls or interrupts are execut-
Flags (C, Z). The ST6 CPU includes three pairs of ed, and consequently the last return address will
flags (Carry and Zero), each pair being associated be lost. It will also remain in its highest position if
with one of the three normal modes of operation: the stack is empty and a RET or RETI is executed.
Normal mode, Interrupt mode and Non Maskable In this case the next instruction will be executed.
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used lFigure 8. ST6 CPU Programming Mode
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
b7 X REG. POINTER b0
in the Non Maskable Interrupt mode (CNMI, ZN- INDEX SHORT
MI). REGISTER DIRECT
b7 Y REG. POINTER b0
ADDRESSING
The ST6 CPU uses the pair of flags associated MODE
b7 V REGISTER b0
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6 b7 W REGISTER b0
CPU uses the Interrupt flags (resp. the NMI flags) b7 ACCUM ULATOR b0
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
b11 PROGRAM COUNTER b0
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status. SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
NORMAL FLAGS C Z
pates in the rotate left instruction.
The Zero flag is set if the result of the last arithme- INTERRUPT FLAGS C Z
tic or logical operation was equal to zero; other-
wise it is cleared. NMI FLAGS C Z
Switching between the three sets of flags is per- VA000423
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is

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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be Figure 9. Oscillator Configurations
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita- CRYSTAL/RESONATOR CLOCK
ble ceramic resonator, or with an external resistor CRYSTAL/RESONATOR option
(RNET). In addition, a Low Frequency Auxiliary Os-
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the ST6xxx
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters OSCin OSCout
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
cally limits the internal clock frequency (f INT) as a
function of VDD, in order to guarantee correct oper- CL1n CL2
ation. These functions are illustrated in Figure 10,
Figure 11, Figure 12 and Figure 13.
A programmable divider on F INT is also provided in EXTERNAL CLOCK
order to adjust the internal clock of the MCU to the CRYSTAL/RESONATOR option
best power consumption and performance trade-
off.
ST6xxx
Figure 9 illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor OSCin OSCout
(RNET), or the lowest cost solution using only the
LFAO. CL1 an CL2 should have a capacitance in the NC
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU clock frequency (fINT) is divided RC NETWORK
RC NETWORK option
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 12. ST6xxx
With an 8 MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs. OSCin OSCout
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment NC
the Program Counter). An instruction may require RNET
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
INTEGRATED CLOCK
lecting the appropriate option. When the CRYSTAL/ CRYSTAL/RESONATOR option
RESONATOR option is selected, it must be used with OSG ENABLED option
a quartz crystal, a ceramic resonator or an external
signal provided on the OSCin pin. When the RC NET-
WORK option is selected, the system clock is gen- ST6xxx
erated by an external resistor.
The main oscillator can be turned off (when the OSCin OSCout
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The NC
Low Frequency Auxiliary Oscillator is automatical-
ly started.

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 ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d)

Turning on the main oscillator is achieved by re- tions: it filters spikes from the oscillator lines which
setting the OSCOFF bit of the A/D Converter Con- would result in over frequency to the ST62 CPU; it
trol Register or by resetting the MCU. Restarting gives access to the Low Frequency Auxiliary Os-
the main oscillator implies a delay comprising the cillator (LFAO), used to ensure minimum process-
oscillator start up delay period plus the duration of ing in case of main oscillator failure, to offer re-
the software instruction at fLFAO clock frequency. duced power consumption or to provide a fixed fre-
3.1.2 Low Frequency Auxiliary Oscillator quency low cost oscillator; finally, it automatically
(LFAO) limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
The Low Frequency Auxiliary Oscillator has three tion even if the power supply should drop.
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines. The OSG is enabled or disabled by choosing the
Secondly, it offers a fully integrated system clock, relevant OSG option. It may be viewed as a filter
without any external components. Lastly, it acts as whose cross-over frequency is device dependent.
a safety oscillator in case of main oscillator failure. Spikes on the oscillator lines result in an effectively
This oscillator is available when the OSG ENA- increased internal clock frequency. In the absence
BLED option is selected. In this case, it automati- of an OSG circuit, this may lead to an over fre-
cally starts one of its periods after the first missing quency for a given power supply voltage. The
edge from the main oscillator, whatever the reason OSG filters out such spikes (as illustrated in Figure
(main oscillator defective, no clock circuitry provid- 10). In all cases, when the OSG is active, the max-
ed, main oscillator switched off...). imum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent. This re-
User code, normal interrupts, WAIT and STOP in- lationship is illustrated in Figure 13.
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura- When the OSG is enabled, the Low Frequency
cy is decreased, since the internal frequency is be- Auxiliary Oscillator may be accessed. This oscilla-
low 1MHz. tor starts operating after the first missing edge of
the main oscillator (see Figure 11).
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there- Over-frequency, at a given power supply level, is
fore feeds the on-chip counter generating the POR seen by the OSG as spikes; it therefore filters out
delay until the Main Oscillator runs. some cycles in order that the internal clock fre-
quency of the device is kept within the range the
The Low Frequency Auxiliary Oscillator is auto- particular device can stand (depending on VDD),
matically switched off as soon as the main oscilla- and below fOSG: the maximum authorised frequen-
tor starts. cy with OSG enabled.
ADCR Note. The OSG should be used wherever possible
Address: 0D1h — Read/Write as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
7 0 tion and reduce the maximum operating frequency
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR to fOSG.
7 6 5 4 3 OFF 1 0 Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0: a minimum and a maximum value and is not accu-
ADC Control Register. These bits are reserved for rate.
ADC Control.
For precise timing measurements, it is not recom-
Bit 2 = OSCOFF. When low, this bit enables main mended to use the OSG and it should not be ena-
oscillator to run. The main oscillator is switched off bled in applications that use the SPI or the UART.
when OSCOFF is high.
It should also be noted that power consumption in
3.1.3 Oscillator Safe Guard Stop mode is higher when the OSG is enabled
The Oscillator Safe Guard (OSG) affords drastical- (around 50µA at nominal conditions and room
ly increased operational integrity in ST62xx devic- temperature).
es. The OSG circuit provides three basic func-

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ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d)

Figure 10. OSG Filtering Principle

(1)

(2)

(3)

(4)

(1) Maximum Frequency for the device to work correctly

(2) Actual Quartz Crystal Frequency at OSCin pin
(3) Noise from OSCin
(4) Resulting Internal Frequency VR001932

Figure 11. OSG Emergency Oscillator Principle

Main
Oscillator

Emergency
Oscillator

Internal
Frequency

VR001933

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 ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d)

Oscillator Control Registers RS1 RS0 Division Ratio
Address: DCh — Write only 0 0 1
0 1 2
Reset State: 00h
1 0 4
7 0 1 1 4
OSCR
- - - -
3
- RS1 RS0 Note: Care is required when handling the OSCR
register as some bits are write only. For this rea-
son, it is not allowed to change the OSCR contents
Bit 7-4. These bits are not used.
while executing interrupt service routine, as the
Bit 3. Reserved. Cleared at Reset. Must be kept service routine cannot save and then restore its
cleared. previous content. If it is impossible to avoid the
Bit 2. Reserved. Must be kept low. writing of this register in interrupt service routine,
an image of this register must be saved in a RAM
RS1-RS0. These bits select the division ratio of location, and each time the program writes to
the Oscillator Divider in order to generate the inter- OSCR it must write also to the image register. The
nal frequency. The following selctions are availa- image register must be written first, so if an inter-
ble: rupt occurs between the two instructions the
OSCR is not affected.

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ST62T53C/T60C/T63C ST62E60C

CLOCK SYSTEM (Cont’d)

Figure 12. Clock Circuit Block Diagram

POR

: 13 Core
OSG

TIMER 1

M OSCILLATOR
MAIN fINT Watchdog
OSCILLATOR U DIVIDER : 12
X RS0,RS1

LFAO

:1

Main Oscillator off

Figure 13. Maximum Operating Frequency (fMAX) versus Supply Voltage (V DD)

Maximum FREQUENCY (MHz)

7 4
FUNCTIONALITY IS NOT

3
6
fOSG
GUARANTEED
IN THIS AREA

5
fOSG Min (at 85°C)
4 2

3
fOSG Min (at 125°C)
2
1
1
2.5 3 3.6 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD )

VR01807J

Notes:
1. In this area, operation is guaranteed at the area is guaranteed at the quartz crystal frequency.
quartz crystal frequency. When the OSG is enabled, access to this area is
2. When the OSG is disabled, operation in this prevented. The internal frequency is kept a fOSG.
area is guaranteed at the crystal frequency. When 4. When the OSG is disabled, operation in this
the OSG is enabled, operation in this area is guar- area is not guaranteed
anteed at a frequency of at least fOSG Min. When the OSG is enabled, access to this area is
3. When the OSG is disabled, operation in this prevented. The internal frequency is kept at fOSG.

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 ST62T53C/T60C/T63C ST62E60C

3.2 RESETS
The MCU can be reset in four ways: is executed immediately following the internal de-
– by the external Reset input being pulled low; lay.
– by Power-on Reset; To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
– by the digital Watchdog peripheral timing out. cient level for the chosen frequency (see recom-
– by Low Voltage Detection (LVD) mended operation) before the reset signal is re-
3.2.1 RESET Input leased. In addition, supply rising must start from
0V.
The RESET pin may be connected to a device of
the application board in order to reset the MCU if As a consequence, the POR does not allow to su-
required. The RESET pin may be pulled low in pervise static, slowly rising, or falling, or noisy
RUN, WAIT or STOP mode. This input can be (presenting oscillation) VDD supplies.
used to reset the MCU internal state and ensure a An external RC network connected to the RESET
correct start-up procedure. The pin is active low pin, or the LVD reset can be used instead to get
and features a Schmitt trigger input. The internal the best performances.
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on Figure 14. Reset and Interrupt Processing
the RESET pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is RESET
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
NMI MASK SET
If RESET activation occurs in the RUN or WAIT INT LATCH CLEARED
( IF PRESENT )
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the SELECT
NMI MODE FLAGS
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
If RESET pin activation occurs in the STOP mode, PUT FFEH
ON ADDRESS BUS
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period. YES
IS RESET STILL
3.2.2 Power-on Reset PRESENT?

The function of the POR circuit consists in waking

up the MCU by detecting around 2V a dynamic NO
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured LOAD PC
FROM RESET LOCATIONS
in the Reset state: all I/O ports are configured as FFE/FFF
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to FETCH INSTRUCTION
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence VA000427

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ST62T53C/T60C/T63C ST62E60C

RESETS (Cont’d)
3.2.3 Watchdog Reset ues, allowing hysteresis effect. Reference value in
The MCU provides a Watchdog timer function in case of voltage drop has been set lower than the
order to ensure graceful recovery from software reference value for power-on in order to avoid any
upsets. If the Watchdog register is not refreshed parasitic Reset when MCU start's running and
before an end-of-count condition is reached, the sinking current on the supply.
internal reset will be activated. This, amongst oth- As long as the supply voltage is below the refer-
er things, resets the watchdog counter. ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
The MCU restarts just as though the Reset had ply voltage rises over the reference value. There-
been generated by the RESET pin, including the fore, only two operating mode exist for the MCU:
built-in stabilisation delay period. RESET active below the voltage reference, and
3.2.4 LVD Reset running mode over the voltage reference as
shown on the Figure 15, that represents a power-
The on-chip Low Voltage Detector, selectable as up, power-down sequence.
user option, features static Reset when supply
voltage is below a reference value. Thanks to this Note: When the RESET state is controlled by one
feature, external reset circuit can be removed of the internal RESET sources (Low Voltage De-
while keeping the application safety. This SAFE tector, Watchdog, Power on Reset), the RESET
RESET is effective as well in Power-on phase as pin is tied to low logic level.
in power supply drop with different reference val-
Figure 15. LVD Reset on Power-on and Power-down (Brown-out)

VDD

VUp

Vdn

RESET
RESET

time
VR02106A

3.2.5 Application Notes

No external resistor is required between VDD and Direct external connection of the pin RESET to
the Reset pin, thanks to the built-in pull-up device. VDD must be avoided in order to ensure safe be-
haviour of the internal reset sources (AND.Wired
structure).

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 ST62T53C/T60C/T63C ST62E60C

RESETS (Cont’d)
3.2.6 MCU Initialization Sequence Figure 16. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
RESET
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In- JP JP:2 BYTES/4 CYCLES
terrupt flag is automatically set, so that the CPU is RESET
in Non Maskable Interrupt mode; this prevents the VECTOR

initialisation routine from being interrupted. The in-

itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the INITIALIZATION
MCU will continue by processing the instruction ROUTINE RETI: 1 BYTE/2 CYCLES
immediately following the RETI instruction. If, how- RETI
ever, a pending interrupt is present, it will be serv-
iced. VA00181

Figure 17. Reset Block Diagram

VDD
ST6
fOSC CK INTERNAL
RESET

RPU COUNTER
AND. Wired
RESD1)
RESET RESET
RESET

POWER ON RESET
WATCHDOG RESET
LVD RESET

VR02107A

1) Resistive ESD protection. Value not guaranteed.

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ST62T53C/T60C/T63C ST62E60C

RESETS (Cont’d)
Table 5Register Reset Status
Register Address(es) Status Comment

Oscillator Control Register 00h

0DCh
EEPROM Control Register 00h EEPROM disabled (if available)
0EAh
Port Data Registers 00h I/O are Input with pull-up
0C0h to 0C2h
Port Direction Register 00h I/O are Input with pull-up
0C4h to 0C6h
Port Option Register 00h I/O are Input with pull-up
0CCh to 0CEh
Interrupt Option Register 00h Interrupt disabled
0C8h
TIMER Status/Control 00h TIMER disabled
0D4h

AR TIMER Mode Control Register 00h AR TIMER stopped

0D5h
AR TIMER Status/Control 0 Register 00h
0D6h
AR TIMER Status/Control 1 Register 00h
0D7h
AR TIMER Compare Register 00h

0DDh
Miscellaneous Register 00h SPI Output not connected to PC3
0E0h to 0E2h
SPI Registers 00h SPI disabled
0E1h
SPI DIV Register 00h SPI disabled
0E2h
SPI MOD Register 00h SPI disabled
0E0h
SPI DSR Register Undefined SPI disabled

X, Y, V, W, Register 080H TO 083H

Accumulator 0FFh
Data RAM 084h to 0BFh
Data RAM Page REgister 0E8h
Data ROM Window Register 0C9h Undefined
EEPROM 00h to 03Fh As written if programmed
A/D Result Register 0D0h
AR TIMER Load Register 0DBh
AR TIMER Reload/Capture Register 0D9h

TIMER Counter Register 0D3h FFh

TIMER Prescaler Register 0D2h 7Fh Max count loaded
Watchdog Counter Register 0D8h FEh
A/D Control Register 0D1h 40h A/D in Standby

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 ST62T53C/T60C/T63C ST62E60C

3.3 DIGITAL WATCHDOG

The digital Watchdog consists of a reloadable When the Watchdog is disabled, low power Stop
downcounter timer which can be used to provide mode is available. Once activated, the Watchdog
controlled recovery from software upsets. cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the In the HARDWARE option, the Watchdog is per-
downcounter reaches zero. User software can manently enabled. Since the oscillator will run con-
prevent this reset by reloading the counter, and tinuously, low power mode is not available. The
should therefore be written so that the counter is STOP instruction is interpreted as a WAIT instruc-
regularly reloaded while the user program runs tion, and the Watchdog continues to countdown.
correctly. In the event of a software mishap (usual- However, when the EXTERNAL STOP MODE
ly caused by externally generated interference), CONTROL option has been selected low power
the user program will no longer behave in its usual consumption may be achieved in Stop Mode.
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will Execution of the STOP instruction is then gov-
decrement down to 00h and reset the MCU. In or- erned by a secondary function associated with the
der to maximise the effectiveness of the Watchdog NMI pin. If a STOP instruction is encountered
function, user software must be written with this when the NMI pin is low, it is interpreted as WAIT,
concept in mind. as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
Watchdog behaviour is governed by two options, the Watchdog counter is frozen and the CPU en-
known as “WATCHDOG ACTIVATION” (i.e. ters STOP mode.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6). When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
In the SOFTWARE option, the Watchdog is disa- activity.
bled until bit C of the DWDR register has been set.

Table 6. Recommended Option Choices

Functions Required Recommended Options
Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”

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ST62T53C/T60C/T63C ST62E60C

DIGITAL WATCHDOG (Cont’d)

The Watchdog is associated with a Data space Figure 18. Watchdog Counter Control
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the D0 C
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the D1 SR

WATCHDOG CONTROL REGISTER

user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR

WATCHDOG COUNTER
RESET
bit must be set to “1”, since it is this bit which gen- D2 T5
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set. D3 T4
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the D4 T3
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to D5 T2
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch- D6 T1
dog timer downcounter is illustrated in Figure 18.
Only the 6 most significant bits may be used to de- D7 T0
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator ÷28 OSC ÷12
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384 µs to 24.576ms). VR02068A

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 ST62T53C/T60C/T63C ST62E60C

DIGITAL WATCHDOG (Cont’d)

3.3.1 Digital Watchdog Register (DWDR) 3.3.2 Application Notes
Address: 0D8h — Read/Write The Watchdog plays an important supporting role
Reset status: 1111 1110 b in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
7 0 lated options should be selected on the basis of a
trade-off between application security and STOP
T0 T1 T2 T3 T4 T5 SR C mode availability.
When STOP mode is not required, hardware acti-
Bit 0 = C: Watchdog Control bit vation without EXTERNAL STOP MODE CON-
If the hardware option is selected, this bit is forced TROL should be preferred, as it provides maxi-
high and the user cannot change it (the Watchdog mum security, especially during power-on.
is always active). When the software option is se- When STOP mode is required, hardware activa-
lected, the Watchdog function is activated by set- tion and EXTERNAL STOP MODE CONTROL
ting bit C to 1, and cannot then be disabled (save should be chosen. NMI should be high by default,
by resetting the MCU). to allow STOP mode to be entered when the MCU
When C is kept low the counter can be used as a is idle.
7-bit timer. The NMI pin can be connected to an I/O line (see
This bit is cleared to “0” on Reset. Figure 19) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
Bit 1 = SR: Software Reset bit low while Watchdog protection is required, or to
This bit triggers a Reset when cleared. avoid noise or key bounce. When no more
processing is required, the I/O line is released and
When C = “0” (Watchdog disabled) it is the MSB of the device placed in STOP mode for lowest power
the 7-bit timer. consumption.
This bit is set to “1” on Reset. When software activation is selected and the
Bits 2-7 = T5-T0: Downcounter bits Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
It should be noted that the register bits are re-
bits are in reverse order).
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog The software activation option should be chosen
downcounter and bit-2 (T5) is the MSB. only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
These bits are set to “1” on Reset.
expectedly activated, the following instructions
should be executed within the first 27 instructions:
jrr 0, WD, #+3
ldi WD, 0FDH

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ST62T53C/T60C/T63C ST62E60C

DIGITAL WATCHDOG (Cont’d)

These instructions test the C bit and Reset the Figure 19. A typical circuit making use of the
MCU (i.e. disable the Watchdog) if the bit is set EXERNAL STOP MODE CONTROL feature
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
SWITCH
generate a Reset. Consequently, user software
should load the watchdog counter within the first NMI
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.

VR02002

Figure 20. Digital Watchdog Block Diagram

RESET

Q 7
RSFF -2 -2 8 -12
S R DB1.7 LOAD SET SET

OSCILLATOR
8 CLOCK
DB0

WRITE
RESET
DATA BUS
VA00010

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 ST62T53C/T60C/T63C ST62E60C

3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt ically reset by the core at the beginning of the non-
sources, in addition to a Non Maskable Interrupt maskable interrupt service routine.
source (top priority interrupt). Each source is asso- Interrupt request from source #1 can be config-
ciated with a specific Interrupt Vector which con- ured either as edge or level sensitive by setting ac-
tains a Jump instruction to the associated interrupt cordingly the LES bit of the Interrupt Option Regis-
service routine. These vectors are located in Pro- ter (IOR).
gram space (see Table 7).
Interrupt request from source #2 are always edge
When an interrupt source generates an interrupt sensitive. The edge polarity can be configured by
request, and interrupt processing is enabled, the setting accordingly the ESB bit of the Interrupt Op-
PC register is loaded with the address of the inter- tion Register (IOR).
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv- Interrupt request from sources #3 & #4 are level
ice routine, thus servicing the interrupt. sensitive.
Interrupt sources are linked to events either on ex- In edge sensitive mode, a latch is set when a edge
ternal pins, or on chip peripherals. Several events occurs on the interrupt source line and is cleared
can be ORed on the same interrupt source, and when the associated interrupt routine is started.
relevant flags are available to determine which So, the occurrence of an interrupt can be stored,
event triggered the interrupt. until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
The Non Maskable Interrupt request has the high- occurs before completion of the running interrupt
est priority and can interrupt any interrupt routine routine, only the first request is stored.
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request Storage of interrupt requests is not available in lev-
is pending, these are processed by the processor el sensitive mode. To be taken into account, the
core according to their priority level: source #1 has low level must be present on the interrupt pin when
the higher priority while source #4 the lower. The the MCU samples the line after instruction execu-
priority of each interrupt source is fixed. tion.
At the end of every instruction, the MCU tests the
Table 7. Interrupt Vector Map interrupt lines: if there is an interrupt request the
Interrupt Source Priority Vector Address next instruction is not executed and the appropri-
Interrupt source #0 1 (FFCh-FFDh)
ate interrupt service routine is executed instead.
Interrupt source #1 2 (FF6h-FF7h) Table 8. Interrupt Option Register Description
Interrupt source #2 3 (FF4h-FF5h)
SET Enable all interrupts
Interrupt source #3 4 (FF2h-FF3h) GEN
CLEARED Disable all interrupts
Interrupt source #4 5 (FF0h-FF1h)
Rising edge mode on inter-
SET
rupt source #2
3.4.1 Interrupt request ESB
Falling edge mode on inter-
CLEARED
All interrupt sources but the Non Maskable Inter- rupt source #2
rupt source can be disabled by setting accordingly Level-sensitive mode on in-
SET
the GEN bit of the Interrupt Option Register (IOR). terrupt source #1
This GEN bit also defines if an interrupt source, in- LES
Falling edge mode on inter-
cluding the Non Maskable Interrupt source, can re- CLEARED
rupt source #1
start the MCU from STOP/WAIT modes. OTHERS NOT USED
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-

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ST62T53C/T60C/T63C ST62E60C

INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure MCU
The interrupt procedure is very similar to a call pro- – Automatically the MCU switches back to the nor-
cedure, indeed the user can consider the interrupt mal flag set (or the interrupt flag set) and pops
as an asynchronous call procedure. As this is an the previous PC value from the stack.
asynchronous event, the user cannot know the The interrupt routine usually begins by the identify-
context and the time at which it occurred. As a re- ing the device which generated the interrupt re-
sult, the user should save all Data space registers quest (by polling). The user should save the regis-
which may be used within the interrupt routines. ters which are used within the interrupt routine in a
There are separate sets of processor flags for nor- software stack. After the RETI instruction is exe-
mal, interrupt and non-maskable interrupt modes, cuted, the MCU returns to the main routine.
which are automatically switched and so do not
need to be saved. Figure 21. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce- INSTRUCTION
dure:
MCU
FETCH
– The interrupt is detected. INSTRUCTION

– The C and Z flags are replaced by the interrupt

flags (or by the NMI flags).
EXECUTE
– The PC contents are stored in the first level of INSTRUCTION
the stack.
– The normal interrupt lines are inhibited (NMI still LOAD PC FROM
active). WAS
NO INTERRUPT VECTOR
THE INSTRUCTION (FFC/FFD)
– The first internal latch is cleared. A RETI ?

– The associated interrupt vector is loaded in the PC. YES

WARNING: In some circumstances, when a YES

IS THE CORE
ALREADY IN
SET
INTERRUPT MASK
?
maskable interrupt occurs while the ST6 core is in NORMAL MODE?

NORMAL mode and especially during the execu- NO

tion of an "ldi IOR, 00h" instruction (disabling all CLEAR PUSH THE
maskable interrupts): if the interrupt arrives during INTERRUPT MASK
PC INTO THE STACK
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to SELECT
PROGRAM FLAGS
SELECT
the interrupt pair CI and ZI. INTERNAL MODE FLAG

User
– User selected registers are saved within the in- "POP"
THE STACKED PC
terrupt service routine (normally on a software
stack).
– The source of the interrupt is found by polling the NO CHECK IF THERE IS
? AN INTERRUPT REQUEST
interrupt flags (if more than one source is associ- AND INTERRUPT MASK

ated with the same vector). YES

VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)

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INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR) Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en- The bit ESB selects the polarity of the interrupt
able/disable the individual interrupt sources and to source #2.
select the operating mode of the external interrupt Bit 4 = GEN: Global Enable Interrupt . When this bit
inputs. This register is write-only and cannot be is set to one, all interrupts are enabled. When this
accessed by single-bit operations. bit is cleared to zero all the interrupts (excluding
Address: 0C8h — Write Only NMI) are disabled.
Reset status: 00h When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
7 0 modes.
- LES ESB GEN - - - - This register is cleared on reset.
3.4.4 Interrupt sources
Bit 7, Bits 3-0 = Unused . Interrupt sources available on these MCUs are
summarized in the Table 9 with associated mask
Bit 6 = LES: Level/Edge Selection bit. bit to enable/disable the interrupt request.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 9Interrupt Requests and Mask Bits
Address Interrupt
Peripheral Register Mask bit Masked Interrupt Source
Register vector
GENERAL IOR C8h GEN All Interrupts, excluding NMI
TIMER TSCR1 D4h ETI TMZ: TIMER Overflow Vector 4
A/D CONVERTER ADCR D1h EAI EOC: End of Conversion Vector 4
OVIE OVF: AR TIMER Overflow
AR TIMER ARMC D5h CPIE CPF: Successful compare Vector 3
EIE EF: Active edge on ARTIMin
SPI SPIMOD E2h SPIE SPRUN: End of Transmission Vector 2
Port PAn ORPA-DRPA C0h-C4h ORPAn-DRPAn PAn pin Vector 1
Port PBn ORPB-DRPB C1h-C5h ORPBn-DRPBn PBn pin Vector 1
Port PCn ORPC-DRPC C2h-C6h ORPCn-DRPCn PCn pin Vector 2

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INTERRUPTS (Cont’d)
Figure 22. Interrupt Block Diagram

FROM REGISTER PORT A,B,C

SINGLE BIT ENABLE

PBE

V DD

PORT A FF
CLK Q 0
PORT B PBE
CLR
Bits
INT #1 (FF6,7)
I Start MUX
1

RESTART FROM
IOR REG. C8H, bit 6 STOP/WAIT

PORT C FF
PBE CLK Q INT #2 (FF4,5)
Bits
CLR
SPIDIV Register
I Start
SPINT bit 2
IOR REG. C8H, bit 5
SPIE bit
OVF
SPIMOD Register OVIE
CPF INT #3 (FF2,3)
AR TIMER
CPIE
EF
EIE
TMZ
TIMER1 INT #4 (FF0,1)
VDD ETI
EOC
ADC EAI

FF NMI (FFC,D)
NMI CLK Q
CLR

I0 Start

Bit GEN (IOR Register)

VA0426K

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 ST62T53C/T60C/T63C ST62E60C

3.5 POWER SAVING MODES

The WAIT and STOP modes have been imple- of the processor core prior to the WAIT instruction,
mented in the ST62xx family of MCUs in order to but also on the kind of interrupt request which is
reduce the product’s electrical consumption during generated. This is described in the following para-
idle periods. These two power saving modes are graphs. The processor core does not generate a
described in the following paragraphs. delay following the occurrence of the interrupt, be-
3.5.1 WAIT Mode cause the oscillator clock is still available and no
stabilisation period is necessary.
The MCU goes into WAIT mode as soon as the 3.5.2 STOP Mode
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen” If the Watchdog is disabled, STOP mode is availa-
state where the core stops processing the pro- ble. When in STOP mode, the MCU is placed in
gram instructions, the RAM contents and peripher- the lowest power consumption mode. In this oper-
al registers are preserved as long as the power ating mode, the microcontroller can be considered
supply voltage is higher than the RAM retention as being “frozen”, no instruction is executed, the
voltage. In this mode the peripherals are still ac- oscillator is stopped, the RAM contents and pe-
tive. ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
WAIT mode can be used when the user wants to tention voltage, and the ST62xx core waits for the
reduce the MCU power consumption during idle occurrence of an external interrupt request or a
periods, while not losing track of time or the capa- Reset to exit the STOP state.
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock If the STOP state is exited due to a Reset (by acti-
signal to the peripherals. Timer counting may be vating the external pin) the MCU will enter a nor-
enabled as well as the Timer interrupt, before en- mal reset procedure. Behaviour in response to in-
tering the WAIT mode: this allows the WAIT mode terrupts depends on the state of the processor
to be exited when a Timer interrupt occurs. The core prior to issuing the STOP instruction, and
same applies to other peripherals which use the also on the kind of interrupt request that is gener-
clock signal. ated.
If the WAIT mode is exited due to a Reset (either This case will be described in the following para-
by activating the external pin or generated by the graphs. The processor core generates a delay af-
Watchdog), the MCU enters a normal reset proce- ter occurrence of the interrupt request, in order to
dure. If an interrupt is generated during WAIT wait for complete stabilisation of the oscillator, be-
mode, the MCU’s behaviour depends on the state fore executing the first instruction.

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ST62T53C/T60C/T63C ST62E60C

POWER SAVING MODE (Cont’d)

3.5.3 Exit from WAIT and STOP Modes tered will be completed, starting with the
execution of the instruction which follows the
The following paragraphs describe how the MCU STOP or the WAIT instruction, and the MCU is
exits from WAIT and STOP modes, when an inter- still in the interrupt mode. At the end of this rou-
rupt occurs (not a Reset). It should be noted that tine pending interrupts will be serviced in accord-
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in- ance with their priority.
terrupt mode) prior to entering WAIT or STOP – In the event of a non-maskable interrupt, the
mode, as well as on the interrupt type. non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
Interrupts do not affect the oscillator selection. STOP mode was entered will be completed by
3.5.3.1 Normal Mode executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
If the MCU was in the main routine when the WAIT interrupt mode.
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc- Notes:
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the To achieve the lowest power consumption during
STOP or WAIT instruction is then executed, pro- RUN or WAIT modes, the user program must take
viding no other interrupts are pending. care of:
3.5.3.2 Non Maskable Interrupt Mode – configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
If the STOP or WAIT instruction has been execut- logic levels);
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode – placing all peripherals in their power down
as soon as an interrupt occurs: the instruction modes before entering STOP mode;
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in- When the hardware activated Watchdog is select-
terrupt mode, even if another interrupt has been ed, or when the software Watchdog is enabled, the
generated. STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
If the MCU was in interrupt mode before the STOP MCU can only be restarted by a Reset. Although
or WAIT instruction was executed, it exits from setting GEN low does not mask the NMI as an in-
STOP or WAIT mode as soon as an interrupt oc- terrupt, it will stop it generating a wake-up signal.
curs. Nevertheless, two cases must be consid-
ered: The WAIT and STOP instructions are not execut-
– If the interrupt is a normal one, the interrupt rou- ed if an enabled interrupt request is pending.
tine in which the WAIT or STOP mode was en-

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 ST62T53C/T60C/T63C ST62E60C

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The MCU features Input/Output lines which may be also written by user software, in conjunction
be individually programmed as any of the following with the related option registers, to select the dif-
input or output configurations: ferent input mode options.
– Input without pull-up or interrupt Single-bit operations on I/O registers are possible
– Input with pull-up and interrupt but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
– Input with pull-up, but without interrupt ly affect the Port data register causing an unde-
– Analog input sired change of the input configuration.
– Push-pull output The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
– Open drain output
set.
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
Each port is associated with 3 registers in Data different port options available both in input and in
space. Each bit of these registers is associated output mode.
with a particular line (for instance, bits 0 of Port A
All I/O registers can be read or written to just as
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A). any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
The DATA registers (DRx), are used to read the manipulation. During MCU initialization, all I/O reg-
voltage level values of the lines which have been isters are cleared and the input mode with pull-ups
configured as inputs, or to write the logic value of and no interrupt generation is selected for all the
the signal to be output on the lines configured as pins, thus avoiding pin conflicts.
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 23. I/O Port Block Diagram

RESET VDD
SIN CONTROLS

DATA VDD
DIRECTION
REGISTER

INPUT/OUTPUT

DATA
REGISTER
SHIFT
REGISTER

OPTION
REGISTER

SOUT
TO INTERRUPT

TO ADC
VA00413

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ST62T53C/T60C/T63C ST62E60C

I/O PORTS (Cont’d)

4.1.1 Operating Modes 4.1.1.2 Interrupt Options
Each pin may be individually programmed as input All input lines can be individually connected by
or output with various configurations. software to the interrupt system by programming
This is achieved by writing the relevant bit in the the OR and DR registers accordingly. The inter-
Data (DR), Data Direction (DDR) and Option reg- rupt trigger modes (falling edge, rising edge and
isters (OR). Table 10 illustrates the various port low level) can be configured by software as de-
configurations which can be selected by user soft- scribed in the Interrupt Chapter for each port.
ware. 4.1.1.3 Analog Input Options
4.1.1.1 Input Options Some pins can be configured as analog inputs by
Pull-up, High Impedance Option. All input lines programming the OR and DR registers according-
can be individually programmed with or without an ly. These analog inputs are connected to the on-
internal pull-up by programming the OR and DR chip 8-bit Analog to Digital Converter. ONLY ONE
registers accordingly. If the pull-up option is not pin should be programmed as an analog input at
selected, the input pin will be in the high-imped- any time, since by selecting more than one input
ance state. simultaneously their pins will be effectively short-
ed.
Table 10. I/O Port Option Selection
DDR OR DR Mode Option
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 X Output Open-drain output (20mA sink when available)
1 1 X Output Push-pull output (20mA sink when available)

Note: X = Don’t care

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 ST62T53C/T60C/T63C ST62E60C

I/O PORTS (Cont’d)

4.1.2 Safe I/O State Switching Sequence outputs, it is advisable to keep a copy of the data
Switching the I/O ports from one state to another register in RAM. Single bit instructions may then
should be done in a sequence which ensures that be used on the RAM copy, after which the whole
no unwanted side effects can occur. The recom- copy register can be written to the port data regis-
mended safe transitions are illustrated in Figure ter:
24. All other transitions are potentially risky and SET bit, datacopy
should be avoided when changing the I/O operat- LD a, datacopy
ing mode, as it is most likely that undesirable side- LD DRA, a
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the Warning: Care must also be taken to not use in-
analog multiplexer. structions that act on a whole port register (INC,
Single bit instructions (SET, RES, INC and DEC) DEC, or read operations) when all 8 bits are not
should be used with great caution on Ports Data available on the device. Unavailable bits must be
registers, since these instructions make an implicit masked by software (AND instruction).
read and write back of the entire register. In port
input mode, however, the data register reads from
The WAIT and STOP instructions allow the
the input pins directly, and not from the data regis-
ter latches. Since data register information in input ST62xx to be used in situations where low power
mode is used to set the characteristics of the input consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the mode with well-defined logic levels.
state of the input pins. As a general rule, it is better The user must take care not to switch outputs with
to limit the use of single bit instructions on data heavy loads during the conversion of one of the
registers to when the whole (8-bit) port is in output analog inputs in order to avoid any disturbance to
mode. In the case of inputs or of mixed inputs and the conversion.

Figure 24. Diagram showing Safe I/O State Transitions

Interrupt Input
pull-up 010* 011 Analog

Input
pull-up (Reset 000 001 Input
state)

Output 100 101

Output
Open Drain Open Drain

Output 110 111

Output
Push-pull Push-pull
Note *. xxx = DDR, OR, DR Bits respectively

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ST62T53C/T60C/T63C ST62E60C

I/O PORTS (Cont’d)

Table 11I/O Port Option Selections

MODE AVAILABLE ON(1) SCHEMATIC

PA0-PA3
Input PB0-PB3, PB6-PB7
Data in
PC2-PC4

Interrupt

PA0-PA3
Input
PB0-PB3, PB6-PB7
with pull up Data in
PC2-PC4
Interrupt

Input PA0-PA3
with pull up PB0-PB3, PB6-PB7
Data in
with interrupt PC2-PC4
Interrupt

PA0-PA3
Analog Input
PC2-PC4 ADC

Open drain output PA0-PA3

5mA PC2-PC4

Data out
Open drain output PB0-PB3, PB6-PB7
30mA

Push-pull output PA0-PA3

5mA PC2-PC4

Data out

Push-pull output PB0-PB3, PB6-PB7

30mA

Note 1. Provided the correct configuration has been selected.

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 ST62T53C/T60C/T63C ST62E60C

I/O PORTS (Cont’d)

4.1.3 AR Timer Alternate function Option 4.1.4 SPI Alternate function Option
When bit PWMOE of register ARMC is low, pin AR- PC2/PC4 are used as standard I/O as long as bit
TIMout/PB7 is configured as any standard pin of SPCLK of the SPI Mode Register is kept low.
port B through the port registers. When PWMOE is When PC2/Sin is configured as input, it is automat-
high, ARTIMout/PB7 is the PWM output, independ- ically connected to the SPI shift register input, in-
ently of the port registers configuration. dependent of the state at SPCLK.
ARTIMin/PB6 is connected to the AR Timer input. PC3/SOUT is configured as SPI push-pull output
It is configured through the port registers as any by setting bit 0 of the Miscellaneous register (ad-
standard pin of port B. To use ARTIMin/PB6 as AR dress DDh), regardless of the state of Port C reg-
Timer input, it must be configured as input through isters. PC4/SCK is configured as push-pull output
DDRB. clock (master mode) by programming it as push-
pull output through DDRC register and by setting
bit SPCLK of the SPI Mode Register.
PC4/SCK is configured as input clock (slave mode)
by programming it as input through DDRC register
and by clearing bit SPCLK of the SPI Mode Regis-
ter. With this configuration, PC4 can simultaneous-
ly be used as an input.

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ST62T53C/T60C/T63C ST62E60C

I/O PORTS (Cont’d)

Figure 25Peripheral Interface Configuration of SPI, Timer 1 and AR Timer

VDD

PP/OD

1 OUT
PC3/Sout MUX
0 DR

b0
MISC.
OR REGISTER
IN

PC2/Sin DR
SPI

CLOCK IN

1 CLOCK OUT
PC4/SCK MUX
0 DR
SPCLK
MOD REGISTER
OR

IN
OR
TOUT
TIMER 1
1 OUT
PC1/TIM1 MUX
0 DR

ARTIMin

ARTIMin DR

AR TIMER
OR
PWMOE

PP/OD ARTIMout
1
ARTIMout MUX
0 DR
VR0C1661

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 ST62T53C/T60C/T63C ST62E60C

4.2 TIMER
The MCU features an on-chip Timer peripheral, The prescaler input is the internal frequency (fINT)
consisting of an 8-bit counter with a 7-bit program- divided by 12. The prescaler decrements on the
mable prescaler, giving a maximum count of 215. rising edge. Depending on the division factor pro-
Figure 26 shows the Timer Block Diagram. The grammed by PS2, PS1 and PS0 bits in the TSCR
content of the 8-bit counter can be read/written in (see Figure 12), the clock input of the timer/coun-
the Timer/Counter register, TCR, which can be ad- ter register is multiplexed to different sources. For
dressed in Data space as a RAM location at ad- division factor 1, the clock input of the prescaler is
dress 0D3h. The state of the 7-bit prescaler can be also that of timer/counter; for factor 2, bit 0 of the
read in the PSC register at address 0D2h. The prescaler register is connected to the clock input of
control logic device is managed in the TSCR reg- TCR. This bit changes its state at half the frequen-
ister as described in the following paragraphs. cy of the prescaler input clock. For factor 4, bit 1 of
the PSC is connected to the clock input of TCR,
The 8-bit counter is decrement by the output (ris- and so forth. The prescaler initialize bit, PSI, in the
ing edge) coming from the 7-bit prescaler and can TSCR register must be set to allow the prescaler
be loaded and read under program control. When (and hence the counter) to start. If it is cleared, all
it decrements to zero then the TMZ (Timer Zero)bit the prescaler bits are set and the counter is inhib-
in the TSCR is set. If the ETI (Enable Timer Inter- ited from counting. The prescaler can be loaded
rupt) bit in the TSCR is also set, an interrupt re- with any value between 0 and 7Fh, if bit PSI is set.
quest is generated. The Timer interrupt can be The prescaler tap is selected by means of the
used to exit the MCU from WAIT mode. PS2/PS1/PS0 bits in the control register.
Figure 27 illustrates the Timer’s working principle.
Figure 26. Timer Block Diagram

DATA BUS

8 8 8

6 8-BIT b7 b6 b5 b4 b3 b2 b1 b0
5
COUNTER
4 STATUS/CONTROL
PSC SELECT
3 REGISTER
2 1 OF 7
fINT 1 TMZ ETI D5 D4 PSI PS2 PS1 PS0
12
0
3

INTERRUPT
LINE

VR02070A

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ST62T53C/T60C/T63C ST62E60C

TIMER (Cont’d)
4.2.1 Timer Operation zero, the TMZ bit in the TSCR register is set to
The Timer prescaler is clocked by the prescaler one.
clock input (fINT ÷ 12). 4.2.3 Application Notes
The user can select the desired prescaler division TMZ is set when the counter reaches zero; howev-
ratio through the PS2, PS1, PS0 bits. When the er, it may also be set by writing 00h in the TCR
TCR count reaches 0, it sets the TMZ bit in the register or by setting bit 7 of the TSCR register.
TSCR. The TMZ bit can be tested under program The TMZ bit must be cleared by user software
control to perform a timer function whenever it when servicing the timer interrupt to avoid unde-
goes high. sired interrupts when leaving the interrupt service
4.2.2 Timer Interrupt routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
When the counter register decrements to zero with ed with 07Fh, and the TSCR register is cleared.
the ETI (Enable Timer Interrupt) bit set to one, an This means that the Timer is stopped (PSI=“0”)
interrupt request associated with Interrupt Vector and the timer interrupt is disabled.
#4 is generated. When the counter decrements to
Figure 27. Timer Working Principle

7-BIT PRESCALER

CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6

0 1 2 3 4 5 6 7 PS0
8-1 MULTIPLEXER PS1
PS2

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

8-BIT COUNTER

VA00186

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 ST62T53C/T60C/T63C ST62E60C

TIMER (Cont’d)
A write to the TCR register will predominate over PSI=“0” both counter and prescaler are not run-
the 8-bit counter decrement to 00h function, i.e. if a ning.
write and a TCR register decrement to 00h occur Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
simultaneously, the write will take precedence, lect. These bits select the division ratio of the pres-
and the TMZ bit is not set until the 8-bit counter caler register.
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time. Table 12. Prescaler Division Factors
PS2 PS1 PS0 Divided by
4.2.4 Timer Registers 0 0 0 1
Timer Status Control Register (TSCR) 0 0 1 2
Address: 0D4h — Read/Write 0 1 0 4
0 1 1 8
7 0
1 0 0 16
TMZ ETI D5 D4 PSI PS2 PS1 PS0 1 0 1 32
1 1 0 64
Bit 7 = TMZ: Timer Zero bit 1 1 1 128

A low-to-high transition indicates that the timer

count register has decrement to zero. This bit Timer Counter Register (TCR)
must be cleared by user software before starting a Address: 0D3h — Read/Write
new count.
7 0
Bit 6 = ETI: Enable Timer Interrup
When set, enables the timer interrupt request D7 D6 D5 D4 D3 D2 D1 D0
(vector #4). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener- Bit 7-0 = D7-D0: Counter Bits.
ated.
Bit 5 = D5: Reserved
Prescaler Register PSC
Must be set to “1”.
Address: 0D2h — Read/Write
Bit 4 = D4
Do not care. 7 0

Bit 3 = PSI: Prescaler Initialize Bit D7 D6 D5 D4 D3 D2 D1 D0

Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and Bit 7 = D7: Always read as "0".
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as Bit 6-0 = D6-D0: Prescaler Bits.

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ST62T53C/T60C/T63C ST62E60C

4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe- the prescaler and counter contents are frozen.
ripheral consists of an 8-bit timer/counter with When TEN is set, the AR counter runs at the rate
compare and capture/reload capabilities and of a of the selected clock source. The counter is
7-bit prescaler with a clock multiplexer, enabling cleared on system reset.
the clock input to be selected as fINT, fINT/3 or an The AR counter may also be initialized by writing
external clock source. A Mode Control Register, to the ARLR load register, which also causes an
ARMC, two Status Control Registers, ARSC0 and immediate copy of the value to be placed in the AR
ARSC1, an output pin, ARTIMout, and an input counter, regardless of whether the counter is run-
pin, ARTIMin, allow the Auto-Reload Timer to be ning or not. Initialization of the counter, by either
used in 4 modes: method, will also clear the ARPSC register, where-
– Auto-reload (PWM generation), upon counting will start from a known value.
– Output compare and reload on external event 4.3.2 Timer Operating Modes
(PLL), Four different operating modes are available for
– Input capture and output compare for time meas- the AR Timer:
urement. Auto-reload Mode with PWM Generation. This
– Input capture and output compare for period mode allows a Pulse Width Modulated signal to be
measurement. generated on the ARTIMout pin with minimum
The AR Timer can be used to wake the MCU from Core processing overhead.
WAIT mode either with an internal or with an exter- The free running 8-bit counter is fed by the pres-
nal clock. It also can be used to wake the MCU caler’s output, and is incremented on every rising
from STOP mode, if used with an external clock edge of the clock signal.
signal connected to the ARTIMin pin. A Load reg- When a counter overflow occurs, the counter is
ister allows the program to read and write the automatically reloaded with the contents of the Re-
counter on the fly. load/Capture Register, ARCC, and ARTIMout is
4.3.1 AR Timer Description set. When the counter reaches the value con-
The AR COUNTER is an 8-bit up-counter incre- tained in the compare register (ARCP), ARTIMout
mented on the input clock’s rising edge. The coun- is reset.
ter is loaded from the ReLoad/Capture Register, On overflow, the OVF flag of the ARSC0 register is
ARRC, for auto-reload or capture operations, as set and an overflow interrupt request is generated
well as for initialization. Direct access to the AR if the overflow interrupt enable bit, OVIE, in the
counter is not possible; however, by reading or Mode Control Register (ARMC), is set. The OVF
writing the ARLR load register, it is possible to flag must be reset by the user software.
read or write the counter’s contents on the fly. When the counter reaches the compare value, the
The AR Timer’s input clock can be either the inter- CPF flag of the ARSC0 register is set and a com-
nal clock (from the Oscillator Divider), the internal pare interrupt request is generated, if the Compare
clock divided by 3, or the clock signal connected to Interrupt enable bit, CPIE, in the Mode Control
the ARTIMin pin. Selection between these clock Register (ARMC), is set. The interrupt service rou-
sources is effected by suitably programming bits tine may then adjust the PWM period by loading a
CC0-CC1 of the ARSC1 register. The output of the new value into ARCP. The CPF flag must be reset
AR Multiplexer feeds the 7-bit programmable AR by user software.
Prescaler, ARPSC, which selects one of the 8 The PWM signal is generated on the ARTIMout
available taps of the prescaler, as defined by pin (refer to the Block Diagram). The frequency of
PSC0-PSC2 in the AR Mode Control Register. this signal is controlled by the prescaler setting
Thus the division factor of the prescaler can be set and by the auto-reload value present in the Re-
to 2n (where n = 0, 1,..7). load/Capture register, ARRC. The duty cycle of
The clock input to the AR counter is enabled by the the PWM signal is controlled by the Compare Reg-
TEN (Timer Enable) bit in the ARMC register. ister, ARCP.
When TEN is reset, the AR counter is stopped and

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AUTO-RELOAD TIMER (Cont’d)

Figure 28. AR Timer Block Diagram
DATA BUS
DDRB7

DRB7

AR COMPARE
REGISTER

8
PB7/
ARTIMout
CPF
COMPARE R

S
8
PWMOE

f INT OVF OVF

M
7-Bit 8-Bit OVIE
f INT /3 U
AR PRESCALER AR COUNTER LOAD
X TCLD

CC0-CC1 PS0-PS2 EIE

EF
AR TIMER
8
INTERRUPT
CPF
CPIE

8 8

PB6/
ARTIMin
SL0-SL1
AR AR
EF
SYNCHRO RELOAD/CAPTURE LOAD
REGISTER REGISTER

8 8

DATA BUS

VR01660A

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ST62T53C/T60C/T63C ST62E60C

AUTO-RELOAD TIMER (Cont’d)

It should be noted that the reload values will also The ARTC counter is initialized by writing to the
affect the value and the resolution of the duty cycle ARRC register and by then setting the TCLD (Tim-
of PWM output signal. To obtain a signal on ARTI- er Load) and the TEN (Timer Clock Enable) bits in
Mout, the contents of the ARCP register must be the Mode Control register, ARMC.
greater than the contents of the ARRC register. Enabling and selection of the clock source is con-
The maximum available resolution for the ARTI- trolled by the CC0, CC1, SL0 and SL1 bits in the
Mout duty cycle is: Status Control Register, ARSC1. The prescaler di-
Resolution = 1/[255-(ARRC)] vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com- In Auto-reload Mode, any of the three available
pare Register, ARCP, must be in the range from clock sources can be selected: Internal Clock, In-
(ARRC) to 255. ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 29. Auto-reload Timer PWM Function

COUNTER

255
COMPARE
VALUE

RELOAD
REGISTER
000
t

PWM OUTPUT

t
VR001852

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AUTO-RELOAD TIMER (Cont’d)

Capture Mode with PWM Generation. In this the count is incremented on every clock rising
mode, the AR counter operates as a free running edge.
8-bit counter fed by the prescaler output. The Each counter overflow sets the ARTIMout pin. A
counter is incremented on every clock rising edge. match between the counter and ARCP (Compare
An 8-bit capture operation from the counter to the Register) resets the ARTIMout pin and sets the
ARRC register is performed on every active edge compare flag, CPF. A compare interrupt request is
on the ARTIMin pin, when enabled by Edge Con- generated if the related compare interrupt enable
trol bits SL0, SL1 in the ARSC1 register. At the bit, CPIE, is set. A PWM signal is generated on
same time, the External Flag, EF, in the ARSC0 ARTIMout. The CPF flag must be reset by user
register is set and an external interrupt request is software.
generated if the External Interrupt Enable bit, EIE, Initialization of the counter is as described in the
in the ARMC register, is set. The EF flag must be previous paragraph. In addition, if the external AR-
reset by user software. TIMin input is enabled, an active edge on the input
Each ARTC overflow sets ARTIMout, while a pin will copy the contents of the ARRC register into
match between the counter and ARCP (Compare the counter, whether the counter is running or not.
Register) resets ARTIMout and sets the compare Notes:
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit, The allowed AR Timer clock sources are the fol-
CPIE, is set. A PWM signal is generated on ARTI- lowing:
Mout. The CPF flag must be reset by user soft- AR Timer Mode Clock Sources
ware.
Auto-reload mode fINT, fINT/3, ARTIMin
The frequency of the generated signal is deter- Capture mode fINT, fINT/3
mined by the prescaler setting. The duty cycle is Capture/Reset mode fINT, fINT/3
determined by the ARCP register.
External Load mode fINT, fINT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip- The clock frequency should not be modified while
tion). the counter is counting, since the counter may be
Enabling and selection of clock sources is control- set to an unpredictable value. For instance, the
led by the CC0 and CC1 bits in the AR Status Con- multiplexer setting should not be modified while
trol Register, ARSC1. the counter is counting.
The prescaler division ratio is selected by pro- Loading of the counter by any means (by auto-re-
gramming the PS0, PS1 and PS2 bits in the load, through ARLR, ARRC or by the Core) resets
ARSC1 Register. the prescaler at the same time.
In Capture mode, the allowed clock sources are Care should be taken when both the Capture inter-
the internal clock and the internal clock divided by rupt and the Overflow interrupt are used. Capture
3; the external ARTIMin input pin should not be and overflow are asynchronous. If the capture oc-
used as a clock source. curs when the Overflow Interrupt Flag, OVF, is
Capture Mode with Reset of counter and pres- high (between counter overflow and the flag being
caler, and PWM Generation. This mode is identi- reset by software, in the interrupt routine), the Ex-
cal to the previous one, with the difference that a ternal Interrupt Flag, EF, may be cleared simul-
capture condition also resets the counter and the taneusly without the interrupt being taken into ac-
prescaler, thus allowing easy measurement of the count.
time between two captures (for input period meas- The solution consists in resetting the OVF flag by
urement on the ARTIMin pin). writing 06h in the ARSC0 register. The value of EF
Load on External Input. The counter operates as is not affected by this operation. If an interrupt has
a free running 8-bit counter fed by the prescaler. occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).

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AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers ARSC0 register is also set, an interrupt request is
AR Mode Control Register (ARMC) generated.
Address: D5h — Read/Write Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
Reset status: 00h lowing bit combinations will select the various op-
erating modes:
7 0
ARMC1 ARMC0 Operating Mode
TCLD TEN PWMOE EIE CPIE OVIE ARMC1 ARMC0
0 0 Auto-reload Mode
0 1 Capture Mode
The AR Mode Control Register ARMC is used to Capture Mode with Reset
program the different operating modes of the AR 1 0
of ARTC and ARPSC
Timer, to enable the clock and to initialize the Load on External Edge
counter. It can be read and written to by the Core 1 1
Mode
and it is cleared on system reset (the AR Timer is
disabled).
AR Timer Status/Control Registers ARSC0 &
Bit 7 = TLCD: Timer Load Bit. This bit, when set, ARSC1. These registers contain the AR Timer sta-
will cause the contents of ARRC register to be tus information bits and also allow the program-
loaded into the counter and the contents of the ming of clock sources, active edge and prescaler
prescaler register, ARPSC, are cleared in order to multiplexer setting.
initialize the timer before starting to count. This bit ARSC0 register bits 0,1 and 2 contain the interrupt
is write-only and any attempt to read it will yield a
flags of the AR Timer. These bits are read normal-
logical zero. ly. Each one may be reset by software. Writing a
Bit 6 = TEN: Timer Clock Enable. This bit, when one does not affect the bit value.
set, allows the timer to count. When cleared, it will AR Status Control Register 0 (ARSC0)
stop the timer and freeze ARPSC and ARTSC.
Address: D6h — Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI- 7 0
Mout pin. When reset, the PWM output is disabled.
Bit 4 = EIE: External Interrupt Enable. This bit, D7 D6 D5 D4 D3 EF CPF OVF
when set, enables the external interrupt request.
When reset, the external interrupt request is Bits 7-3 = D7-D3: Unused
masked. If EIE is set and the related flag, EF, in
Bit 2 = EF: External Interrupt Flag. This bit is set by
the ARSC0 register is also set, an interrupt re-
quest is generated. any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request. Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
If CPIE is reset, the compare interrupt request is
ter are equal. The flag is cleared by writing a zero
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re- to the CPF bit.
quest is generated. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE (overflow). The flag is cleared by writing a zero to
the OVF bit.
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the

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AUTO-RELOAD TIMER (Cont’d)

AR Status Control Register 1(ARSC1) AR Load Register ARLR. The ARLR load register
Address: D7h — Read/Write is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
7 0 ter is not affected by system reset.
AR Load Register (ARLR)
PS2 PS1 PS0 D4 SL1 SL0 CC1 CC0
Address: DBh — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection 7 0
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by D7 D6 D5 D4 D3 D2 D1 D0
these bits. The prescaler division ratio is listed in the
following table: Bit 7-0 = D7-D0: Load Register Data Bits. These
Table 13. Prescaler Division Ratio Selection are the load register data bits.

PS2 PS1 PS0 ARPSC Division Ratio

AR Reload/Capture Register. The ARRC reload/
0 0 0 1 capture register is used to hold the auto-reload
0 0 1 2 value which is automatically loaded into the coun-
0 1 0 4 ter when overflow occurs.
0 1 1 8 AR Reload/Capture (ARRC)
1 0 0 16 Address: D9h — Read/Write
1 0 1 32
7 0
1 1 0 64
1 1 1 128 D7 D6 D5 D4 D3 D2 D1 D0

Bit 4 = D4: Reserved. Must be kept reset.

Bit 3-2 = SL1-SL0: Timer Input Edge Control Bits 1- Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
0. These bits control the edge function of the Timer are the Reload/Capture register data bits.
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection AR Compare Register. The CP compare register
is enabled. If bit SL1 is reset, the AR Timer input pin is used to hold the compare value for the compare
is rising edge sensitive; if set, it is falling edge sen- function.
sitive.
AR Compare Register (ARCP)
SL1 SL0 Edge Detection
Address: DAh — Read/Write
X 0 Disabled
0 1 Rising Edge 7 0
1 1 Falling Edge
D7 D6 D5 D4 D3 D2 D1 D0

Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.

These bits select the clock source for the AR Timer Bit 7-0 = D7-D0: Compare Data Bits. These are
through the AR Multiplexer. The programming of the Compare register data bits.
the clock sources is explained in the following Table
14:
Table 14. Clock Source Selection.
CC1 CC0 Clock Source
0 0 Fint
0 1 Fint Divided by 3
1 0 ARTIMin Input Clock
1 1 Reserved

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4.4 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to sion to allow stabilisation of the A/D converter.
digital converter with analog inputs as alternate I/O This action is also needed before entering WAIT
functions (the number of which is device depend- mode, since the A/D comparator is not automati-
ent), offering 8-bit resolution with a typical conver- cally disabled in WAIT mode.
sion time of 70us (at an oscillator clock frequency During Reset, any conversion in progress is
of 8MHz). stopped, the control register is reset to 40h and the
The ADC converts the input voltage by a process ADC interrupt is masked (EAI=0).
of successive approximations, using a clock fre-
quency derived from the oscillator with a division Figure 30. ADC Block Diagram
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased. INTERRUPT
CLOCK
Selection of the input pin is done by configuring Ain CONVERTER RESET
the related I/O line as an analog input via the Op- AVSS
tion and Data registers (refer to I/O ports descrip- AVDD
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si- CONTROL REGISTER RESULT REGISTER
multaneously, to avoid device malfunction.
8 8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores CORE CORE
the conversion result, and the ADC control regis- CONTROL SIGNALS VA00418
ter, ADCR, used to program the ADC functions.
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto- 4.4.1 Application Notes
matically clears (resets to “0”) the End Of Conver- The A/D converter does not feature a sample and
sion Bit (EOC). When a conversion is complete, hold circuit. The analog voltage to be measured
the EOC bit is automatically set to “1”, in order to should therefore be stable during the entire con-
flag that conversion is complete and that the data version cycle. Voltage variation should not exceed
in the ADC data conversion register is valid. Each ±1/2 LSB for the optimum conversion accuracy. A
conversion has to be separately initiated by writing low pass filter may be used at the analog input
to the STA bit. pins to reduce input voltage variation during con-
The STA bit is continuously scanned so that, if the version.
user sets it to “1” while a previous conversion is in When selected as an analog channel, the input pin
progress, a new conversion is started before com- is internally connected to a capacitor Cad of typi-
pleting the previous one. The start bit (STA) is a cally 12pF. For maximum accuracy, this capacitor
write only bit, any attempt to read it will show a log- must be fully charged at the beginning of conver-
ical “0”. sion. In the worst case, conversion starts one in-
The A/D converter features a maskable interrupt struction (6.5 µs) after the channel has been se-
associated with the end of conversion. This inter- lected. In worst case conditions, the impedance,
rupt is associated with interrupt vector #4 and oc- ASI, of the analog voltage source is calculated us-
curs when the EOC bit is set (i.e. when a conver- ing the following formula:
sion is completed). The interrupt is masked using 6.5µs = 9 x Cad x ASI
the EAI (interrupt mask) bit in the control register.
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
The power consumption of the device can be re- cluding a 50% guardband. ASI can be higher if Cad
duced by turning off the ADC peripheral. This is has been charged for a longer period by adding in-
done by setting the PDS bit in the ADC control reg- structions before the start of conversion (adding
ister to “0”. If PDS=“1”, the A/D is powered and en- more than 26 CPU cycles is pointless).
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-

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A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the micro- the noise during the conversion. But the first con-
processor, the user should not switch heavily load- version step is performed before the execution of
ed output signals during conversion, if high preci- the WAIT when most of clocks signals are still en-
sion is required. Such switching will affect the sup- abled . The key is to synchronize the ADC start
ply voltages used as analog references. with the effective execution of the WAIT. This is
The accuracy of the conversion depends on the achieved by setting ADC SYNC option. This way,
quality of the power supplies (V DD and VSS). The ADC conversion starts in effective WAIT for maxi-
user must take special care to ensure a well regu- mum accuracy.
lated reference voltage is present on the VDD and Note: With this extra option, it is mandatory to ex-
VSS pins (power supply voltage variations must be ecute WAIT instruction just after ADC start instruc-
less than 5V/ms). This implies, in particular, that a tion. Insertion of any extra instruction may cause
suitable decoupling capacitor is used at the VDD spurious interrupt request at ADC interrupt vector.
pin. A/D Converter Control Register (ADCR)
The converter resolution is given by:: Address: 0D1h — Read/Write
7 0
V DD – V SS
---------------------------- EAI EOC STA PDS D3 D2 D1 D0
256

Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to

The Input voltage (Ain) which is to be converted
“1” the A/D interrupt is enabled, when EAI=0 the
must be constant for 1µs before conversion and
interrupt is disabled.
remain constant during conversion.
Bit 6 = EOC: End of conversion. Read Only. This
Conversion resolution can be improved if the pow-
read only bit indicates when a conversion has
er supply voltage (VDD) to the microcontroller is been completed. This bit is automatically reset to
lowered. “0” when the STA bit is written. If the user is using
In order to optimise conversion resolution, the user the interrupt option then this bit can be used as an
can configure the microcontroller in WAIT mode, interrupt pending bit. Data in the data conversion
because this mode minimises noise disturbances register are valid only when this bit is set to “1”.
and power supply variations due to output switch- Bit 5 = STA : Start of Conversion. Write Only. Writ-
ing. Nevertheless, the WAIT instruction should be ing a “1” to this bit will start a conversion on the se-
executed as soon as possible after the beginning
lected channel and automatically reset to “0” the
of the conversion, because execution of the WAIT
EOC bit. If the bit is set again when a conversion is
instruction may cause a small variation of the VDD in progress, the present conversion is stopped and
voltage. The negative effect of this variation is min-
a new one will take place. This bit is write only, any
imized at the beginning of the conversion when the
attempt to read it will show a logical zero.
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are Bit 4 = PDS: Power Down Selection. This bit acti-
determined. vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
The best configuration, from an accuracy stand- mode).
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator Bit 3-0 = D3-D0. Not used
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking A/D Converter Data Register (ADR)
up the microcontroller could also be done using Address: 0D0h — Read only
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect 7 0
conversion accuracy.
D7 D6 D5 D4 D3 D2 D1 D0
One extra feature is available in the ADC to get a
better accuracy. In fact, each ADC conversion has
to be followed by a WAIT instruction to minimize Bit 7-0 = D7-D0 : 8 Bit A/D Conversion Result.

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4.5 SERIAL PERIPHERAL INTERFACE (SPI)

The SPI peripheral is an optimized synchronous mode is defined by the serial clock being supplied
serial interface with programmable transmission externally on the SCK pin by the external Master
modes and master/slave capabilities supporting a device.
wide range of industry standard SPI specifications. For maximum versatility the SPI may be pro-
The SPI interface may also implement asynchro- grammed to sample data either on the rising or on
nous data transfer, in which case processor over- the falling edge of SCK, with or without phase shift
head is limited to data transfer from or to the shift (clock Polarity and Phase selection).
register on an interrupt driven basis.
The Sin, Sout and SCK signals are connected as
The SPI may be controlled by simple user soft- alternate I/O pin functions.
ware to perform serial data exchange with low-
cost external memory, or with serially controlled For serial input operation, Sin must be configured
peripherals to drive displays, motors or relays. as an input. For serial output operation, Sout is se-
lected as an output by programming Bit 0 of the
The SPI’s shift register is simultaneously fed by Miscellaneous Register: clearing this bit will set
the Sin pin and feeds the Sout pin, thus transmis- the pin as a standard I/O line, while setting the bit
sion and reception are essentially the same proc- will select the Sout function.
ess. Suitable setting of the number of bits in the
data frame can allow filtering of unwanted leading An interrupt request may be associated with the
data bits in the incoming data stream. end of a transmission or reception cycle; this is de-
fined by programming the number of bits in the
The SPI comprises an 8-bit Data/Shift Register, data frame and by enabling the interrupt. This re-
DSR, a Divide register, DIV, a Mode Control Reg- quest is associated with interrupt vector #2, and
ister MOD, and a Miscellaneous register, MISCR. can be masked by programming the SPIE bit of
The SPI may be operated either in Master mode or the MOD register. Since the SPI interrupt is
in Slave mode. “ORed” with the port interrupt source, an interrupt
Master mode is defined by the synchronous serial flag bit is available in the DIV register allowing dis-
clock being supplied by the MCU, by suitably pro- crimination of the interrupt request.
gramming the clock divider (DIV register). Slave
Figure 31. SPI Block Diagram
CPU
SPI
CYCLE
DIVIDER
CLOCK

SCK FILTER

CLOCK

Sin FILTER
Sout

SHIFT
8 REGISTER

DATA BUS

VR001693

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.5.1 SPI Registers pin is configured as input, the slave mode is se-
SPI Mode Control Register (MOD) lected. If SPCLK is high, the SCK pin is automatic-
cally configured as push pull output and the mas-
Address: E2h — Read/Write ter mode is selected. In this case, the phase and
Reset status: 00h polarity of the clock are controlled by CPOL and
CPHA.
7 0
Note: When the master mode is enabled, it is
SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL mandatory to configure PC4 in input mode through
the i/o port registers.
The MOD register defines and controls the trans- Bit 3 = SPIN: Input Selection
mission modes and characteristics. This bit enables the transfer of the data input to the
This register is read/write and all bits are cleared Shift Register in receive mode. If this bit is cleared
at reset. Setting SPSTRT = 1 and SPIN = 1 is not the Shift Register input is 0. If this bit is set, the
allowed and must be avoided. Shift Register input corresponds to the input signal
present on the Sin pin.
Bit 7 = SPRUN: SPI Run. This bit is the SPI activity
flag. This can be used in either transmit or receive Bit 2 = SPSTRT: Start Selection
modes; it is automatically cleared by the SPI at the This bit selects the transmission or reception start
end of a transmission or reception and generates mode. If SPSTRT is cleared, the internal start con-
an interrupt request (providing that the SPIE Inter- dition occurs as soon as the SPRUN bit is set. If
rupt Enable bit is set). The Core can stop transmis- SPSTRT is set, the internal start signal is the logic
sion or reception at any time by resetting the “AND” between the SPRUN bit and the external
SPRUN bit; this will also generate an interrupt re- signal present on the Sin pin; in this case transmis-
quest (providing that the SPIE Interrupt enable bit sion will start after the latest of both signals provid-
is set). The SPRUN bit can be used as a start con- ing that the first signal is still present (note that this
dition parameter, in conjunction with the SPSTRT implies a rising edge). After the transmission or re-
bit, when an external signal is present on the Sin cetion has been started, it will continue even if the
pin. Note that a rising edge is then necessary to in- Sin signal is reset.
itiate reception; this may require external data in- Bit 1 = EFILT: Enable Filters
version. This bit can be used to poll the end of re-
ception or transmission. This bit enables/disables the input noise filters on
the Sin and SCK inputs. If it is cleared to zero the
Bit 6 = SPIE: SPI Interrupt Enable. This bit is the filters are enabled, if set to one the filters are disa-
SPI Interrupt Enable bit. If this bit is set the SPI in- bled. These noise filters will eliminate any pulse on
terrupt (vector #2) is enabled, when SPIE is reset, Sin and SCK with a pulse width smaller than one
the interrupt is disabled. to two Core clock periods (depending on the oc-
Bit 5 = CPHA: Clock Phase Selection. This bit se- currence of the signal edge with respect to the
lects the clock phase of the clock signal. If this bit Core clock edge). For example, if the ST6260B/
is cleared to zero the normal state is selected; in 65B runs with an 8MHz crystal, Sin and SCK will
this case Bit 7 of the data frame is present on Sout be delayed by 125 to 250ns.
pin as soon as the SPI Shift Register is loaded. If Bit 0 = CPOL: Clock Polarity
this bit is set to one the shifted state' is selected; in
this case Bit 7 of data frame is present on Sout pin This bit controls the relationship between the data
on the first falling edge of Shift Register clock. The on the Sin and Sout pins and SCK. The CPOL bit
polarity relation and the division ratio between selects the clock edge which captures data and al-
Shift Register and SPI base clock are also pro- lows it to change state. It has the greatest impact
grammable; refer to DIV register and Timing Dia- on the first bit transmitted (the MSB) as it does (or
grams for more information. does not) allow a clock transition before the first
data capture edge.
Bit 4= SPCLK: Base Clock Selection
Refer to the timing diagrams at the end of this sec-
This bit selects the SPI base clock source. It is ei- tion for additional details. These show the relation-
ther the core cycle clock (fINT/13) (Master mode) ship between CPOL, CPHA and SCK, and indicate
or the signal provided at SCK pin by an external the active clock edges and strobe times.
device (slave mode). If SPCLK is low and the SCK

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

SPI DIV Register (DIV) DIV6-DIV3 Number of bits sent
Address: E1h — Read/Write 0 0 0 0 Reserved (not to be used)
Reset status: 00h 0 0 0 1 1
0 0 1 0 2
7 0
0 0 1 1 3
SPINT DOV6 DIV5 DIV4 DIV3 CD2 CD1 CD0 0 1 0 0 4
0 1 0 1 5
The SPIDIV register defines the transmission rate 0 1 1 0 6
and frame format and contains the interrupt flag.
0 1 1 1 7
Bits CD0-CD2, DIV3-DIV6 are read/write while
1 0 0 0 8
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register is set. 1 0 0 1 9 ⎞
Bit 7 = SPINT: Interrupt Flag. If SPIE bit=1, SPINT 1 0 1 0 10 ⎟
is automatically set to one by the SPI at the end of 1 0 1 1 11 ⎟ Refer to the
a transmission or reception and an interrupt re- 1 1 0 0 12 ⎟ description of the
quest can be generated depending on the state of 1 1 0 1 13 ⎟ DIV6-DIV3 bits in
the interrupt mask bit in the MOD control register.
This bit is write and read and must be cleared by 1 1 1 0 14 ⎟ the DIV Register
user software at the end of the interrupt service 1 1 1 1 15 ⎠
routine.
Bit 6-3 = DIV6-DIV3: Burst Mode Bit Clock Period SPI Data/Shift Register (SPIDSR)
Selection. Define the number of shift register bits Address: E0h — Read/Write
that are transmitted or received in a frame. The
available selections are listed in Table 16. The Reset status: XXh
normal maximum setting is 8 bits, since the shift
7 0
register is 8 bits wide. Note that by setting a great-
er number of bits, in conjunction with the SPIN bit D7 D6 D5 D4 D3 D2 D1 D0
in the MOD register, unwanted data bits may be fil-
tered from the data stream.
SPIDSR is read/write, however write access is not
Bit 2-0 = CD2-CD0: Base/Bit Clock Rate Selec- allowed if the SPRUN bit of Mode Control register
tion. Define the division ratio between the core is set to one.
clock (fINT divided by 13) and the clock supplied to
the Shift Register in Master mode. Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA bits. The affect
Table 15. Base/Bit Clock Ratio Selection of these setting is shown in the following diagrams.
CD2-CD0 Divide Ratio (decimal) The Shift Register transmits and receives the Most
0 0 0 Divide by 1 Significant Bit first.
0 0 1 Divide by 2 Bit 7-0 = DSR7-DSR0: Data Bits. These are the
0 1 0 Divide by 4 SPI shift register data bits.
0 1 1 Divide by 8 Miscellaneous Register (MISCR)
1 0 0 Divide by 16 Address: DDh — Write only
1 0 1 Divide by 32 Reset status: xxxxxxxb
1 1 0 Divide by 64
7 0
1 1 1 Divide by 256
Note: For example, when an 8MHz CPU clock is - - - - - - - D0
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are Bit 7-1 = D7-D1: Reserved.
available by proportionally selecting division fac-
tors depending on CPU clock frequency. Bit 0 = D0: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
Data setup time on Sin is typically 250ns min, while
data hold time is typically 50ns min. cleared, Sout acts as a standard I/O line.

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

4.6 SPI Timing Diagrams

Figure 32. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal

SPRUN

SCK

Sin
Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR001694

Figure 33. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal

SPRUN

SCK

Sin
Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0A1694

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SERIAL PERIPHERAL INTERFACE SPI (Cont’d)

Figure 34. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted

SPRUN

SCK

Sin
Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0B1694

Figure 35. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted

SPRUN

SCK

Sin
Sampling

Sout b7 b6 b5 b4 b3 b2 b1 b0

VR0C1694

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 ST62T53C/T60C/T63C ST62E60C

5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use bits of the opcode with the byte following the op-
the hardware in the most efficient way possible code. The instructions (JP, CALL) which use the
while keeping byte usage to a minimum; in short, extended addressing mode are able to branch to
to provide byte efficient programming capability. any address of the 4K bytes Program space.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with An extended addressing mode instruction is two-
a single instruction. Furthermore, the program byte long.
may branch to a selected address depending on
Program Counter Relative. The relative address-
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
or RES instruction is processed.
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
5.2 ADDRESSING MODES ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
The ST6 core offers nine addressing modes, executed. The relative addressing mode instruc-
which are described in the following paragraphs. tion is one-byte long. The opcode is obtained in
Three different address spaces are available: Pro- adding the three most significant bits which char-
gram space, Data space, and Stack space. Pro- acterize the kind of the test, one bit which deter-
gram space contains the instructions which are to mines whether the branch is a forward (when it is
be executed, plus the data for immediate mode in- 0) or backward (when it is 1) branch and the four
structions. Data space contains the Accumulator, less significant bits which give the span of the
the X,Y,V and W registers, peripheral and Input/ branch (0h to Fh) which must be added or sub-
Output registers, the RAM locations and Data tracted to the address of the relative instruction to
ROM locations (for storage of tables and con- obtain the address of the branch.
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines Bit Direct. In the bit direct addressing mode, the
and interrupts. bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
Immediate. In the immediate addressing mode, dress of the byte in which the specified bit must be
the operand of the instruction follows the opcode set or cleared. Thus, any bit in the 256 locations of
location. As the operand is a ROM byte, the imme- Data space memory can be set or cleared.
diate addressing mode is used to access con-
stants which do not change during program execu- Bit Test & Branch. The bit test and branch ad-
tion (e.g., a constant used to initialize a loop coun- dressing mode is a combination of direct address-
ter). ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
Direct. In the direct addressing mode, the address tification and the tested condition are included in
of the byte which is processed by the instruction is the opcode byte. The address of the byte to be
stored in the location which follows the opcode. Di- tested follows immediately the opcode in the Pro-
rect addressing allows the user to directly address gram space. The third byte is the jump displace-
the 256 bytes in Data Space memory with a single ment, which is in the range of -127 to +128. This
two-byte instruction. displacement can be determined using a label,
which is converted by the assembler.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in Indirect. In the indirect addressing mode, the byte
the short-direct addressing mode. In this case, the processed by the register-indirect instruction is at
instruction is only one byte and the selection of the the address pointed by the content of one of the in-
location to be processed is contained in the op- direct registers, X or Y (80h,81h). The indirect reg-
code. Short direct addressing is a subset of the di- ister is selected by the bit 4 of the opcode. A regis-
rect addressing mode. (Note that 80h and 81h are ter indirect instruction is one byte long.
also indirect registers).
Inherent. In the inherent addressing mode, all the
Extended. In the extended addressing mode, the information necessary to execute the instruction is
12-bit address needed to define the instruction is contained in the opcode. These instructions are
obtained by concatenating the four less significant one byte long.

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5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions Load & Store. These instructions use one, two or
which, when combined with nine addressing three bytes in relation with the addressing mode.
modes, yield 244 usable opcodes. They can be di- One operand is the Accumulator for LOAD and the
vided into six different types: load/store, arithme- other operand is obtained from data memory using
tic/logic, conditional branch, control instructions, one of the addressing modes.
jump/call, and bit manipulation. The following par-
agraphs describe the different types. For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
All the instructions belonging to a given type are immediate data.
presented in individual tables.
Table 17. Load & Store Instructions
Flags
Instruction Addressing Mode Bytes Cycles
Z C
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *

Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected

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INSTRUCTION SET (Cont’d)

Arithmetic and Logic. These instructions are tent or an immediate value in relation with the ad-
used to perform the arithmetic calculations and dressing mode. In CLR, DEC, INC instructions the
logic operations. In AND, ADD, CP, SUB instruc- operand can be any of the 256 data space ad-
tions one operand is always the accumulator while dresses. In COM, RLC, SLA the operand is always
the other can be either a data space memory con- the accumulator.
Table 18. Arithmetic & Logic Instructions
Flags
Instruction Addressing Mode Bytes Cycles
Z C
ADD A, (X) Indirect 1 4 ∆ ∆
ADD A, (Y) Indirect 1 4 ∆ ∆
ADD A, rr Direct 2 4 ∆ ∆
ADDI A, #N Immediate 2 4 ∆ ∆
AND A, (X) Indirect 1 4 ∆ ∆
AND A, (Y) Indirect 1 4 ∆ ∆
AND A, rr Direct 2 4 ∆ ∆
ANDI A, #N Immediate 2 4 ∆ ∆
CLR A Short Direct 2 4 ∆ ∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆ ∆
CP A, (X) Indirect 1 4 ∆ ∆
CP A, (Y) Indirect 1 4 ∆ ∆
CP A, rr Direct 2 4 ∆ ∆
CPI A, #N Immediate 2 4 ∆ ∆
DEC X Short Direct 1 4 ∆ *
DEC Y Short Direct 1 4 ∆ *
DEC V Short Direct 1 4 ∆ *
DEC W Short Direct 1 4 ∆ *
DEC A Direct 2 4 ∆ *
DEC rr Direct 2 4 ∆ *
DEC (X) Indirect 1 4 ∆ *
DEC (Y) Indirect 1 4 ∆ *
INC X Short Direct 1 4 ∆ *
INC Y Short Direct 1 4 ∆ *
INC V Short Direct 1 4 ∆ *
INC W Short Direct 1 4 ∆ *
INC A Direct 2 4 ∆ *
INC rr Direct 2 4 ∆ *
INC (X) Indirect 1 4 ∆ *
INC (Y) Indirect 1 4 ∆ *
RLC A Inherent 1 4 ∆ ∆
SLA A Inherent 2 4 ∆ ∆
SUB A, (X) Indirect 1 4 ∆ ∆
SUB A, (Y) Indirect 1 4 ∆ ∆
SUB A, rr Direct 2 4 ∆ ∆
SUBI A, #N Immediate 2 4 ∆ ∆
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register

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INSTRUCTION SET (Cont’d)

Conditional Branch. The branch instructions Control Instructions. The control instructions
achieve a branch in the program when the select- control the MCU operations during program exe-
ed condition is met. cution.
Bit Manipulation Instructions. These instruc- Jump and Call. These two instructions are used
tions can handle any bit in data space memory. to perform long (12-bit) jumps or subroutines call
One group either sets or clears. The other group inside the whole program space.
(see Conditional Branch) performs the bit test
branch operations.
Table 19. Conditional Branch Instructions
Flags
Instruction Branch If Bytes Cycles
Z C
JRC e C=1 1 2 * *
JRNC e C=0 1 2 * *
JRZ e Z=1 1 2 * *
JRNZ e Z=0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Notes:
b. 3-bit address rr. Data space register
e. 5 bit signed displacement in the range -15 to +16<F128M> ∆ . Affected. The tested bit is shifted into carry.
ee. 8 bit signed displacement in the range -126 to +129 * . Not Affected

Table 20. Bit Manipulation Instructions

Flags
Instruction Addressing Mode Bytes Cycles
Z C
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Notes:
b. 3-bit address; * . Not<M> Affected
rr. Data space register;

Table 21. Control Instructions

Flags
Instruction Addressing Mode Bytes Cycles
Z C
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆ ∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Notes:
1. This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*. Not Affected

Table 22. Jump & Call Instructions

Instruction Flags
Addressing Mode Bytes Cycles
Z C
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
Notes:
abc. 12-bit address;
* . Not Affected

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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW LOW
0 1 2 3 4 5 6 7
0000 0001 0010 0011 0100 0101 0110 0111
HI HI
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
0 e abc e b0,rr,ee e # e a,(x) 0
0000 0000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI
1 e abc e b0,rr,ee e x e a,nn 1
0001 0001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP
2 e abc e b4,rr,ee e # e a,(x) 2
0010 0010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI
3 e abc e b4,rr,ee e a,x e a,nn 3
0011 0011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD
4 e abc e b2,rr,ee e # e a,(x) 4
0100 0100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI
5 e abc e b2,rr,ee e y e a,nn 5
0101 0101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC
6 e abc e b6,rr,ee e # e (x) 6
0110 0110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
7 e abc e b6,rr,ee e a,y e # 7
0111 0111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr,ee e # e (x),a 8
1000 1000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 RNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC
9 e abc e b1,rr,ee e v e # 9
1001 1001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND
A e abc e b5,rr,ee e # e a,(x) A
1010 1010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI
B e abc e b5,rr,ee e a,v e a,nn B
1011 1011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB
C e abc e b3,rr,ee e # e a,(x) C
1100 1100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI
D e abc e b3,rr,ee e w e a,nn D
1101 1101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC
E e abc e b7,rr,ee e # e (x) E
1110 1110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC
F e abc e b7,rr,ee e a,w e # F
1111 1111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

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Opcode Map Summary (Continued)

LOW LOW
8 9 A B C D E F
1000 1001 1010 1011 1100 1101 1110 1111
HI HI
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD
0 e abc e b0,rr e rr,nn e a,(y) 0
0000 0000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
1 e abc e b0,rr e x e a,rr 1
0001 0001
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP
2 e abc e b4,rr e a e a,(y) 2
0010 0010
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP
3 e abc e b4,rr e x,a e a,rr 3
0011 0011
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD
4 e abc e b2,rr e e a,(y) 4
0100 0100
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD
5 e abc e b2,rr e y e a,rr 5
0101 0101
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC
6 e abc e b6,rr e e (y) 6
0110 0110
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC
7 e abc e b6,rr e y,a e rr 7
0111 0111
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD
8 e abc e b1,rr e # e (y),a 8
1000 1000
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind
2 RNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
9 e abc e b1,rr e v e rr,a 9
1001 1001
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND
A e abc e b5,rr e a e a,(y) A
1010 1010
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND
B e abc e b5,rr e v,a e a,rr B
1011 1011
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB
C e abc e b3,rr e e a,(y) C
1100 1100
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB
D e abc e b3,rr e w e a,rr D
1101 1101
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC
E e abc e b7,rr e e (y) E
1110 1110
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC
F e abc e b7,rr e w,a e rr F
1111 1111
1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir

Abbreviations for Addressing Modes: Legend:

dir Direct # Indicates Illegal Instructions Cycle
sd Short Direct e 5 Bit Displacement 2 JRC Mnemonic
imm Immediate b 3 Bit Address Operand e
inh Inherent rr 1byte dataspace address
Bytes 1 prc
ext Extended nn 1 byte immediate data
b.d Bit Direct abc 12 bit address
Addressing Mode
bt Bit Test ee 8 bit Displacement
pcr Program Counter Relative
ind Indirect

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6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs Power Considerations.The average chip-junc-
against damage due to high static voltages, how- tion temperature, Tj, in Celsius can be obtained
ever it is advisable to take normal precaution to from:
avoid application of any voltage higher than the Tj=TA + PD x RthJA
specified maximum rated voltages.
Where:TA = Ambient Temperature.
For proper operation it is recommended that VI
and VO be higher than V SS and lower than V DD. RthJA =Package thermal resistance (junc-
Reliability is enhanced if unused inputs are con- tion-to ambient).
nected to an appropriate logic voltage level (VDD PD = Pint + Pport.
or V SS).
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).

Symbol Parameter Value Unit

VDD Supply Voltage -0.3 to 7.0 V
(1)
VI Input Voltage VSS - 0.3 to VDD + 0.3 V
VO Output Voltage VSS - 0.3 to VDD + 0.3(1) V
IVDD Total Current into VDD (source) 80 mA
IVSS Total Current out of VSS (sink) 100 mA
Tj Junction Temperature 150 °C
TSTG Storage Temperature -60 to 150 °C

Notes:
- Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.

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6.2 RECOMMENDED OPERATING CONDITIONS

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
6 Suffix Version -40 85
TA Operating Temperature 1 Suffix Version 0 70 °C
3 Suffix Version -40 125
fOSC = 4MHz, 1 & 6 Suffix 3.0 6.0
Operating Supply Voltage fOSC = 4MHz, 3 Suffix 3.0 6.0
V
(Except ST626xB ROM devices) fosc= 8MHz , 1 & 6 Suffix 3.6 6.0
fosc= 8MHz , 3 Suffix 4.5 6.0
VDD
fOSC = 4MHz, 1 & 6 Suffix 3.0 6.0
Operating Supply Voltage fOSC = 4MHz, 3 Suffix 3.0 6.0
V
(ST626xB ROM devices) fosc= 8MHz , 1 & 6 Suffix 4.0 6.0
fosc= 8MHz , 3 Suffix 4.5 6.0
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency2) VDD = 3.0V , 3 Suffix 0 4.0
MHz
(Except ST626xB ROM devices) VDD = 3.6V , 1 & 6 Suffix 0 8.0
VDD = 3.6V , 3 Suffix 0 4.0
fOSC
VDD = 3.0V, 1 & 6 Suffix 0 4.0
Oscillator Frequency2) VDD = 3.0V , 3 Suffix 0 4.0
MHz
(ST626xB ROM devices) VDD = 4.0V , 1 & 6 Suffix 0 8.0
VDD = 4.0V , 3 Suffix 0 4.0
IINJ+ Pin Injection Current (positive) VDD = 4.5 to 5.5V +5 mA
IINJ- Pin Injection Current (negative) VDD = 4.5 to 5.5V -5 mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results

Figure 36. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (V DD)

Maximum FREQUENCY (MHz)

1 & 6 Suffix version

8
FUNCTIONALITY IS NOT
1 & 6 Suffix 3 Suffix version
7 GUARANTEED IN
version
THIS AREA
6

4
3 Suffix version
3

1
2.5 3 3.6 4 4.5 5 5.5 6

SUPPLY VOLTAGE (VDD)

All devices except ST626xB ROM devices

ST626xB ROM devices

The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.

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 ST62T53C/T60C/T63C ST62E60C

6.3 DC ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIL Input Low Level Voltage
VDD x 0.3 V
All Input pins
VIH Input High Level Voltage
VDD x 0.7 V
All Input pins

Hysteresis Voltage (1) VDD= 5V 0.2

VHys V
All Input pins VDD= 3V 0.2

Vup LVD Threshold in power-on 4.1 4.3

Vdn LVD threshold in powerdown 3.5 3.8
Low Level Output Voltage VDD= 5.0V; IOL = +10µA 0.1
All Output pins VDD= 5.0V; IOL = + 3mA 0.8
VOL VDD= 5.0V; IOL = +10µA 0.1 V
Low Level Output Voltage
VDD= 5.0V; IOL = +7mA 0.8
30 mA Sink I/O pins
VDD= 5.0V; IOL = +15mA 1.3
High Level Output Voltage VDD= 5.0V; IOH = -10µA 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -3.0mA 3.5
All Input pins 40 100 350
RPU Pull-up Resistance ΚΩ
RESET pin 150 350 900
Input Leakage Current VIN = VSS (No Pull-Up configured)
0.1 1.0
IIL All Input pins but RESET VIN = VDD
µA
IIH Input Leakage Current VIN = VSS -8 -16 -30
RESET pin VIN = VDD 10
Supply Current in RESET VRESET=VSS
7 mA
Mode fOSC=8MHz
Supply Current in
VDD=5.0V fINT=8MHz 7 mA
RUN Mode (2)
Supply Current in WAIT
IDD VDD=5.0V fINT=8MHz 2.5 mA
Mode (3)
Supply Current in STOP ILOAD=0mA
20 µA
Mode, with LVD disabled(3) VDD=5.0V
Supply Current in STOP ILOAD=0mA
500
Mode, with LVD enabled(3) VDD=5.0V
Retention EPROM Data Retention TA = 55°C 10 years

Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by

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ST62T53C/T60C/T63C ST62E60C

DC ELECTRICAL CHARACTERISTICS (Cont’d)

(TA = -40 to +85°C unless otherwise specified))

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Vup LVD Threshold in power-on Vdn +50 mV 4.1 4.3 V
Vdn LVD threshold in powerdown 3.6 3.8 Vup -50 mV V
VDD= 5.0V; IOL = +10µA 0.1
Low Level Output Voltage
VDD= 5.0V; IOL = + 5mA 0.8
All Output pins
VDD= 5.0V; IOL = + 10mAv 1.2
VOL VDD= 5.0V; IOL = +10µA 0.1 V
Low Level Output Voltage VDD= 5.0V; IOL = +10mA 0.8
30 mA Sink I/O pins VDD= 5.0V; IOL = +20mA 1.3
VDD= 5.0V; IOL = +30mA 2.0
High Level Output Voltage VDD= 5.0V; IOH = -10µA 4.9
VOH V
All Output pins VDD= 5.0V; IOH = -5.0mA 3.5
Supply Current in STOP ILOAD=0mA
IDD 10 µA
Mode, with LVD disabled(*) VDD=5.0V

Note:
(*) All Peripherals in stand-by.

6.4 AC ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
tREC Supply Recovery Time (1) 100 ms
TA = 25°C 5 10
TWEE EEPROM Write Time TA = 85°C 10 20 ms
TA = 125°C 20 30
Endurance
(2) EEPROM WRITE/ERASE Cycle QA LOT Acceptance (25°C) 300,000 1 million cycles

Retention EEPROM Data Retention TA = 55°C 10 years

fLFAO Internal frequency with LFAO active 200 400 800 kHz
VDD = 3V 1
Internal Frequency with OSG VDD = 3.6V 1
fOSG fOSC MHz
enabled2) VDD = 4.5V 2
VDD = 6V 2
VDD=5.0V (Except 626xB ROM)
R=47kΩ 4 5 5.8 MHz
R=100kΩ 2.7 3.2 3.5 MHz
R=470kΩ 800 850 900 kHz
Internal frequency with RC oscilla-
fRC VDD=5.0V (626xB ROM)
tor and OSG disabled2) 3)
R=10kΩ 6.3 8.2 9.8 MHz
R=27kΩ 4.7 5.9 7 MHz
R=67kΩ 2.8 3.6 4.3 MHz
R=100kΩ 2.2 2.8 3.4 MHz
CIN Input Capacitance All Inputs Pins 10 pF
COUT Output Capacitance All Outputs Pins 10 pF

Notes:
1. Period for which VDD has to be connected at 0V to allow internal Reset function at next power-up.
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.

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 ST62T53C/T60C/T63C ST62E60C

6.5 A/D CONVERTER CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Res Resolution 8 Bit
fOSC > 1.2MHz ±2
ATOT Total Accuracy (1) (2) LSB
fOSC > 32kHz ±4
fOSC = 8MHz (TA < 85°C) 70
tC Conversion Time µs
fOSC = 4 MHz 140
Conversion result when
ZIR Zero Input Reading 00 Hex
VIN = VSS
Conversion result when
FSR Full Scale Reading FF Hex
VIN = VDD
Analog Input Current During
ADI VDD= 4.5V 1.0 µA
Conversion
ACIN Analog Input Capacitance 2 5 pF

Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.

6.6 TIMER CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.

fIN Input Frequency on TIMER Pin

f INT MHz
----------
4
VDD = 3.0V 1 µs
tW Pulse Width at TIMER Pin
VDD >4.5V 125 ns

6.7 SPI CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
FCL Clock Frequency Applied on Scl 500 kHz
tSU Set-up Time Applied on Sin 250 ns
th Hold Time Applied onSin 50 ns

6.8 ARTIMER ELECTRICAL CHARACTERISTICS

(TA = -40 to +125°C unless otherwise specified)

Value
Symbol Parameter Test Conditions Unit
Min Typ Max

RUN and WAIT Modes

fIN Input Frequency on ARTIMin Pin MHz

STOP mode 2

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ST62T53C/T60C/T63C ST62E60C

Figure 37. Vol versus Iol on all I/O port at Vdd=5V

6 T = -40°C
Vol (V)

T = 25°C
4
T = 95°C
2 T = 125°C

0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only

Figure 38. Vol versus Iol on all I/O port at T=25°C

8
6 Vdd = 3.0V
Vol (V)

Vdd = 4.0V
4
Vdd = 5.0V
2 Vdd = 6.0V
0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only

Figure 39. Vol versus Iol for High sink (30mA) I/Oports at T=25°C

5
4
Vdd = 3.0V
Vol (V)

3 Vdd = 4.0V
2 Vdd = 5.0V
1 Vdd = 6.0V

0
0 10 20 30 40
Iol (mA)
This curves represents typical variations and is given for guidance only

70/84
 ST62T53C/T60C/T63C ST62E60C

Figure 40. Vol versus Iol for High sink (30mA) I/O ports at Vdd=5V

5
4
T = -40°C
Vol (V)

3 T = 25°C
2 T = 95°C
T = 125°C
1
0
0 10 20 30 40
Iol (mA)

This curves represents typical variations and is given for guidance only

Figure 41. Voh versus Ioh on all I/O port at 25°C

6
4 Vdd = 3.0V
Voh (V)

Vdd = 4.0V
2
Vdd = 5.0V
0 Vdd = 6.0V
-2
0 10 20 30 40
Ioh (mA)
This curves represents typical variations and is given for guidance only

Figure 42. Voh versus Ioh on all I/O port at Vdd=5V

4 T = -40°C
Voh (V)

T = 25°C
2
T = 95°C
0 T = 125°C

-2
0 10 20 30 40
Ioh (mA)

This curves represents typical variations and is given for guidance only

71/84
ST62T53C/T60C/T63C ST62E60C

Figure 43. Idd WAIT versus VDD at 8 Mhz for OTP devices

2.5
Idd WAIT (mA)

2 T = -40°C
1.5 T = 25°C
1 T = 95°C
0.5 T = 125°C
0
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 44. Idd STOP versus VDD for OTP devices

8
Idd STOP (µA)

6 T = -40°C
4 T = 25°C
2 T = 95°C
0 T = 125°C
-2
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 45. Idd STOP versus VDD for ROM devices

1.5
Idd STOP (µA)

T = -40°C
1
T = 25°C
0.5 T = 95°C
T = 125°C
0

-0.5
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

72/84
 ST62T53C/T60C/T63C ST62E60C

Figure 46. Idd WAIT versus VDD at 8Mhz for ROM devices

2.5
Idd WAIT (mA)

2 T = -40°C
1.5 T = 25°C
1 T = 95°C
0.5 T = 125°C
0
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 47. Idd RUN versus VDD at 8 Mhz for ROM and OTP devices

6
Idd RUN (mA)

T = -40°C
T = 25°C
4
T = 95°C
T = 125°C
2

0
3V 4V 5V 6V
Vdd
This curves represents typical variations and is given for guidance only

Figure 48. LVD thresholds versus temperature

4.2

4.1
Vthresh.

4
Vup
Vdn
3.9

3.8

3.7
-40°C 25°C 95°C 125°C
Temp
This curves represents typical variations and is given for guidance only

73/84
ST62T53C/T60C/T63C ST62E60C

Figure 49. RC frequency versus V DD for ROM ST626xB only

10

R=1OK

R=27K
Frequency
MHz

R=67K

R=100K

1
3 4 5 6
VDD (volts)]

This curves represents typical variations and is given for guidance only

Figure 50. RC frequency versus V DD (Except for ST626xB ROM devices)

10
Frequency

R=47K
MHz

1 R=100K
R=470K

0.1
3 3.5 4 4.5 5 5.5 6
VDD (volts)
This curves represents typical variations and is given for guidance only

74/84
 ST62T53C/T60C/T63C ST62E60C

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA

Figure 51. 20-Pin Plastic Dual In-Line Package, 300-mil Width

mm inches
Dim.
A2 A Min Typ Max Min Typ Max
A 5.33 0.210
A1 L c A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b eB
D1 b2 e b 0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D D 24.89 26.16 26.92 0.980 1.030 1.060
D1 0.13 0.005
e 2.54 0.100
20 11
eB 10.92 0.430
E1
E1 6.10 6.35 7.11 0.240 0.250 0.280
1 10
L 2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
N 20

Figure 52. 20-Pin Ceramic Side-Brazed Dual In-Line Package

mm inches
Dim.
Min Typ Max Min Typ Max
A 3.63 0.143
A1 0.38 0.015
B 3.56 0.46 0.56 0.140 0.018 0.022
B1 1.14 12.70 1.78 0.045 0.500 0.070
C 0.20 0.25 0.36 0.008 0.010 0.014
D 24.89 25.40 25.91 0.980 1.000 1.020
D1 22.86 0.900
E1 6.99 7.49 8.00 0.275 0.295 0.315
e 2.54 0.100
G 6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.14 0.045
L 2.92 3.30 3.81 0.115 0.130 0.150
S 12.70 0.500
Ø 4.22 0.166
CDIP20W Number of Pins
N 20

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ST62T53C/T60C/T63C ST62E60C

PACKAGE MECHANICAL DATA (Cont’d)

Figure 53. 20-Pin Plastic Small Outline Package, 300-mil Width

D
mm inches
h x 45× Dim.
L
Min Typ Max Min Typ Max
A A 2.35 2.65 0.093 0.104
A1 c
A1 0.10 0.30 0.004 0.012
a
B e B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.60 13.00 0.496 0.512
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
E H
α 0° 8° 0° 8°
L 0.40 1.27 0.016 0.050
Number of Pins
N 20

7.2 ORDERING INFORMATION

Table 23OTP/EPROM VERSION ORDERING INFORMATION

Program
Sales Type EEPROM (Bytes) Temperature Range Package
Memory (Bytes)
ST62T53CB6 -40 to + 85°C
PDIP20
ST62T53CB3 -40 to + 125°C
1836 (OTP) -
ST62T53CM6 -40 to + 85°C
PSO20
ST62T53CM3 -40 to + 125°C
ST62T60CB6 -40 to + 85°C
PDIP20
ST62T60CB3 -40 to + 125°C
3884 (OTP) 128
ST62T60CM6 -40 to + 85°C
PSO20
ST62T60CM3 -40 to + 125°C
ST62T63CB6 PDIP20
1836 (OTP) 64 -40 to + 85°C
ST62T63CM6 PSO20
ST62E60CF1 3884 (EPROM) 128 0 to +70°C CDIP20

76/84
 ST62P53C/P60C/P63C
8-BIT FASTROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 128 bytes
■ Data EEPROM: 64/128 bytes (none on ST62P53C) PDIP20
■ User Programmable Options
■ 13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 6 I/O lines can sink up to 30mA to drive LEDs or PSO20
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler (See end of Datasheet for Ordering Information)
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■ Digital Watchdog
■ Oscillator Safe Guard DEVICE SUMMARY
■ Low Voltage Detector for Safe Reset DEVICE ROM (Bytes) EEPROM
■ 8-bit A/D Converter with 7 analog inputs ST62P53C 1836 -
■ 8-bit Synchronous Peripheral Interface (SPI) ST62P60C 3884 128
ST62P63C 1836 64
■ On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■ User configurable Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).

Rev. 2.8

July 2001 77/84

1
ST62P53C/P60C/P63C

1 GENERAL DESCRIPTION
1.1 INTRODUCTION tents and options which will be used to produce
the specified MCU. The listing is then returned to
The ST62P53C, ST62P60C and ST62P63C are
the customer who must thoroughly check, com-
the Factory Advanced Service Technique ROM plete, sign and return it to STMicroelectronics. The
(FASTROM) versions of ST62T53C, ST6260B signed listing forms a part of the contractual agree-
and ST62T63C OTP devices.
ment for the production of the specific customer
They offer the same functionality as OTP devices, MCU.
selecting as FASTROM options the options de-
The STMicroelectronics Sales Organization will be
fined in the programmable option byte of the OTP pleased to provide detailed information on con-
version. tractual points.
1.2 ORDERING INFORMATION Table 24. ROM Memory Map for ST62P60C
The following section deals with the procedure for Device Address Description
transfer of customer codes to STMicroelectronics.
0000h-007Fh Reserved
1.2.1 Transfer of Customer Code 0080h-0F9Fh User ROM
Customer code is made up of the ROM contents 0FA0h-0FEFh Reserved
and the list of the selected FASTROM options. 0FF0h-0FF7h Interrupt Vectors
0FF8h-0FFBh Reserved
The ROM contents are to be sent on diskette, or
0FFCh-0FFDh NMI Interrupt Vector
by electronic means, with the hexadecimal file 0FFEh-0FFFh Reset Vector
generated by the development tool. All unused
bytes must be set to FFh. Table 25. ROM Memory Map: ST62P53C/P63C
The selected options are communicated to STMi- Device Address Description
croelectronics using the correctly filled OPTION 0000h-087Fh Reserved
LIST appended. See page 82. 0880h-0F9Fh User ROM
1.2.2 Listing Generation and Verification 0FA0h-0FEFh Reserved
0FF0h-0FF7h Interrupt Vectors
When STMicroelectronics receives the user’s 0FF8h-0FFBh Reserved
ROM contents, a computer listing is generated 0FFCh-0FFDh NMI Interrupt Vector
from it. This listing refers exactly to the ROM con- 0FFEh-0FFFh Reset Vector
Table 26. FASTROM Version Ordering Information
Sales Type ROM (Bytes) EEPROM (Bytes) Temperature Range Package
ST62P53CB1/XXX 0 to + 70°C
ST62P53CB6/XXX -40 to + 85°C PDIP20
ST62P53CB3/XXX (*) -40 to + 125°C
1836 -
ST62P53CM1/XXX 0 to + 70°C
ST62P53CM6/XXX -40 to + 85°C PSO20
ST62P53CM3/XXX (*) -40 to + 125°C
ST62P60CB1/XXX 0 to + 70°C
ST62P60CB6/XXX -40 to + 85°C PDIP20
ST62P60CB3/XXX (*) -40 to + 125°C
3884 128
ST62P60CM1/XXX 0 to + 70°C
ST62P60CM6/XXX -40 to + 85°C PSO20
ST62P60CM3/XXX (*) -40 to + 125°C
ST62P63CB1/XXX 0 to + 70°C
ST62P63CB6/XXX -40 to + 85°C PDIP20
ST62P63CB3/XXX (*) -40 to + 125°C
1836 64
ST62P63CM1/XXX 0 to + 70°C
ST62P63CM6/XXX -40 to + 85°C PSO20
ST62P63CM3/XXX (*) -40 to + 125°C
(*) Advanced information

78/84
1
 ST6253C/60B/63B
8-BIT ROM MCUs WITH A/D CONVERTER,
SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI

■ 3.0 to 6.0V Supply Operating Range

■ 8 MHz Maximum Clock Frequency
■ -40 to +125°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 128 bytes
■ Data EEPROM: 64/128 bytes (none on ST6253C) PDIP20
■ User Programmable Options
■ 13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 6 I/O lines can sink up to 30mA to drive LEDs or PSO20
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler (See end of Datasheet for Ordering Information)
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■ Digital Watchdog
■ 8-bit A/D Converter with 7 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI) DEVICE SUMMARY
■ On-chip Clock oscillator can be driven by Quartz DEVICE ROM (Bytes) EEPROM LVD & OSG
Crystal Ceramic resonator or RC network ST6253C 1836 - Yes
■ User configurable Power-on Reset ST6260B 3884 128 No
■ One external Non-Maskable Interrupt ST6263B 1836 64 No
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).

Rev. 2.8

July 2001 79/84

1
ST6253C/60B/63B

1 GENERAL DESCRIPTION
1.1 INTRODUCTION 1.2 ROM READOUT PROTECTION
The ST6253C, ST6260B and ST6263B are mask If the ROM READOUT PROTECTION option is
programmed ROM versions of ST62T53C, selected, a protection fuse can be blown to pre-
ST6260B and ST62T63C OTP devices. vent any access to the program memory content.
They offer the same functionality as OTP devices, In case the user wants to blow this fuse, high volt-
selecting as ROM options the options defined in age must be applied on the TEST pin.
the programmable option byte of the OTP version,
except the LVD & OSG options that are not availa-
ble on the ST6260B/63B ROM device. Figure 55. Programming Circuit
Figure 54. Programming wave form

0.5s min
TEST
5V 47mF

15 100nF
14V typ
10
VSS
5

VDD

TEST PROTECT
150 µs typ
TEST 14V
100nF
100mA ZPD15
max 15V

VR02003

4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection

80/84
1
 ST6253C/60B/63B

1.3 ORDERING INFORMATION

The following section deals with the procedure for The STMicroelectronics Sales Organization will be
transfer of customer codes to STMicroelectronics. pleased to provide detailed information on contrac-
1.3.1 Transfer of Customer Code tual points.
Customer code is made up of the ROM contents Table 27. ROM Memory Map for ST6260B
and the list of the selected mask options. The ROM Device Address Description
contents are to be sent on diskette, or by electronic
means, with the hexadecimal file generated by the 0000h-007Fh Reserved
0080h-0F9Fh User ROM
development tool. All unused bytes must be set to
0FA0h-0FEFh Reserved
FFh. 0FF0h-0FF7h Interrupt Vectors
The selected mask options are communicated to 0FF8h-0FFBh Reserved
STMicroelectronics using the correctly filled OP- 0FFCh-0FFDh NMI Interrupt Vector
TION LIST appended. See page 82. 0FFEh-0FFFh Reset Vector
1.3.2 Listing Generation and Verification
Table 28. ROM Memory Map for ST6253C/63B
When STMicroelectronics receives the user’s ROM
Device Address Description
contents, a computer listing is generated from it.
This listing refers exactly to the mask which will be 0000h-087Fh Reserved
used to produce the specified MCU. The listing is 0880h-0F9Fh User ROM
then returned to the customer who must thoroughly 0FA0h-0FEFh Reserved
0FF0h-0FF7h Interrupt Vectors
check, complete, sign and return it to STMicroelec-
0FF8h-0FFBh Reserved
tronics. The signed listing forms a part of the con- 0FFCh-0FFDh NMI Interrupt Vector
tractual agreement for the creation of the specific 0FFEh-0FFFh Reset Vector
customer mask.

Table 1. ROM Version Ordering Information

Sales Type ROM (Bytes) EEPROM (Bytes) Temperature Range Package
ST6253CB1/XXX 0 to + 70°C
ST6253CB6/XXX -40 to + 85°C PDIP20
ST6253CB3/XXX -40 to + 125°C
1836 -
ST6253CM1/XXX 0 to + 70°C
ST6253CM6/XXX -40 to + 85°C PSO20
ST6253CM3/XXX -40 to + 125°C
ST6260BB1/XXX 0 to + 70°C
ST6260BB6/XXX -40 to + 85°C PDIP20
ST6260BB3/XXX -40 to + 125°C
3884 128
ST6260BM1/XXX 0 to + 70°C
ST6260BM6/XXX -40 to + 85°C PSO20
ST6260BM3/XXX -40 to + 125°C
ST6263BB1/XXX 0 to + 70°C
ST6263BB6/XXX -40 to + 85°C PDIP20
ST6263BB3/XXX -40 to + 125°C
1836 64
ST6263BM1/XXX 0 to + 70°C
ST6263BM6/XXX -40 to + 85°C PSO20
ST6263BM3/XXX -40 to + 125°C

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ST6253C/60B/63B

ST6253C/60B/63B/P53C/P60C/P63C MICROCONTROLLER OPTION LIST

Customer: .... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...
Address: .... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...
.... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...
Contact: .... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...
Phone: .... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...
Reference: .... ..... .... .... .... .... .... ..... .... .... .... .... ..... ............ .... ...

STMicroelectronics references:

Device: [ ] ST6253C (2 KB) [ ] ST6260B (4 KB) [ ] ST6263B (2 KB)

[ ] ST62P53C (2 KB) [ ] ST62P60C (4 KB) [ ] ST62P63C (2 KB)

Package: [ ] Dual in Line Plastic

[ ] Small Outline Plastic with conditioning
Conditioning option: [ ] Standard (Tube) [ ] Tape & Reel
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C

Marking: [ ] Standard marking

[ ] Special marking (ROM only)
PDIP28 (10 char. max): _ _ _ _ _ _ _ _ _ _
PSO28 (8 char. max): _ _ _ _ _ _ _ _
SSOP28 (11 char. max): _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Oscillator Safeguard*: [ ] Enabled [ ] Disabled

Oscillator Selection: [ ] Quartz crystal / Ceramic resonator
[ ] RC network
Reset Delay: [ ] 32768 cycle delay [ ] 2048 cycle delay
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
PB1:PB0 Pull-Up at RESET*: [ ] Enabled [ ] Disabled
PB3:PB2 Pull-Up at RESET*: [ ] Enabled [ ] Disabled
External STOP Mode Control: [ ] Enabled [ ] Disabled

Readout Protection: FASTROM:

[ ] Enabled [ ] Disabled
ROM:
[ ] Enabled:
[ ] Fuse is blown by STMicroelectronics
[ ] Fuse can be blown by the customer
[ ] Disabled

Low Voltage Detector*: [ ] Enabled [ ] Disabled

NMI pull-up*: [ ] Enabled [ ] Disabled
ADC Synchro*: [ ] Enabled [ ] Disabled
*except on ST6260B/63B

Comments:
Oscillator Frequency in the application: ...........................................
Supply Operating Range in the application: ...........................................
Notes: ..........................................................................
Date: ..........................................................................
Signature: ..........................................................................

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 ST6253C/60B/63B

2 SUMMARY OF CHANGES
Rev. Main Changes Date

Modification of “Additional Notes for EEPROM Parallel Mode” (p.13)

In section 4.2 on page 43: vector #4 instead of vector #3 for the timer interrupt request.
July
2.8 Changed fRC values in section 6.4 on page 68.
2001
Changed Figure 49 on page 74.
Changed option list on page 82.

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ST6253C/60B/63B

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
©2001 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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