ST72340, ST72344, ST72345

8-BIT MCU WITH UP TO 16K FLASH MEMORY,

10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI

■ Memories
– up to 16 Kbytes Program memory: Single volt-
age extended Flash (XFlash) with read-out
and write protection, In-Circuit and In-Applica-
tion Programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20 LQFP48 LQFP44
years at 55°C. 7x7 10 x 10
– up to 1 Kbyte RAM
– 256 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management LQFP32
– Power On / Power Off safe reset with 3 pro- 7x7
grammable threshold levels (LVD)
– Auxiliary Voltage Detector (AVD) – 16-bit timer B with: 2 input captures, 2 output
compares, PWM and Pulse generator modes
– Clock sources: crystal/ceramic resonator os- ■ 3 Communication Interfaces
cillators, high-accuracy internal RC oscillator
or external clock – I2C Multi Master / Slave
– PLL for 4x or 8x frequency multiplication – I2C Slave 3 Addresses No Stretch with DMA
– 5 Power Saving Modes: Slow, Wait, Halt, access and Byte Pair Coherency on I²C Read
Auto-Wakeup from Halt and Active Halt – SCI asynchronous serial interface (LIN com-
– Clock output capability (fCPU) patible)
■ Interrupt Management – SPI synchronous serial interface
– Nested interrupt controller ■ 1 Analog peripheral
– 10 interrupt vectors plus TRAP and RESET – 10-bit ADC with 12 input channels (8 on 32-
pin devices)
– 9 external interrupt lines on 4 vectors
■ Instruction Set
■ Up to 34 I/O Ports
– 8-bit data manipulation
– up to 34 multifunctional bidirectional I/O lines
– 63 basic instructions with illegal opcode de-
– up to 12 high sink outputs (10 on 32-pin devic- tection
es)
– 17 main addressing modes
■ 4 Timers
– 8 x 8 unsigned multiply instruction
– Configurable window watchdog timer ■ Development tools
– Realtime base
– Full hardware/software development package
– 16-bit timer A with: 1 input capture, 1 output
compares, external clock input, PWM and – On-Chip Debug Module
Pulse generator modes
Device Summary
Features ST72F340 ST72F344 ST72F345
Program memory - bytes 8K 16K 8K 16K 16K
RAM (stack) - bytes 512 (256) 1K (256) 512 (256) 1K (256) 1K (256)
EEPROM data - bytes 256 256 256 256 256
Common peripherals Window Watchdog, 2 16-bit Timers, SCI, SPI, I2CMMS
Other peripherals - 10-bit ADC I2C3SNS, 10-bit ADC
Int high-accuracy 1MHz RC Not present Present Present
CPU Frequency 8MHz @ 3.3V to 5.5V, 4MHz @ 2.7V to 5.5V
Temperature Range -40°C to +85 °C
Package LQFP32 7x7, LQFP44 10x10 LQFP48 7x7
Rev. 2

October 2006 1/191

1
 Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.5 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 42
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
191
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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 Table of Contents
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 65
11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5 SCI SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.7 I2C TRIPLE SLAVE INTERFACE WITH DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13.4 PLL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.5 INTERNAL RC OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.6 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.7 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.8 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.9 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.10 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.11 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 174
13.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 181
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
. . . 187
16.1 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 188

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16.3 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.4 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.5 IN-APPLICATION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.6 PROGRAMMING OF EEPROM DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.7 FLASH WRITE/ERASE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Please pay special attention to the Section “KNOWN LIMITATIONS” on page 187

191

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 ST72340, ST72344, ST72345

1 INTRODUCTION
The ST7234x devices are members of the ST7 mi- The enhanced instruction set and addressing
crocontroller family. All devices are based on a modes of the ST7 offer both power and flexibility to
common industry-standard 8-bit core, featuring an software developers, enabling the design of highly
enhanced instruction set. efficient and compact application code. In addition
They feature single-voltage FLASH memory with to standard 8-bit data management, all ST7 micro-
byte-by-byte In-Circuit Programming (ICP) and In- controllers feature true bit manipulation, 8x8 un-
Application Programming (IAP) capabilities. signed multiplication and indirect addressing
modes.
Under software control, all devices can be placed
in WAIT, SLOW, Auto-Wakeup from Halt, Active- The devices feature an on-chip Debug Module
HALT or HALT mode, reducing power consump- (DM) to support in-circuit debugging (ICD). For a
tion when the application is in idle or stand-by description of the DM registers, refer to the ST7
state. ICC Protocol Reference Manual.

Figure 1. General Block Diagram

8-BIT CORE PROGRAM

ALU MEMORY
(16K - 32K Bytes)
RESET
CONTROL
RAM
VSS (512- 1024 Bytes)
VDD LVD

AVD WATCHDOG
OSC1
CLOCK CONTROL I2CMMS
OSC2
PA
ADDRESS AND DATA BUS

(5-bits)
INTERNAL RC PORT A

MCC/RTC/BEEP
PORT B
PB
PORT F (5-bits)
PWM ART
PF
(6-bits)
TIMER A

PORT C
BEEP

TIMER B PC
(8-bits)
I2C3SNS
SPI
PD
(6-bits) PORT D

PORT E
10-BIT ADC PE
(2-bits)
VAREF
SCI
VSSA

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ST72340, ST72344, ST72345

2 PIN DESCRIPTION
Figure 2. LQFP32 Package Pinout

PD1 / AIN1
PD0 / AIN0

PE0 / TDO
PE1 / RDI
PB4 (HS)

VDD_2
PB3
PB0
32 31 30 29 28 27 26 25
VDDA 24 OSC1

)
1
ei3 ei2 ei0
VSSA 2 23 OSC2
AIN8 / PF0 3 22 VSS_2
ei1
(HS) PF1 4 21 RESET
OCMP1_A / AIN10 / PF4 5 20 ICCSEL
ICAP1_A / (HS) PF6 6 19 PA7 (HS) / SCL
EXTCLK_A / (HS) PF7 7 18 PA6 (HS) / SDA
AIN12 / OCMP2_B / PC0 8 ei0 17 PA4 (HS)
9 10 11 12 13 14 15 16
AIN14 / MOSI / PC5
ICCCLK / SCK / PC6
AIN15 / SS / PC7
(HS) PA3
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4

(HS) 20mA high sink capability

eix associated external interrupt vector

Figure 3. LQFP44 Package Pinout

PA6 (HS) / SDA
PA7 (HS) / SCL
PE0 / TDO

PA5 (HS)
PA4 (HS)
ICCSEL
RESET
VDD_2

VSS_2
OSC1
OSC2

44 43 42 41 40 39 38 37 36 35 34
RDI / PE1 1 ei0 33 VSS_1
PB0 2 32 VDD_1
PB1 3 ei0 31 PA3 (HS)
ei2
PB2 4 30 PC7 / SS / AIN15
PB3 5 29 PC6 / SCK / ICCCLK
(HS) PB4 6 ei3 28 PC5 / MOSI / AIN14
AIN0 / PD0 7 27 PC4 / MISO / ICCDATA
AIN1 / PD1 8 26 PC3 (HS) / ICAP1_B
AIN2 / PD2 9 25 PC2 (HS) / ICAP2_B
AIN3 / PD3 10 24 PC1 / OCMP1_B / AIN13
ei1
AIN4 / PD4 11 23 PC0 / OCMP2_B / AIN12
12 13 14 15 16 17 18 19 20 21 22
EXTCLK_A / (HS) PF7
BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

VDDA
VSSA

(HS) PF2

ICAP1_A / (HS) PF6

VDD_0
VSS_0
AIN5 / PD5

MCO / AIN8 / PF0

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 ST72340, ST72344, ST72345

PIN DESCRIPTION (Cont’d)

Figure 4. LQFP48 Package Pinout

PD6/SDA3SNS
PD7/SCL3SNS
PA6 (HS)/SDA
PA7 (HS)/SCL

PA5 (HS)
PA4 (HS)
ICCSEL
RESET
OSC1
OSC2
VDD_2

VSS_2
48 47 46 45 44 43 42 41 40 39 38 37
PE0/TD0 1 36 VSS_1
RDI / PE1 2 ei0 35 VDD_1
PB0 3 ei0 34 PA3 (HS)
PB1 4 33 PC7 / SS / AIN15
ei2 PC6 / SCK / ICCCLK
PB2 5 32
PB3 6 31 PC5 / MOSI / AIN14
(HS) PB4 7 ei3 30 PC4 / MISO / ICCDATA
AIN0 / PD0 8 29 PC3 (HS) / ICAP1_B
AIN1 / PD1 9 28 PC2 (HS) / ICAP2_B
AIN2 / PD2 10 27 PC1 / OCMP1_B / AIN13
AIN3 / PD3 11 26 NC
AIN4 / PD4 12 ei1 25 NC
13 14 15 16 17 18 19 20 21 22 23 24
OCMP1_A / AIN10 / PF4
BEEP / (HS) PF1

EXTCLK_A / (HS) PF7

VDDA
VSSA

(HS) PF2

VDD_0
VSS_0
AIN5 / PD5

MCO / AIN8 / PF0

PC0 / OCMP2_B / AIN12

ICAP1_A / (HS) PF6

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ST72340, ST72344, ST72345

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 152.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output: OD = open drain 2), PP = push-pull

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are set in in-
put pull-up configuration after reset through the option byte Package selection. The configuration of these
pads must be kept at reset state to avoid added current consumption.
Table 1. Device Pin Description
Pin n° Level Port
Main
Type

function
LQFP32
LQFP44
LQFP48

Input Output
Output

Pin Name Alternate Function

Input

(after
float
wpu

ana

reset)
OD

PP
int

1 13 14 VDDA S Analog Supply Voltage

2 14 15 VSSA S Analog Ground Voltage
PF0/MCO/ Main clock out ADC Analog
3 15 16 I/O CT X ei1 X X X Port F0
AIN8 (fOSC/2) Input 8
PF1 (HS)/
4 16 17 I/O CT HS X ei1 X X Port F1 Beep signal output
BEEP
17 18 PF2 (HS) I/O CT HS X ei1 X X Port F2
PF4/
Timer A Output ADC Analog
5 18 19 OCMP1_A/ I/O CT X X X X X Port F4
Compare 1 Input 10
AIN10
PF6 (HS)/
6 19 20 I/O CT HS X X X X Port F6 Timer A Input Capture 1
ICAP1_A
PF7 (HS)/
7 20 21 I/O CT HS X X X X Port F7 Timer A External Clock Source
EXTCLK_A
- 21 22 VDD_0 S Digital Main Supply Voltage
- 22 23 VSS_0 S Digital Ground Voltage
PC0/
Timer B Output ADC Analog
8 23 24 OCMP2_B/ I/O CT X X X X X Port C0
Compare 2 Input 12
AIN12
PC1/
Timer B Output ADC Analog
9 24 27 OCMP1_B/ I/O CT X X X X X Port C1
Compare 1 Input 13
AIN13
PC2 (HS)/
10 25 28 I/O CT HS X X X X Port C2 Timer B Input Capture 2
ICAP2_B

8/191
 ST72340, ST72344, ST72345

Pin n° Level Port

Main

Type
function
LQFP32
LQFP44
LQFP48

Input Output

Output
Pin Name Alternate Function

Input
(after

float
wpu

ana
reset)

OD

PP
int
PC3 (HS)/
11 26 29 I/O CT HS X X X X Port C3 Timer B Input Capture 1
ICAP1_B
PC4/MISO/ SPI Master In / ICC Data In-
12 27 30 I/O CT X X X X Port C4
ICCDATA3) Slave Out Data put
PC5/MOSI/ SPI Master Out / ADC Analog
13 28 31 I/O CT X X X X X Port C5
AIN14 Slave In Data Input 14
PC6/SCK/ ICC Clock
14 29 32 I/O CT X X X X Port C6 SPI Serial Clock
ICCCLK3) Output
SPI Slave Select ADC Analog
15 30 33 PC7/SS/AIN15 I/O CT X X X X X Port C7
(active low) Input 15
16 31 34 PA3 (HS) I/O CT HS X ei0 X X Port A3
- 32 35 VDD_1 S Digital Main Supply Voltage
- 33 36 VSS_1 S Digital Ground Voltage
PD7/
- - 37 I/O CT HS X T Port D7 I2C3SNS Serial Clock
SCL3SNS
PD6/
- - 38 I/O CT HS X T Port D6 I2C3SNS Serial Data
SDA3SNS
17 34 39 PA4 (HS) I/O CT HS X X X X Port A4
35 40 PA5 (HS) I/O CT HS X X X X Port A5
18 36 41 PA6 (HS)/SDA I/O CT HS X T Port A6 I2C Serial Data
19 37 42 PA7 (HS)/SCL I/O CT HS X T Port A7 I2C Serial Clock
20 38 43 ICCSEL I ICC Mode selection
21 39 44 RESET I/O CT Top priority non maskable interrupt.
22 40 45 VSS_2 S Digital Ground Voltage
23 41 46 OSC2 O Resonator oscillator inverter output
External clock input or Resonator oscillator in-
24 42 47 OSC1 I
verter input
25 43 48 VDD_2 S Digital Main Supply Voltage
26 44 1 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out
27 1 2 PE1/RDI I/O CT X ei0 X X Port E1 SCI Receive Data In
28 2 3 PB0 I/O CT X ei2 X X Port B0
- 3 4 PB1 I/O CT X ei2 X X Port B1
- 4 5 PB2 I/O CT X ei2 X X Port B2
29 5 6 PB3 I/O CT X ei2 X X Port B3
30 6 7 PB4 (HS) I/O CT HS X ei3 X X Port B4
31 7 8 PD0/AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0
32 8 9 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1
- 9 10 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2
- 10 11 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3
- 11 12 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4
12 13 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5

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ST72340, ST72344, ST72345

Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented).
3. On the BGA package, ICCDATA and ICCCLK are bonded on pins E3 and A4 respectively. They are not
implemented as alternate functions on PC4 and PC6.

10/191
 ST72340, ST72344, ST72345

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad- of user program memory. The RAM space in-
dressing 64 Kbytes of memories and I/O registers. cludes up to 256 bytes for the stack from 0100h to
The available memory locations consist of 128 01FFh.
bytes of register locations, up to 1 Kbytes of RAM, The highest address bytes contain the user reset
256 bytes of Data EEPROM and up to 16 Kbytes and interrupt vectors.
Figure 5. Memory Map

0000h 0080h
HW Registers Short Addressing
See Table
007Fh RAM (zero page)
0080h 00FFh
RAM 0100h
(512 or 1K Bytes)
047Fh 256 Bytes Stack
0480h 01FFh
Reserved 0200h
0BFFh 16-bit Addressing
0C00h RAM
Data EEPROM 047Fh
(256 Bytes)
0CFFh
0D00h C000h C000h
Reserved
BFFFh SECTOR 2
C000h 16 KBytes
Program Memory E000h
E000h
(8 or 16 KBytes) SECTOR 1
FFDFh F000h (4k)
FFE0h 8 KBytes or FB00h (2k)
Interrupt & Reset Vectors or FC00h (1k)
or FE00h (0.5k)
See Table 8 SECTOR 0
FFFFh
FFFFh FFFFh

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ST72340, ST72344, ST72345

REGISTER AND MEMORY MAP (Cont’d)

Table 2. Hardware Register Map

Register
Address Block Register Name Reset Status Remarks
Label

0000h PADR Port A Data Register 00h1) R/W

2)
0001h Port A PADDR Port A Data Direction Register 00h R/W
0002h PAOR Port A Option Register 00h R/W

0003h PBDR Port B Data Register 00h 1) R/W

0004h Port B2) PBDDR Port B Data Direction Register 00h R/W
0005h PBOR Port B Option Register 00h R/W

0006h PCDR Port C Data Register 00h1) R/W

0007h Port C2) PCDDR Port C Data Direction Register 00h R/W
0008h PCOR Port C Option Register 00h R/W

0009h PDADR Port D Data Register 00h1) R/W

000Ah Port D2) PDDDR Port D Data Direction Register 00h R/W
000Bh PDOR Port D Option Register 00h R/W

000Ch PEDR Port E Data Register 00h1) R/W

000Dh Port E2) PEDDR Port E Data Direction Register 00h R/W
000Eh PEOR Port E Option Register 00h R/W

000Fh PFDR Port F Data Register 00h1) R/W

2)
0010h Port F PFDDR Port F Data Direction Register 00h R/W
0011h PFOR Port F Option Register 00h R/W

0012h to
Reserved area (5 bytes)
0016h

0017h RCCRH RC oscillator Control Register High FFh R/W

RC
0018h RCCRL RC oscillator Control Register Low 03h R/W

0019h Reserved area (1 byte)

001Ah to
DM3) Reserved area (6 bytes)
001Fh

00020h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

0021h SPIDR SPI Data I/O Register xxh R/W

0022h SPI SPICR SPI Control Register 0xh R/W
0023h SPICSR SPI Control Status Register 00h R/W

0024h ISPR0 Interrupt Software Priority Register 0 FFh R/W

0025h ISPR1 Interrupt Software Priority Register 1 FFh R/W
0026h ITC ISPR2 Interrupt Software Priority Register 2 FFh R/W
0027h ISPR3 Interrupt Software Priority Register 3 FFh R/W

0028h EICR External Interrupt Control Register 00h R/W

00029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WWDG WDGCR Watchdog Control Register 7Fh R/W

002Bh SI SICSR System Integrity Control/Status Register 000x 000xb R/W

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 ST72340, ST72344, ST72345

Register
Address Block Register Name Reset Status Remarks
Label

002Ch MCCSR Main Clock Control/Status Register 00h R/W

MCC
002Dh MCCBCR MCC Beep Control Register 00h R/W

002Eh AWUCSR AWU Control/Status Register 00h R/W

AWU
002Fh AWUPR AWU Prescaler Register FFh R/W

0030h WWDG WDGWR Window Watchdog Control Register 7Fh R/W

0031h TACR2 Timer A Control Register 2 00h R/W

0032h TACR1 Timer A Control Register 1 00h R/W
0033h TACSR Timer A Control/Status Register xxh R/W
0034h TAIC1HR Timer A Input Capture 1 High Register xxh Read Only
0035h TAIC1LR Timer A Input Capture 1 Low Register xxh Read Only
0036h TAOC1HR Timer A Output Compare 1 High Register 80h R/W
0037h TAOC1LR Timer A Output Compare 1 Low Register 00h R/W
0038h TIMER A TACHR Timer A Counter High Register FFh Read Only
0039h TACLR Timer A Counter Low Register FCh Read Only
003Ah TAACHR Timer A Alternate Counter High Register FFh Read Only
003Bh TAACLR Timer A Alternate Counter Low Register FCh Read Only
003Ch TAIC2HR Timer A Input Capture 2 High Register xxh Read Only
003Dh TAIC2LR Timer A Input Capture 2 Low Register xxh Read Only
003Eh TAOC2HR Timer A Output Compare 2 High Register 80h R/W
003Fh TAOC2LR Timer A Output Compare 2 Low Register 00h R/W

0040h Reserved Area (1 Byte)

0041h TBCR2 Timer B Control Register 2 00h R/W

0042h TBCR1 Timer B Control Register 1 00h R/W
0043h TBCSR Timer B Control/Status Register xxh R/W
0044h TBIC1HR Timer B Input Capture 1 High Register xxh Read Only
0045h TBIC1LR Timer B Input Capture 1 Low Register xxh Read Only
0046h TBOC1HR Timer B Output Compare 1 High Register 80h R/W
0047h TBOC1LR Timer B Output Compare 1 Low Register 00h R/W
0048h TIMER B TBCHR Timer B Counter High Register FFh Read Only
0049h TBCLR Timer B Counter Low Register FCh Read Only
004Ah TBACHR Timer B Alternate Counter High Register FFh Read Only
004Bh TBACLR Timer B Alternate Counter Low Register FCh Read Only
004Ch TBIC2HR Timer B Input Capture 2 High Register xxh Read Only
004Dh TBIC2LR Timer B Input Capture 2 Low Register xxh Read Only
004Eh TBOC2HR Timer B Output Compare 2 High Register 80h R/W
004Fh TBOC2LR Timer B Output Compare 2 Low Register 00h R/W

0050h SCISR SCI Status Register C0h Read Only

0051h SCIDR SCI Data Register xxh R/W
0052h SCIBRR SCI Baud Rate Register 00h R/W
0053h SCICR1 SCI Control Register 1 x000 0000b R/W
SCI
0054h SCICR2 SCI Control Register 2 00h R/W
0055h Reserved area --
0056h SCIERPR SCI Extended Receive Prescaler Register 00h R/W
0057h SCIETPR SCI Extended Transmit Prescaler Register 00h R/W

13/191
ST72340, ST72344, ST72345

Register
Address Block Register Name Reset Status Remarks
Label

0058h I2CCR I2C Control Register 00h R/W

0059h I2CSR1 I2C Status Register 1 00h Read Only
005Ah I2CSR2 I2C Status Register 2 00h Read Only
005Bh I2C I2CCCR I2C Clock Control Register 00h R/W
005Ch I2COAR1 I2C Own Address Register 1 00h R/W
005Dh I2COAR2 I2C Own Address Register2 40h R/W
005Eh I2CDR I2C Data Register 00h R/W

005Fh Reserved area (1 byte)

0060h I2C3SCR1 I2C3SNS Control Register 1 00h R/W

0061h I2C3SCR2 I2C3SNS Control Register 2 00h R/W
0062h I2C3SSR I2C3SNS Status Register 00h Read Only
0063h I2C3SBCR I2C3SNS Byte Count Register 00h Read Only
0064h I2C3SSAR1 I2C3SNS Slave Address 1 Register 00h R/W
I2C3SNS
0065h I2C3SCAR1 I2C3SNS Current Address 1 Register 00h R/W
0066h I2C3SSAR2 I2C3SNS Slave Address 2 Register 00h R/W
0067h I2C3SCAR2 I2C3SNS Current Address 2 Register 00h R/W
0068h I2C3SSAR3 I2C3SNS Slave Address 3 Register 00h R/W
0069h I2C3SCAR3 I2C3SNS Current Address 3 Register 00h R/W

0070h ADCCSR A/D Control Status Register 00h R/W

0071h ADC ADCDRH A/D Data Register High xxh Read Only
0072h ADCDRL A/D Data Low Register 0000 00xxb Read Only

0073h to
Reserved area (13 bytes)
007Fh

Legend: x=undefined, R/W=read/write

Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.

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 ST72340, ST72344, ST72345

4 FLASH PROGRAM MEMORY the device from the application board and
while the application is running.
4.3.1 In-Circuit Programming (ICP)
4.1 Introduction
ICP uses a protocol called ICC (In-Circuit Commu-
The ST7 single voltage extended Flash (XFlash) is nication) which allows an ST7 plugged on a print-
a non-volatile memory that can be electrically ed circuit board (PCB) to communicate with an ex-
erased and programmed either on a byte-by-byte ternal programming device connected via cable.
basis or up to 32 bytes in parallel. ICP is performed in three steps:
The XFlash devices can be programmed off-board Switch the ST7 to ICC mode (In-Circuit Communi-
(plugged in a programming tool) or on-board using cations). This is done by driving a specific signal
In-Circuit Programming or In-Application Program- sequence on the ICCCLK/DATA pins while the
ming. RESET pin is pulled low. When the ST7 enters
The array matrix organisation allows each sector ICC mode, it fetches a specific RESET vector
to be erased and reprogrammed without affecting which points to the ST7 System Memory contain-
other sectors. ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
4.2 Main Features – Download ICP Driver code in RAM from the
ICCDATA pin
■ ICP (In-Circuit Programming) – Execute ICP Driver code in RAM to program
■ IAP (In-Application Programming) the FLASH memory
■ ICT (In-Circuit Testing) for downloading and Depending on the ICP Driver code downloaded in
executing user application test patterns in RAM RAM, FLASH memory programming can be fully
■ Sector 0 size configurable by option byte customized (number of bytes to program, program
■ Read-out and write protection locations, or selection of the serial communication
interface for downloading).
4.3 PROGRAMMING MODES 4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
The ST7 can be programmed in three different programmed in Sector 0 by the user (in ICP
ways: mode).
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and This mode is fully controlled by user software. This
data EEPROM (if present) can be pro- allows it to be adapted to the user application, (us-
grammed or erased. er-defined strategy for entering programming
– In-Circuit Programming. In this mode, FLASH mode, choice of communications protocol used to
sectors 0 and 1, option byte row and data fetch the data to be stored etc.)
EEPROM (if present) can be programmed or IAP mode can be used to program any memory ar-
erased without removing the device from the eas except Sector 0, which is write/erase protect-
application board.
ed to allow recovery in case errors occur during
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can the programming operation.
be programmed or erased without removing

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ST72340, ST72344, ST72345

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface 2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
ICP needs a minimum of 4 and up to 7 pins to be flicts between the programming tool and the appli-
connected to the programming tool. These pins cation reset circuit if it drives more than 5mA at
are: high level (push pull output or pull-up resistor<1K).
– RESET: device reset A schottky diode can be used to isolate the appli-
– VSS: device power supply ground cation RESET circuit in this case. When using a
– ICCCLK: ICC output serial clock pin classical RC network with R>1K or a reset man-
– ICCDATA: ICC input serial data pin agement IC with open drain output and pull-up re-
– ICCSEL: ICC selection sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2 reset is generated by the application during the
pins) ICC session.
– VDD: application board power supply (option- 3. The use of Pin 7 of the ICC connector depends
al, see Note 3) on the Programming Tool architecture. This pin
Notes: must be connected when using most ST Program-
1. If the ICCCLK or ICCDATA pins are only used ming Tools (it is used to monitor the application
as outputs in the application, no signal isolation is power supply). Please refer to the Programming
necessary. As soon as the Programming Tool is Tool manual.
plugged to the board, even if an ICC session is not 4. Pin 9 has to be connected to the OSC1 pin of
in progress, the ICCCLK and ICCDATA pins are the ST7 when the clock is not available in the ap-
not available for the application. If they are used as plication or if the selected clock option is not pro-
inputs by the application, isolation such as a serial grammed in the option byte. ST7 devices with mul-
resistor has to be implemented in case another de- ti-oscillator capability need to have OSC2 ground-
vice forces the signal. Refer to the Programming ed in this case.
Tool documentation for recommended resistor val-
ues.

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR
(See Note 3) HE10 CONNECTOR TYPE

OPTIONAL APPLICATION BOARD

(See Note 4) 9 7 5 3 1

10 8 6 4 2
APPLICATION
RESET SOURCE
See Note 2

10kΩ

APPLICATION CL2 CL1 APPLICATION

POWER SUPPLY See Note 1 I/O
VSS
VDD

ICCSEL

RESET

ICCCLK

ICCDATA
OSC1
OSC2

ST7

16/191
 ST72340, ST72344, ST72345

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection vent any change being made to the memory con-
tent.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec- Warning: Once set, Write/erase protection can
tion which can be applied individually. never be removed. A write-protected flash device
is no longer reprogrammable.
4.5.1 Read out Protection
Write/erase protection is enabled through the
Readout protection, when selected provides a pro- FMP_W bit in the option byte.
tection against program memory content extrac-
tion and against write access to Flash memory.
Even if no protection can be considered as totally 4.6 Register Description
unbreakable, the feature provides a very high level FLASH CONTROL/STATUS REGISTER (FCSR)
of protection for a general purpose microcontroller. Read/Write
Both program and data E2 memory are protected. Reset Value: 000 0000 (00h)
In flash devices, this protection is removed by re- 1st RASS Key: 0101 0110 (56h)
programming the option. In this case, both pro- 2nd RASS Key: 1010 1110 (AEh)
gram and data E2 memory are automatically
erased, and the device can be reprogrammed. 7 0
Read-out protection selection depends on the de-
vice type: 0 0 0 0 0 OPT LAT PGM

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte. Note: This register is reserved for programming
– In ROM devices it is enabled by mask option using ICP, IAP or other programming methods. It
specified in the Option List. controls the XFlash programming and erasing op-
4.5.2 Flash Write/Erase Protection erations. For details on XFlash programming, refer
to the ST7 Flash Programming Reference Manual.
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo- When an EPB or another programming tool is
ry. It does not apply to E2 data. Its purpose is to used (in socket or ICP mode), the RASS keys are
provide advanced security to applications and pre- sent automatically.

17/191
ST72340, ST72344, ST72345

5 DATA EEPROM

5.1 INTRODUCTION 5.2 MAIN FEATURES

The Electrically Erasable Programmable Read ■ Up to 32 Bytes programmed in the same cycle
Only Memory can be used as a non-volatile back- ■ EEPROM mono-voltage (charge pump)
up for storing data. Using the EEPROM requires a
■ Chained erase and programming cycles
basic access protocol described in this chapter.
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Read-out protection
Figure 7. EEPROM Block Diagram

HIGH VOLTAGE
PUMP

EECSR 0 0 0 0 0 0 E2LAT E2PGM

EEPROM
ADDRESS 4 ROW
MEMORY MATRIX
DECODER DECODER
(1 ROW = 32 x 8 BITS)

128 128

4 DATA 32 x 8 BITS
MULTIPLEXER DATA LATCHES

ADDRESS BUS DATA BUS

18/191
 ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP- When E2PGM bit is set by the software, all the
ROM Control/Status register (EECSR). The flow- previous bytes written in the data latches (up to
chart in Figure 8 describes these different memory 32) are programmed in the EEPROM cells. The ef-
access modes. fective high address (row) is determined by the
last EEPROM write sequence. To avoid wrong
Read Operation (E2LAT = 0) programming, the user must take care that all the
The EEPROM can be read as a normal ROM loca- bytes written between two programming sequenc-
tion when the E2LAT bit of the EECSR register is es have the same high address: only the five Least
cleared. Significant Bits of the address can change.
On this device, Data EEPROM can also be used to The programming cycle is fully completed when
execute machine code. Take care not to write to the E2PGM bit is cleared.
the Data EEPROM while executing from it. This Note: Care should be taken during the program-
would result in an unexpected code being execut- ming cycle. Writing to the same memory location
ed. will over-program the memory (logical AND be-
tween the two write access data result) because
Write Operation (E2LAT = 1) the data latches are only cleared at the end of the
To access the write mode, the E2LAT bit has to be programming cycle and by the falling edge of the
set by software (the E2PGM bit remains cleared). E2LAT bit.
When a write access to the EEPROM area occurs, It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8. Data EEPROM Programming Flowchart

READ MODE WRITE MODE

E2LAT = 0 E2LAT = 1
E2PGM = 0 E2PGM = 0

WRITE UP TO 32 BYTES
READ BYTES
IN EEPROM AREA
IN EEPROM AREA
(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1
E2PGM=1 (set by software)

0 E2PGM 1

CLEARED BY HARDWARE

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ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

Figure 9. Data E2PROM Write Operation

⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address

ROW 0 00h...1Fh
DEFINITION 1 20h...3Fh
...
N Nx20h...Nx20h+1Fh

Read operation impossible Read operation possible

Byte 1 Byte 2 Byte 32 Programming cycle

PHASE 1 PHASE 2
Writing data latches Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application Cleared by hardware
E2PGM bit

Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not
be guaranteed.

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 ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING

Wait mode If a read access occurs while E2LAT = 1, then the

data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol- If a write access occurs while E2LAT = 0, then the
ler or when the microcontroller enters Active Halt data on the bus will not be latched.
mode.The DATA EEPROM will immediately enter If a programming cycle is interrupted (by RESET
this mode if there is no programming in progress, action), the integrity of the data in memory will not
otherwise the DATA EEPROM will finish the cycle be guaranteed.
and then enter WAIT mode.
5.6 DATA EEPROM READ-OUT PROTECTION
Active Halt mode The read-out protection is enabled through an op-
Refer to Wait mode. tion bit (see option byte section).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
Halt mode against read-out (including a re-write protection).
The DATA EEPROM immediately enters HALT In Flash devices, when this protection is removed
mode if the microcontroller executes the HALT in- by reprogramming the Option Byte, the entire Pro-
struction. Therefore the EEPROM will stop the gram memory and EEPROM is first automatically
function in progress, and data may be corrupted. erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.

Figure 10. Data EEPROM Programming Cycle

READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE
WRITE OF
DATA
LATCHES tPROG

E2LAT

E2PGM

ALL INTERRUPTS MUST BE MASKED 1) I bit in CC register

Note 1: refer to “Programming of EEPROM data” on page 189

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ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EEC-

SR)
Read/Write
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 E2LAT E2PGM

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress

Note: if the E2PGM bit is cleared during the pro-

gramming cycle, the memory data is not guaran-
teed

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 ST72340, ST72344, ST72345

DATA EEPROM (Cont’d)

Table 3. DATA EEPROM Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

EECSR E2LAT E2PGM

0020h
Reset Value 0 0 0 0 0 0 0 0

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ST72340, ST72344, ST72345

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION 6.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains The six CPU registers shown in Figure 1 are not
six internal registers allowing efficient 8-bit data present in the memory mapping and are accessed
manipulation. by specific instructions.
Accumulator (A)
6.2 MAIN FEATURES The Accumulator is an 8-bit general purpose reg-
■ Enable executing 63 basic instructions ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
■ Fast 8-bit by 8-bit multiply data.
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
■ Two 8-bit index registers These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
■ 16-bit stack pointer manipulation. (The Cross-Assembler generates a
■ Low power HALT and WAIT modes precede instruction (PRE) to indicate that the fol-
■ Priority maskable hardware interrupts lowing instruction refers to the Y register.)
■ Non-maskable software/hardware interrupts The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 11. CPU Registers
7 0
ACCUMULATOR
RESET VALUE = XXh
7 0
X INDEX REGISTER
RESET VALUE = XXh
7 0
Y INDEX REGISTER
RESET VALUE = XXh

15 PCH 8 7 PCL 0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7 0
1 1 I1 H I0 N Z C CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X

15 8 7 0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC) This bit is set and cleared by hardware. This bit in-
Read/Write dicates that the result of the last arithmetic, logical
or data manipulation is zero.
Reset Value: 111x1xxx 0: The result of the last operation is different from
7 0 zero.
1: The result of the last operation is zero.
1 1 I1 H I0 N Z C This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in- Bit 0 = C Carry/borrow.
terrupt masks and four flags representative of the This bit is set and cleared by hardware and soft-
result of the instruction just executed. This register ware. It indicates an overflow or an underflow has
can also be handled by the PUSH and POP in- occurred during the last arithmetic operation.
structions. 0: No overflow or underflow has occurred.
These bits can be individually tested and/or con- 1: An overflow or underflow has occurred.
trolled by specific instructions. This bit is driven by the SCF and RCF instructions
Arithmetic Management Bits and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
Bit 4 = H Half carry. rotate instructions.
This bit is set by hardware when a carry occurs be-
Interrupt Management Bits
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during Bit 5,3 = I1, I0 Interrupt
the same instructions. The combination of the I1 and I0 bits gives the cur-
0: No half carry has occurred. rent interrupt software priority.
1: A half carry has occurred.
Interrupt Software Priority I1 I0
This bit is tested using the JRH or JRNH instruc- Level 0 (main) 1 0
tion. The H bit is useful in BCD arithmetic subrou-
tines. Level 1 0 1
Level 2 0 0
Bit 2 = N Negative.
Level 3 (= interrupt disable) 1 1
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic, These two bits are set/cleared by hardware when
logical or data manipulation. It’s a copy of the re- entering in interrupt. The loaded value is given by
sult 7th bit. the corresponding bits in the interrupt software pri-
0: The result of the last operation is positive or null. ority registers (IxSPR). They can be also set/
1: The result of the last operation is negative cleared by software with the RIM, SIM, IRET,
(that is, the most significant bit is a logic 1). HALT, WFI and PUSH/POP instructions.
This bit is accessed by the JRMI and JRPL instruc- See the interrupt management chapter for more
tions. details.
Bit 1 = Z Zero.

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP) The least significant byte of the Stack Pointer
Read/Write (called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
15 8
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
0 0 0 0 0 0 0 1 fore lost. The stack also wraps in case of an under-
flow.
7 0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
The Stack Pointer is a 16-bit register which is al- at the first location pointed to by the SP. Then the
ways pointing to the next free location in the stack. other registers are stored in the next locations as
It is then decremented after data has been pushed shown in Figure 12.
onto the stack and incremented before data is
popped from the stack (see Figure 12). – When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an – On return from interrupt, the SP is incremented
MCU Reset, or after a Reset Stack Pointer instruc- and the context is popped from the stack.
tion (RSP), the Stack Pointer contains its reset val- A subroutine call occupies two locations and an in-
ue (the SP7 to SP0 bits are set) which is the stack terrupt five locations in the stack area.
higher address.
Figure 12. Stack Manipulation Example
CALL Interrupt PUSH Y POP Y IRET RET
Subroutine Event or RSP

@ 0100h

SP
SP SP
Y
CC CC CC
A A A
X X X
PCH PCH PCH
SP SP
PCL PCL PCL
PCH PCH PCH PCH PCH
SP
@ 01FFh PCL PCL PCL PCL PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

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7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for – External Clock Input (enabled by option byte)
securing the application in critical situations (for – PLL for multiplying the frequency by 8 or 4
example in case of a power brown-out), and re- (enabled by option byte)
ducing the number of external components.
■ Reset Sequence Manager (RSM)
Main features
■ System Integrity Management (SI)
■ Clock Management – Main supply Low voltage detection (LVD) with
– 1 MHz high-accuracy internal RC oscillator reset generation (enabled by option byte)
(enabled by option byte) – Auxiliary Voltage Detector (AVD) with inter-
– 1 to 16 MHz External crystal/ceramic resona- rupt capability for monitoring the main supply
tor (enabled by option byte) (enabled by option byte)
Figure 13. Clock, Reset and Supply Block Diagram
RCCRH/RCCRL Register
MAIN CLOCK fCPU
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 CONTROLLER
WITH REAL TIME
CLOCK(MCC/RTC)

Tunable
RC Oscillator External Clock (0.5-8MHz)
RC Clock (1MHz.)
1MHz
8MHz fOSC2
/2 PLL 1MHz --> 8MHz
/2
DIVIDER PLL 1MHz --> 4MHz 4MHz DIVIDER* PLL Clock 8/4MHz

OSC Option bit PLLx4x8

Option bit
DIV2EN OSC, PLLOFF
Option bit*
OSCRANGE[2:0]
Option bits
OSC1 OSC Crystal OSC (0.5-8MHz)
/2
1-16 MHz DIVIDER
OSC2

*not available if PLLx4 is enabled

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7.1 PHASE LOCKED LOOP When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
The PLL can be used to multiply a 1MHz frequen- clock after a delay of tSTARTUP.
cy from the RC oscillator or the external clock by 4
or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena- When the PLL output signal reaches the operating
bled and the multiplication factor of 4 or 8 is select- frequency, the LOCKED bit in the SICSCR register
ed by 3 option bits. Refer to Table 4 for the PLL is set. Full PLL accuracy (ACCPLL) is reached after
configuration depending on the required frequency a stabilization time of tSTAB (see Figure 14 )
and the application voltage. Refer to Section 15.1 Refer to Section 7.5.4 on page 35 for a description
for the option byte description. of the LOCKED bit in the SICSR register.
Table 4. PLL Configurations Caution: The PLL is not recommended for appli-
cations where timing accuracy is required.
Target Ratio VDD PLL Ratio DIV2
x41) 2.7V - 3.65V x4 OFF
x4 x8 ON
3.3V - 5.5V
x8 x8 OFF
1) For a target ratio of x4 between 3.3V - 3.65V,
this is the recommended configuration.
Figure 14. PLL Output Frequency Timing
Diagram
LOCKED bit set
4/8 x
input
freq.
tSTAB
Output freq.

tLOCK

tSTARTUP

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7.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by tance values must be adjusted according to the
three different source types coming from the multi- selected oscillator.
oscillator block: These oscillators are not stopped during the
■ an external source RESET phase to avoid losing time in the oscillator
■ 4 crystal or ceramic resonator oscillators start-up phase.
■ an internal high-accuracy RC oscillator
Table 5. ST7 Clock Sources
Each oscillator is optimized for a given frequency
Hardware Configuration
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details. ST7

External Clock
OSC1 OSC2
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
EXTERNAL
the ST7 main oscillator may start and, in this con- SOURCE
figuration, could generate an fOSC clock frequency
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
Crystal/Ceramic Resonators

product behaviour must therefore be considered ST7

undefined when the OSC pins are left unconnect- OSC1 OSC2
ed.
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive CL1 CL2
the OSC1 pin while the OSC2 pin is tied to ground. LOAD
CAPACITORS
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
Internal RC Oscillator

the ST7. The selection within a list of 4 oscillators ST7

OSC1 OSC2
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 15.1 on page 181 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-

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MULTI-OSCILLATOR (Cont’d)
Internal RC Oscillator 7.3 REGISTER DESCRIPTION
The device contains a high-precision internal RC
RC CONTROL REGISTER (RCCRH)
oscillator. It must be calibrated to obtain the fre-
Read / Write
quency required in the application. This is done by
Reset Value: 1111 1111 (FFh)
software writing a calibration value in the RCCRH
and RCCRL Registers.
7 0
Whenever the microcontroller is reset, the RCCR
returns to its default value (FF 03h), i.e. each time
the device is reset, the calibration value must be CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
loaded in the RCCRH and RCCRL registers. Pre-
defined calibration values are stored in XFLASH
for 3 and 5V VDD supply voltages at 25°C, as Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
shown in the following table. justment Bits
RCCR Conditions Address
VDD=5V RC CONTROL REGISTER (RCCRL)
RCCR0 TA=25°C BEE0, BEE1 Read / Write
fRC=1MHz Reset Value: 0000 0011 (03h)
VDD=3V
RCCR1 TA=25°C BEE4, BEE5 7 0
fRC=1MHz
0 0 0 0 0 0 CR1 CR0
Note:
– To improve clock stability, it is recommended to
place a decoupling capacitor between the VDD Bits 7:2 = Reserved, must be kept cleared.
and VSS pins.
Bits 1:0 = CR[1:0] RC Oscillator Frequency Ad-
– These two 10-bit values are systematically pro- justment Bits
grammed by ST, including on FASTROM devic- This 10-bit value must be written immediately after
es. Consequently, customers intending to use reset to adjust the RC oscillator frequency in order
FASTROM service must not use these address- to obtain the specified accuracy. The application
es. can store the correct value for each voltage range
– RCCR0 and RCCR1 calibration values will be in EEPROM and write it to this register at start-up.
erased if the read-out protection bit is reset after 0000h = maximum available frequency
it has been set. See “Memory Protection” on 03FFh = lowest available frequency
page 17. Note: To tune the oscillator, write a series of differ-
Caution: If the voltage or temperature conditions ent values in the register until the correct frequen-
change in the application, the frequency may need cy is reached. The fastest method is to use a di-
to be recalibrated. chotomy starting with 200h.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.

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7.4 RESET SEQUENCE MANAGER (RSM)

7.4.1 Introduction of the external oscillator used in the application
The reset sequence manager includes three RE- (see Section 15.1 on page 181).
SET sources as shown in Figure 16: The RESET vector fetch phase duration is 2 clock
■ External RESET source pulse cycles.
■ Internal LVD RESET (Low Voltage Detection) Figure 15. RESET Sequence Phases
■ Internal WATCHDOG RESET

Note: A reset can also be triggered following the

detection of an illegal opcode or prebyte code. Re- RESET
fer to Section 12.2.1 on page 149 for further de-
INTERNAL RESET FETCH
tails. Active Phase
256 or 4096 CLOCK CYCLES VECTOR
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad- 7.4.2 Asynchronous External RESET pin
dresses FFFEh-FFFFh in the ST7 memory map. The RESET pin is both an input and an open-drain
The basic RESET sequence consists of 3 phases output with integrated RON weak pull-up resistor.
as shown in Figure 15: This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
■ Active Phase depending on the RESET source
low by external circuitry to reset the device. See
■ 256 or 4096 CPU clock cycle delay (selected by “ELECTRICAL CHARACTERISTICS” on
option byte) page 152 for more details.
■ RESET vector fetch A RESET signal originating from an external
The 256 or 4096 CPU clock cycle delay allows the source must have a duration of at least th(RSTL)in in
oscillator to stabilise and ensures that recovery order to be recognized (see Figure 17). This de-
has taken place from the Reset state. The shorter tection is asynchronous and therefore the MCU
or longer clock cycle delay should be selected by can enter reset state even in HALT mode.
option byte to correspond to the stabilization time
Figure 16. Reset Block Diagram

VDD

RON

Filter INTERNAL
RESET
RESET

WATCHDOG RESET
PULSE
ILLEGAL OPCODE RESET 1)
GENERATOR
LVD RESET

Note 1: See “Illegal Opcode Reset” on page 149. for more details on illegal opcode reset conditions.

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which 7.4.4 Internal Low Voltage Detector (LVD)
plays a major role in EMS performance. In a noisy RESET
environment, it is recommended to follow the Two different RESET sequences caused by the in-
guidelines mentioned in the electrical characteris- ternal LVD circuitry can be distinguished:
tics section.
■ Power-On RESET
If the external RESET pulse is shorter than
■ Voltage Drop RESET
tw(RSTL)out (see short ext. Reset in Figure 17), the
signal on the RESET pin may be stretched. Other- The device RESET pin acts as an output that is
wise the delay will not be applied (see long ext. pulled low when VDD<VIT+ (rising edge) or
Reset in Figure 17). Starting from the external RE- VDD<VIT- (falling edge) as shown in Figure 17.
SET pulse recognition, the device RESET pin acts The LVD filters spikes on VDD larger than tg(VDD) to
as an output that is pulled low during at least avoid parasitic resets.
tw(RSTL)out.
Note:
7.4.3 External Power-On RESET
It is recommended to make sure that the VDD sup-
If the LVD is disabled by option byte, to start up the ply voltage rises monotonously when the device is
microcontroller correctly, the user must ensure by exiting from Reset, to ensure the application func-
means of an external reset circuit that the reset tions properly.
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency. 7.4.5 Internal Watchdog RESET
(see “OPERATING CONDITIONS” on page 154) The RESET sequence generated by a internal
A proper reset signal for a slow rising VDD supply Watchdog counter overflow is shown in Figure 17.
can generally be provided by an external RC net- Starting from the Watchdog counter underflow, the
work connected to the RESET pin. device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 17. RESET Sequences
VDD

VIT+(LVD)
VIT-(LVD)

LVD SHORT EXT. LONG EXT. WATCHDOG

RESET RESET RESET RESET
RUN RUN ACTIVE
RUN ACTIVE
RUN ACTIVE
RUN
ACTIVE PHASE PHASE PHASE PHASE

tw(RSTL)out tw(RSTL)out

th(RSTL)in th(RSTL)in tw(RSTL)out

DELAY
EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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7.5 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains The LVD is an optional function which can be se-
the Low Voltage Detector (LVD) and Auxiliary Volt- lected by option byte.
age Detector (AVD) functions. It is managed by
the SICSR register.
Note: LVD Threshold Configuration
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re- The voltage threshold can be configured by option
fer to Section 12.2.1 on page 149 for further de- byte to be low, medium or high. The configuration
tails. should be chosen depending on the fOSC and VDD
parameters in the application. When correctly con-
7.5.1 Low Voltage Detector (LVD) figured, the LVD ensures safe power-on and pow-
The Low Voltage Detector function (LVD) gener- er-off conditions for the microcontroller without us-
ates a static reset when the VDD supply voltage is ing any external components.
below a VIT- reference value. This means that it To determine which LVD thresholds to use:
secures the power-up as well as the power-down
keeping the ST7 in reset. – Define the minimum operating voltage for the ap-
plication VAPP(min)
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order – Refer to the Electrical Characteristics section to
to avoid a parasitic reset when the MCU starts run- get the minimum operating voltage for the MCU
ning and sinks current on the supply (hysteresis). at the application frequency VDD(min) .
The LVD Reset circuitry generates a reset when – Select the LVD threshold that ensures that the
VDD is below: internal RESET is released at VAPP(min) and ac-
tivated at VDD(MCUmin)
– VIT+ when VDD is rising
– VIT- when VDD is falling During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
The LVD function is illustrated in Figure 18. other devices.

Figure 18. Low Voltage Detector vs Reset

VDD

Vhys
VIT+(LVD)
VIT-((LVD)

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.5.2 Auxiliary Voltage Detector (AVD) old.
The AVD is used to provide the application with an In the case of a drop in voltage below VIT-(PVD), the
early warning of a drop in voltage. If enabled, an AVDF flag is set and an interrupt request is issued.
interrupt can be generated allowing software to If VDD rises above the VIT+(AVD) threshold voltage
shut down safely before the LVD resets the micro- the AVDF bit is cleared automatically by hardware.
controller. See Figure 19. No interrupt is generated, and therefore software
The AVD function is active only if the LVD is ena- should poll the AVDF bit to detect when the volt-
bled through the option byte (see Section 15.1 on age has risen, and resume normal processing.
page 181). The activation level of the AVD is fixed
at around 0.5 mV above the selected LVD thresh-

Figure 19. Using the AVD to Monitor VDD

VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhys
VIT+(AVD)
VIT-(AVD)

VIT-(LVD)

AVDF bit 0 1 0 1 RESET VALUE

AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS

LVD RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.5.3 Low Power Modes Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
Mode Description ed by the LVD block. It is set by hardware (LVD re-
No effect on SI. AVD interrupts cause the set) and cleared by software (writing zero). See
WAIT WDGRF flag description for more details. When
device to exit from Wait mode.
HALT The SICSR register is frozen. the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
7.5.3.1 Interrupts Bit 3 = LOCKED PLL Locked Flag
The AVD interrupt event generates an interrupt if This bit is set and cleared by hardware. It is set au-
the corresponding AVDIE Bit is set and the inter- tomatically when the PLL reaches its operating fre-
rupt mask in the CC register is reset (RIM instruc- quency.
tion). 0: PLL not locked
1: PLL locked
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Bits 2:1 = Reserved, must be kept cleared.

AVD event AVDF AVDIE Yes No

Bit 0 = WDGRF Watchdog reset flag
7.5.4 Register Description This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
SYSTEM INTEGRITY (SI) CONTROL/STATUS
ware (watchdog reset) and cleared by software
REGISTER (SICSR)
(writing zero) or an LVD Reset (to ensure a stable
Read/Write cleared state of the WDGRF flag when CPU
Reset Value: 000x 000x (xxh) starts).
Combined with the LVDRF flag information, the
7 0 flag description is given by the following table.

PDVD AVD RESET Sources LVDRF WDGRF

LVD LOC WDG
0 0 0
IE F RF KED RF External RESET pin 0 0
Watchdog 0 1
Bit 7 = Reserved, must be kept cleared. LVD 1 X

Bit 6 = AVDIE Voltage Detector interrupt enable Application notes

This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag The LVDRF flag is not cleared when another RE-
goes from 0 to 1. The pending interrupt information SET type occurs (external or watchdog), the
is automatically cleared when software enters the LVDRF flag remains set to keep trace of the origi-
AVD interrupt routine. nal failure.
0: PDVD interrupt disabled In this case, a watchdog reset can be detected by
1: PDVD interrupt enabled software while an external reset can not.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
Bit 5 = AVDF Voltage Detector flag be used in the application.
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit goes from 0 to 1. Refer
to Figure 19 and to Section 7.5.2 for additional de-
tails.
0: VDD over VIT+(AVD) threshold
1: VDD under VIT-(AVD) threshold

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8 INTERRUPTS

8.1 INTRODUCTION When an interrupt request has to be serviced:

The ST7 enhanced interrupt management pro- – Normal processing is suspended at the end of
vides the following features: the current instruction execution.
■ Hardware interrupts
– The PC, X, A and CC registers are saved onto
the stack.
■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
with flexible interrupt priority and level of the serviced interrupt vector.
management:
– The PC is then loaded with the interrupt vector of
– Up to 4 software programmable nesting levels the interrupt to service and the first instruction of
– Up to 16 interrupt vectors fixed by hardware the interrupt service routine is fetched (refer to
– 2 non maskable events: RESET, TRAP “Interrupt Mapping” table for vector addresses).
This interrupt management is based on: The interrupt service routine should end with the
– Bit 5 and bit 3 of the CPU CC register (I1:0), IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
– Fixed interrupt vector addresses located at the the I1 and I0 bits will be restored from the stack
high addresses of the memory map (FFE0h to and the program in the previous level will resume.
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest- Table 6. Interrupt Software Priority Levels
ed) ST7 interrupt controller. Interrupt software priority Level I1 I0
Level 0 (main) Low 1 0
8.2 MASKING AND PROCESSING FLOW Level 1 0 1
The interrupt masking is managed by the I1 and I0 Level 2 0 0
bits of the CC register and the ISPRx registers Level 3 (= interrupt disable) High 1 1
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 20
Figure 20. Interrupt Processing Flowchart

PENDING Y Y
RESET TRAP
INTERRUPT

Interrupt has the same or a N

N lower software priority
than current one
I1:0
Interrupt has a higher

FETCH NEXT THE INTERRUPT

than current one
software priority

INSTRUCTION STAYS PENDING

Y
“IRET”

RESTORE PC, X, A, CC EXECUTE

FROM STACK INSTRUCTION STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont’d)
Servicing Pending Interrupts registers (except for RESET), the corresponding
As several interrupts can be pending at the same vector is loaded in the PC register and the I1 and
time, the interrupt to be taken into account is deter- I0 bits of the CC are set to disable interrupts (level
mined by the following two-step process: 3). These sources allow the processor to exit
HALT mode.
– the highest software priority interrupt is serviced,
■ TRAP (Non Maskable Software Interrupt)
– if several interrupts have the same software pri-
This software interrupt is serviced when the TRAP
ority then the interrupt with the highest hardware
instruction is executed. It will be serviced accord-
priority is serviced first.
ing to the flowchart in Figure 20.
Figure 21 describes this decision process. ■ RESET

Figure 21. Priority Decision Process The RESET source has the highest priority in the
ST7. This means that the first current routine has
PENDING
the highest software priority (level 3) and the high-
INTERRUPTS
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Same Different
SOFTWARE Maskable interrupt vector sources can be serviced
PRIORITY if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
HIGHEST SOFTWARE and I0 in CC register). If any of these two condi-
PRIORITY SERVICED tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST HARDWARE ■ External Interrupts
PRIORITY SERVICED
External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv-
When an interrupt request is not serviced immedi- ity is software selectable through the External In-
ately, it is latched and then processed when its terrupt Control register (EICR).
software priority combined with the hardware pri- External interrupt triggered on edge will be latched
ority becomes the highest one. and the interrupt request automatically cleared
upon entering the interrupt service routine.
Notes: If several input pins of a group connected to the
1. The hardware priority is exclusive while the soft- same interrupt line are selected simultaneously,
ware one is not. This allows the previous process these will be logically ORed.
to succeed with only one interrupt. ■ Peripheral Interrupts
2. TLI, RESET and TRAP can be considered as
having the highest software priority in the decision Usually the peripheral interrupts cause the MCU to
process. exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter-
Different Interrupt Vector Sources rupt occurs when a specific flag is set in the pe-
ripheral status registers and if the corresponding
Two interrupt source types are managed by the
enable bit is set in the peripheral control register.
ST7 interrupt controller: the non-maskable type
The general sequence for clearing an interrupt is
(RESET, TRAP) and the maskable type (external
based on an access to the status register followed
or from internal peripherals).
by a read or write to an associated register.
Non-Maskable Sources Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
These sources are processed regardless of the serviced) will therefore be lost if the clear se-
state of the I1 and I0 bits of the CC register (see quence is executed.
Figure 20). After stacking the PC, X, A and CC

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INTERRUPTS (Cont’d)

8.3 INTERRUPTS AND LOW POWER MODES 8.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT The following Figure 22 and Figure 23 show two
low power mode. On the contrary, only external different interrupt management modes. The first is
and other specified interrupts allow the processor called concurrent mode and does not allow an in-
to exit from the HALT modes (see column “Exit terrupt to be interrupted, unlike the nested mode in
from HALT” in “Interrupt Mapping” table). When Figure 23. The interrupt hardware priority is given
several pending interrupts are present while exit- in this order from the lowest to the highest: MAIN,
ing HALT mode, the first one serviced can only be IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
an interrupt with exit from HALT mode capability given for each interrupt.
and it is selected through the same decision proc- Warning: A stack overflow may occur without no-
ess shown in Figure 21. tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
TRAP

SOFTWARE
I1 I0
IT2

IT1

IT4

IT3

IT0

PRIORITY
LEVEL
HARDWARE PRIORITY

USED STACK = 10 BYTES

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 3 1 1
IT2 3 1 1
IT3 3 1 1
RIM
IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

Figure 23. Nested Interrupt Management

TRAP

SOFTWARE
I1 I0
IT0
IT2

IT1

IT4

IT3

PRIORITY
LEVEL
USED STACK = 20 BYTES
HARDWARE PRIORITY

TRAP 3 1 1
IT0 3 1 1
IT1 IT1 2 0 0
IT2 IT2 1 0 1
IT3 3 1 1
RIM
IT4 IT4 3 1 1
MAIN MAIN 3/0
11 / 10 10

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INTERRUPTS (Cont’d)

8.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

INTERRUPT SOFTWARE PRIORITY REGIS-
Read/Write
TERS (ISPRX)
Reset Value: 111x 1010 (xAh)
Read/Write (bit 7:4 of ISPR3 are read only)
7 0 Reset Value: 1111 1111 (FFh)
7 0
1 1 I1 H I0 N Z C
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft- ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
ware priority.
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Interrupt Software Priority Level I1 I0
Level 0 (main) Low 1 0
ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) High 1 1 These four registers contain the interrupt software
priority of each interrupt vector.
These two bits are set/cleared by hardware when – Each interrupt vector (except RESET and TRAP)
entering in interrupt. The loaded value is given by has corresponding bits in these registers where
the corresponding bits in the interrupt software pri- its own software priority is stored. This corre-
ority registers (ISPRx). spondence is shown in the following table.
They can be also set/cleared by software with the
Vector address ISPRx bits
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction FFFBh-FFFAh I1_0 and I0_0 bits*
Set” table). FFF9h-FFF8h I1_1 and I0_1 bits
*Note: TRAP and RESET events can interrupt a ... ...
level 3 program. FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).

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INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction New Description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 (level 3) I1:0=11 ?
JRNM Jump if I1:0<>11 I1:0<>11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.

Table 8. Interrupt Mapping

Exit
Source Register Priority Address
N° Description from
Block Label Order Vector
HALT1
RESET Reset Highest yes FFFEh-FFFFh
N/A
TRAP/ICD Software or ICD Interrupt Priority no FFFCh-FFFDh
0 AWU Auto Wake Up Interrupt AWUCSR yes FFFAh-FFFBh
1 MCC/RTC RTC Time base interrupt MCCSR yes FFF8h-FFF9h
2 ei0 External Interrupt Port PA3, PE1 N/A yes FFF6h-FFF7h
3 ei1 External Interrupt Port PF2:0 N/A yes FFF4h-FFF5h
4 ei2 External Interrupt Port PB3:0 N/A yes FFF2h-FFF3h
5 ei3 External Interrupt Port PB4 N/A yes FFF0h-FFF1h
6 I2C3SNS I2C3SNS Address 3 Interrupt no FFEEh-FFEFh
I2C3SSR
7 I2C3SNS I2C3SNS Address 1 & 2 Interrupt no FFECh-FFEDh
8 SPI SPI Peripheral Interrupts SPISR yes2 FFEAh-FFEBh
9 TIMER A TIMER A Peripheral Interrupts TASR no FFE8h-FFE9h
10 TIMER B TIMER B Peripheral Interrupts TBSR no FFE6h-FFE7h
11 SCI SCI Peripheral Interrupt SCISR no FFE4h-FFE5h
12 AVD Auxiliary Voltage Detector Interrupt SICSR Lowest no FFE2h-FFE3h
13 I2C I2C Peripheral Interrupt I2CSRx Priority no FFE0h-FFE1h

Notes:
1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from
ACTIVE-HALT mode only and AWU interrupt which exits from AWUFH mode only.
2. Exit from HALT possible when SPI is in slave mode.

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INTERRUPTS (Cont’d)

8.6 EXTERNAL INTERRUPTS

8.6.1 I/O Port Interrupt Sensitivity ■ Falling edge and low level
The external interrupt sensitivity is controlled by ■ Rising edge and high level (only for ei0 and ei2)
the IPA, IPB and ISxx bits of the EICR register To guarantee correct functionality, the sensitivity
(Figure 24). This control allows to have up to 4 fully bits in the EICR register can be modified only
independent external interrupt source sensitivities. when the I1 and I0 bits of the CC register are both
Each external interrupt source can be generated set to 1 (level 3). This means that interrupts must
on four (or five) different events on the pin: be disabled before changing sensitivity.
■ Falling edge The pending interrupts are cleared by writing a dif-
■ Rising edge ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
■ Falling and rising edge

Figure 24. External Interrupt Control bits

PORT A3, E1 INTERRUPTS EICR

IS20 IS21
PAOR.3
PADDR.3 PA3
SENSITIVITY ei0 INTERRUPT SOURCE
PA3
CONTROL PE1

IPA BIT

PORT F [2:0] INTERRUPTS EICR

IS20 IS21
PFOR.2
PFDDR.2
SENSITIVITY PF2
PF2 PF1 ei1 INTERRUPT SOURCE
CONTROL
PF0

PORT B [3:0] INTERRUPTS EICR

IS10 IS11
PBOR.3
PBDDR.3
SENSITIVITY PB3
PB3 ei2 INTERRUPT SOURCE
CONTROL PB2
PB1
PB0
IPB BIT

PORT B4 INTERRUPT EICR

IS10 IS11
PBOR.4
PBDDR.4 ei3 INTERRUPT SOURCE
SENSITIVITY PB4
PB4 CONTROL

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INTERRUPTS (Cont’d)

8.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
Reset Value: 0000 0000 (00h) The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
7 0

IS11 IS10 IPB IS21 IS20 IPA 0 0

- ei0 (port A3, port E1)

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] External Interrupt Sensitivity
bits, is applied to the following external interrupts: IS21 IS20
- ei2 (port B3..0) IPA bit =0 IPA bit =1
Falling edge & Rising edge
External Interrupt Sensitivity 0 0
low level & high level
IS11 IS10
IPB bit =0 IPB bit =1 0 1 Rising edge only Falling edge only
Falling edge & Rising edge 1 0 Falling edge only Rising edge only
0 0
low level & high level 1 1 Rising and falling edge
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
- ei1 (port F2..0)
IS21 IS20 External Interrupt Sensitivity
- ei3 (port B4)
0 0 Falling edge & low level
IS11 IS10 External Interrupt Sensitivity 0 1 Rising edge only
0 0 Falling edge & low level 1 0 Falling edge only
0 1 Rising edge only 1 1 Rising and falling edge
1 0 Falling edge only
1 1 Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3). Bit 2 = IPA Interrupt polarity for ports A3 and E1
This bit is used to invert the sensitivity of the port
Bit 5 = IPB Interrupt polarity for port B A3 and E1 external interrupts. It can be set and
This bit is used to invert the sensitivity of the port B cleared by software only when I1 and I0 of the CC
[3:0] external interrupts. It can be set and cleared register are both set to 1 (level 3).
by software only when I1 and I0 of the CC register 0: No sensitivity inversion
are both set to 1 (level 3). 1: Sensitivity inversion
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.

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INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
ei1 ei0 MCC + SI AWU
0024h ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
Reset Value 1 1 1 1 1 1 1 1
I2C3SNS I2C3SNS ei3 ei2
0025h ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Reset Value 1 1 1 1 1 1 1 1
SCI TIMER B TIMER A SPI
0026h ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Reset Value 1 1 1 1 1 1 1 1
I2C AVD
0027h ISPR3 I1_13 I0_13 I1_12 I0_12
Reset Value 1 1 1 1 1 1 1 1
EICR IS11 IS10 IPB IS21 IS20 IPA
0028h
Reset Value 0 0 0 0 0 0 0 0

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9 POWER SAVING MODES

9.1 INTRODUCTION 9.2 SLOW MODE

To give a large measure of flexibility to the applica- This mode has two targets:
tion in terms of power consumption, five main pow- – To reduce power consumption by decreasing the
er saving modes are implemented in the ST7 (see internal clock in the device,
Figure 25):
– To adapt the internal clock frequency (fCPU) to
■ Slow
the available supply voltage.
■ Wait (and Slow-Wait)
SLOW mode is controlled by three bits in the
■ Active Halt
MCCSR register: the SMS bit which enables or
■ Auto Wake up From Halt (AWUFH) disables Slow mode and two CPx bits which select
■ Halt the internal slow frequency (fCPU).
After a RESET the normal operating mode is se- In this mode, the master clock frequency (fOSC2)
lected by default (RUN mode). This mode drives can be divided by 2, 4, 8 or 16. The CPU and pe-
the device (CPU and embedded peripherals) by ripherals are clocked at this lower frequency
means of a master clock which is based on the (fCPU).
main oscillator frequency divided or multiplied by 2 Note: SLOW-WAIT mode is activated by entering
(fOSC2). WAIT mode while the device is in SLOW mode.
From RUN mode, the different power saving Figure 26. SLOW Mode Clock Transitions
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator fOSC2/2 fOSC2/4 fOSC2
status. fCPU

Figure 25. Power Saving Mode Transitions

fOSC2

High
MCCSR

CP1:0 00 01

RUN SMS

SLOW NORMAL RUN MODE

NEW SLOW REQUEST
FREQUENCY
REQUEST
WAIT

SLOW WAIT

ACTIVE HALT

AUTO WAKE UP FROM HALT

HALT

Low
POWER CONSUMPTION

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POWER SAVING MODES (Cont’d)

9.3 WAIT MODE Figure 27. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con- OSCILLATOR ON
sumption mode by stopping the CPU. PERIPHERALS ON
This power saving mode is selected by calling the WFI INSTRUCTION
CPU OFF
‘WFI’ instruction. I[1:0] BITS 10
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in N
RESET
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the Y
starting address of the interrupt or Reset service N
INTERRUPT
routine.
The MCU will remain in WAIT mode until a Reset Y
or an Interrupt occurs, causing it to wake up. OSCILLATOR ON
Refer to Figure 27. PERIPHERALS OFF
CPU ON
I[1:0] BITS 10

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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POWER SAVING MODES (Cont’d)

9.4 HALT MODE Figure 29. HALT Mode Flow-chart

The HALT mode is the lowest power consumption HALT INSTRUCTION
mode of the MCU. It is entered by executing the (MCCSR.OIE=0)
‘HALT’ instruction when the OIE bit of the Main (AWUCSR.AWUEN=0)
Clock Controller Status register (MCCSR) is
cleared (see Section 11.2 on page 65 for more de- WATCHDOG
ENABLE
tails on the MCCSR register) and when the
0 DISABLE
AWUEN bit in the AWUCSR register is cleared. WDGHALT 1)
The MCU can exit HALT mode on reception of ei- 1
ther a specific interrupt (see Table 8, “Interrupt
Mapping,” on page 40) or a RESET. When exiting WATCHDOG OSCILLATOR OFF
HALT mode by means of a RESET or an interrupt, RESET PERIPHERALS 2) OFF
the oscillator is immediately turned on and the 256 CPU OFF
or 4096 CPU cycle delay is used to stabilize the I[1:0] BITS 10
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29). N
RESET
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts. Y
N
Therefore, if an interrupt is pending, the MCU INTERRUPT 3)
wakes up immediately.
In HALT mode, the main oscillator is turned off Y OSCILLATOR ON
causing all internal processing to be stopped, in- PERIPHERALS OFF
cluding the operation of the on-chip peripherals. CPU ON
All peripherals are not clocked except the ones I[1:0] BITS XX 4)
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla- 256 OR 4096 CPU CLOCK
tor). CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op- OSCILLATOR ON
tion bit of the option byte. The HALT instruction PERIPHERALS ON
when executed while the Watchdog system is en- CPU ON
abled, can generate a Watchdog RESET (see I[1:0] BITS XX 4)
Section 11.1 on page 58 for more details).
Figure 28. HALT Timing Overview FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU Notes:
RUN HALT CYCLE DELAY RUN
1. WDGHALT is an option bit. See option byte sec-
RESET tion for more details.
OR 2. Peripheral clocked with an external clock source
HALT INTERRUPT can still be active.
INSTRUCTION FETCH 3. Only some specific interrupts can exit the MCU
[MCCSR.OIE=0] VECTOR from HALT mode (such as external interrupt). Re-
fer to Table 8, “Interrupt Mapping,” on page 40 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.

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POWER SAVING MODES (Cont’d)

Halt Mode Recommendations 9.5 ACTIVE-HALT MODE
– Make sure that an external event is available to ACTIVE-HALT mode is the lowest power con-
wake up the microcontroller from Halt mode. sumption mode of the MCU with a real time clock
– When using an external interrupt to wake up the available. It is entered by executing the ‘HALT’ in-
microcontroller, reinitialize the corresponding I/O struction when MCC/RTC interrupt enable flag
as “Input Pull-up with Interrupt” before executing (OIE bit in MCCSR register) is set and when the
the HALT instruction. The main reason for this is AWUEN bit in the AWUCSR register is cleared
that the I/O may be wrongly configured due to ex- (See “Register Description” on page 51.)
ternal interference or by an unforeseen logical
condition. MCCSR Power Saving Mode entered when HALT
OIE bit instruction is executed
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau- 0 HALT mode
tionary measure. 1 ACTIVE-HALT mode
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a The MCU can exit ACTIVE-HALT mode on recep-
program counter failure, it is advised to clear all tion of the RTC interrupt and some specific inter-
occurrences of the data value 0x8E from memo- rupts (see Table 8, “Interrupt Mapping,” on page
ry. For example, avoid defining a constant in 40) or a RESET. When exiting ACTIVE-HALT
ROM with the value 0x8E. mode by means of a RESET a 4096 or 256 CPU
– As the HALT instruction clears the interrupt mask cycle delay occurs (depending on the option byte).
in the CC register to allow interrupts, the user After the start up delay, the CPU resumes opera-
may choose to clear all pending interrupt bits be- tion by servicing the interrupt or by fetching the re-
fore executing the HALT instruction. This avoids set vector which woke it up (see Figure 31).
entering other peripheral interrupt routines after When entering ACTIVE-HALT mode, the I[1:0] bits
executing the external interrupt routine corre- in the CC register are cleared to enable interrupts.
sponding to the wake-up event (reset or external Therefore, if an interrupt is pending, the MCU
interrupt). wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as active halt is enabled, executing
a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.

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POWER SAVING MODES (Cont’d)

Figure 30. ACTIVE-HALT Timing Overview Notes:
1. This delay occurs only if the MCU exits
ACTIVE 256 OR 4096 CYCLE ACTIVE-HALT mode by means of a RESET.
RUN HALT DELAY (AFTER RESET) RUN
2. Peripheral clocked with an external clock
RESET
source can still be active.
OR 3. Only the RTC interrupt and some specific inter-
HALT
INSTRUCTION
INTERRUPT FETCH rupts can exit the MCU from ACTIVE-HALT
(Active Halt enabled) VECTOR mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 40 for
more details.
Figure 31. ACTIVE-HALT Mode Flow-chart
4. Before servicing an interrupt, the CC register is
HALT INSTRUCTION OSCILLATOR ON pushed on the stack. The I[1:0] bits in the CC
PERIPHERALS 2) OFF register are set to the current software priority
(MCCSR.OIE=1)
CPU OFF level of the interrupt routine and restored when
(AWUCSR.AWUEN=0)
I[1:0] BITS 10 the CC register is popped.

N
RESET

N Y
INTERRUPT 3)
OSCILLATOR ON
Y PERIPHERALS OFF
CPU ON
I[1:0] BITS XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

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POWER SAVING MODES (Cont’d)

9.6 AUTO WAKE UP FROM HALT MODE it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
Auto Wake Up From Halt (AWUFH) mode is simi- flag and its associated interrupt are cleared by
lar to Halt mode with the addition of an internal RC software reading the AWUCSR register.
oscillator for wake-up. Compared to ACTIVE-
HALT mode, AWUFH has lower power consump- To compensate for any frequency dispersion of
tion because the main clock is not kept running, the AWU RC oscillator, it can be calibrated by
but there is no accurate realtime clock available. measuring the clock frequency fAWU_RC and then
calculating the right prescaler value. Measurement
It is entered by executing the HALT instruction mode is enabled by setting the AWUM bit in the
when the AWUEN bit in the AWUCSR register has AWUCSR register in Run mode. This connects in-
been set and the OIE bit in the MCCSR register is ternally fAWU_RC to the ICAP2 input of the 16-bit
cleared (see Section 11.2 on page 65 for more de- timer A, allowing the fAWU_RC to be measured us-
tails). ing the main oscillator clock as a reference time-
base.
Figure 32. AWUFH Mode Block Diagram
Similarities with Halt mode
AWU RC The following AWUFH mode behaviour is the
oscillator same as normal Halt mode:
to Timer input capture – The MCU can exit AWUFH mode by means of
fAWU_RC any interrupt with exit from Halt capability or a re-
set (see Section 9.4 "HALT MODE" on page 46).
– When entering AWUFH mode, the I[1:0] bits in
AWUFH the CC register are forced to 10b to enable inter-
AWUFH interrupt rupts. Therefore, if an interrupt is pending, the
/64 prescaler MCU wakes up immediately.
divider
/1 .. 255 – In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
As soon as HALT mode is entered, and if the
which get their clock supply from another clock
AWUEN bit has been set in the AWUCSR register,
generator (such as an external or auxiliary oscil-
the AWU RC oscillator provides a clock signal
lator like the AWU oscillator).
(fAWU_RC). Its frequency is divided by a fixed divid-
er and a programmable prescaler controlled by the – The compatibility of Watchdog operation with
AWUPR register. The output of this prescaler pro- AWUFH mode is configured by the WDGHALT
vides the delay time. When the delay has elapsed option bit in the option byte. Depending on this
the AWUF flag is set by hardware and an interrupt setting, the HALT instruction when executed
wakes-up the MCU from Halt mode. At the same while the Watchdog system is enabled, can gen-
time the main oscillator is immediately turned on erate a Watchdog RESET.
and a 256 or 4096 cycle delay is used to stabilize
Figure 33. AWUF Halt Timing Diagram
tAWU

RUN MODE HALT MODE 256 or 4096 tCPU RUN MODE

fCPU

fAWU_RC
Clear
by software
AWUFH interrupt

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POWER SAVING MODES (Cont’d)

Figure 34. AWUFH Mode Flow-chart Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT INSTRUCTION
(MCCSR.OIE=0)
2. Peripheral clocked with an external clock source
(AWUCSR.AWUEN=1)
can still be active.
3. Only an AWUFH interrupt and some specific in-
ENABLE terrupts can exit the MCU from HALT mode (such
WATCHDOG as external interrupt). Refer to Table 8, “Interrupt
Mapping,” on page 40 for more details.
0 DISABLE
WDGHALT 1) 4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
1 ister are set to the current software priority level of
AWU RC OSC ON the interrupt routine and recovered when the CC
WATCHDOG MAIN OSC OFF register is popped.
RESET PERIPHERALS 2) OFF
CPU OFF
I[1:0] BITS 10

N
RESET

N Y
INTERRUPT 3)
AWU RC OSC OFF
Y MAIN OSC ON
PERIPHERALS OFF
CPU ON
I[1:0] BITS XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

AWU RC OSC OFF

MAIN OSC ON
PERIPHERALS ON
CPU ON
I[1:0] BITS XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

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POWER SAVING MODES (Cont’d)

9.6.0.1 Register Description
AWUFH CONTROL/STATUS REGISTER AWUFH PRESCALER REGISTER (AWUPR)
(AWUCSR) Read/Write
Read/Write (except bit 2 read only) Reset Value: 1111 1111 (FFh)
Reset Value: 0000 0000 (00h)
7 0
7 0
AWU AWU AWU AWU AWU AWU AWU AWU
AWU AWU AWU PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
0 0 0 0 0
F M EN
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
Bits 7:3 = Reserved. These 8 bits define the AWUPR Dividing factor (as
explained below:
Bit 2= AWUF Auto Wake Up Flag AWUPR[7:0] Dividing factor
This bit is set by hardware when the AWU module 00h Forbidden (See note)
generates an interrupt and cleared by software on
01h 1
reading AWUCSR.
0: No AWU interrupt occurred ... ...
1: AWU interrupt occurred FEh 254
FFh 255
Bit 1= AWUM Auto Wake Up Measurement In AWU mode, the period that the MCU stays in
This bit enables the AWU RC oscillator and con-
Halt Mode (tAWU in Figure 33) is defined by
nects internally its output to the ICAP2 input of 16-
bit timer A. This allows the timer to be used to 1
t = 64 × AWUPR × -------------------------- + t
measure the AWU RC oscillator dispersion and AWU f
AWURC
RCSTRT
then compensate this dispersion by providing the
right value in the AWUPR register. This prescaler register can be programmed to
0: Measurement disabled modify the time that the MCU stays in Halt mode
1: Measurement enabled before waking up automatically.
Note: If 00h is written to AWUPR, depending on
Bit 0 = AWUEN Auto Wake Up From Halt Enabled the product, an interrupt is generated immediately
This bit enables the Auto Wake Up From Halt fea- after a HALT instruction, or the AWUPR remains
ture: once HALT mode is entered, the AWUFH unchanged.
wakes up the microcontroller after a time delay de-
fined by the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
Table 10. AWU Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
AWUCSR AWUF AWUM AWUEN
002Eh 0 0 0 0 0
Reset Value 0 0 0
AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
002Fh
Reset Value 1 1 1 1 1 1 1 1

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10 I/O PORTS

10.1 INTRODUCTION Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently
The I/O ports offer different functional modes: programmable using the sensitivity bits in the
– transfer of data through digital inputs and outputs EICR register.
and for specific pins: Each external interrupt vector is linked to a dedi-
– external interrupt generation cated group of I/O port pins (see pinout description
– alternate signal input/output for the on-chip pe- and interrupt section). If several input pins are se-
ripherals. lected simultaneously as interrupt sources, these
An I/O port contains up to 8 pins. Each pin can be are first detected according to the sensitivity bits in
programmed independently as digital input (with or the EICR register and then logically ORed.
without interrupt generation) or digital output. The external interrupts are hardware interrupts,
which means that the request latch (not accessible
10.2 FUNCTIONAL DESCRIPTION directly by the application) is automatically cleared
when the corresponding interrupt vector is
Each port has two main registers: fetched. To clear an unwanted pending interrupt
– Data Register (DR) by software, the sensitivity bits in the EICR register
– Data Direction Register (DDR) must be modified.
and one optional register: 10.2.2 Output Modes
– Option Register (OR) The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
Each I/O pin may be programmed using the corre- ing the DR register applies this digital value to the
sponding register bits in the DDR and OR regis- I/O pin through the latch. Then reading the DR reg-
ters: Bit X corresponding to pin X of the port. The ister returns the previously stored value.
same correspondence is used for the DR register.
Two different output modes can be selected by
The following description takes into account the software through the OR register: Output push-pull
OR register, (for specific ports which do not pro- and open-drain.
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is DR register value and output pin status:
shown in Figure 1 DR Push-pull Open-drain
10.2.1 Input Modes 0 VSS Vss
The input configuration is selected by clearing the 1 VDD Floating
corresponding DDR register bit.
10.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin. When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
Different input modes can be selected by software ed. This alternate function takes priority over the
through the OR register. standard I/O programming.
Notes: When the signal is coming from an on-chip periph-
1. Writing the DR register modifies the latch value
but does not affect the pin status. eral, the I/O pin is automatically configured in out-
2. When switching from input to output mode, the put mode (push-pull or open drain according to the
DR register has to be written first to drive the cor- peripheral).
rect level on the pin as soon as the port is config- When the signal is going to an on-chip peripheral,
ured as an output. the I/O pin must be configured in input mode. In
3. Do not use read/modify/write instructions (BSET this case, the pin state is also digitally readable by
or BRES) to modify the DR register as this might addressing the DR register.
corrupt the DR content for I/Os configured as input.
Note: Input pull-up configuration can cause unex-
External interrupt function pected value at the input of the alternate peripheral
When an I/O is configured as Input with Interrupt, input. When an on-chip peripheral use a pin as in-
an event on this I/O can generate an external inter- put and output, this pin has to be configured in in-
rupt request to the CPU. put floating mode.

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I/O PORTS (Cont’d)

Figure 35. I/O Port General Block Diagram

ALTERNATE
REGISTER 1
OUTPUT VDD P-BUFFER
ACCESS
(see table below)
0
ALTERNATE PULL-UP
ENABLE (see table below)

DR VDD

DDR

PULL-UP
PAD
CONDITION
OR
DATA BUS

If implemented

OR SEL

N-BUFFER
DIODES
(see table below)
DDR SEL
ANALOG
INPUT
CMOS
SCHMITT
DR SEL
1 TRIGGER

0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)

Table 11. I/O Port Mode Options

Diodes
Configuration Mode Pull-Up P-Buffer
to VDD to VSS
Floating with/without Interrupt Off
Input Off
Pull-up with/without Interrupt On
On
Push-pull On On
Off
Output Open Drain (logic level) Off
True Open Drain NI NI NI (see note)

Legend: NI - not implemented Note: The diode to VDD is not implemented in the
Off - implemented not activated true open drain pads. A local protection between
On - implemented and activated the pad and VSS is implemented to protect the de-
vice against positive stress.

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I/O PORTS (Cont’d)

Table 12. I/O Port Configurations
Hardware Configuration

NOT IMPLEMENTED IN DR REGISTER ACCESS

VDD
TRUE OPEN DRAIN
I/O PORTS
RPU PULL-UP
CONDITION DR W
REGISTER DATA BUS
PAD R
INPUT 1)

ALTERNATE INPUT

EXTERNAL INTERRUPT
SOURCE (eix)

INTERRUPT
CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
OPEN-DRAIN OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

NOT IMPLEMENTED IN DR REGISTER ACCESS

TRUE OPEN DRAIN VDD
PUSH-PULL OUTPUT 2)

I/O PORTS

RPU
DR R/W
REGISTER DATA BUS
PAD

ALTERNATE ALTERNATE
ENABLE OUTPUT

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac- Figure 36. Interrupt I/O Port State Transitions
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts. 01 00 10 11
Analog alternate function INPUT INPUT OUTPUT OUTPUT
When the pin is used as an ADC input, the I/O floating/pull-up floating open-drain push-pull
interrupt (reset state)
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers) XX = DDR, OR
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
10.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in Mode Description
progress. Furthermore it is recommended not to No effect on I/O ports. External interrupts
have clocking pins located close to a selected an- WAIT
cause the device to exit from WAIT mode.
alog pin.
No effect on I/O ports. External interrupts
WARNING: The analog input voltage level must HALT
cause the device to exit from HALT mode.
be within the limits stated in the absolute maxi-
mum ratings.
10.5 INTERRUPTS
10.3 I/O PORT IMPLEMENTATION The external interrupt event generates an interrupt
if the corresponding configuration is selected with
The hardware implementation on each I/O port de- DDR and OR registers and the interrupt mask in
pends on the settings in the DDR and OR registers the CC register is not active (RIM instruction).
and specific feature of the I/O port such as ADC In-
put or true open drain. Enable Exit Exit
Event
Switching these I/O ports from one state to anoth- Interrupt Event Control from from
Flag
er should be done in a sequence that prevents un- Bit Wait Halt
wanted side effects. Recommended safe transi- External interrupt on
tions are illustrated in Figure 2 on page 4. Other DDRx
selected external - Yes
transitions are potentially risky and should be ORx
event
avoided, since they are likely to present unwanted
side-effects such as spurious interrupt generation.

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I/O PORTS (Cont’d)

10.5.1 I/O port implementation
The I/O port register configurations are summa- PA3, PE1, PB3, PF2 (without pull-up)
rised as follows.
MODE DDR OR
Standard ports floating input 0 0
PA5:4, PC7:0, PD5:0, floating interrupt input 0 1
PE0, PF7:6, 4 open drain output 1 0
push-pull output 1 1
MODE DDR OR
floating input 0 0
pull-up input 0 1 True open drain ports
open drain output 1 0 PA7:6 , PD7:6
push-pull output 1 1
MODE DDR
Interrupt ports floating input 0
PB4, PB2:0, PF1:0 (with pull-up) open drain (high sink ports) 1

MODE DDR OR
floating input 0 0
pull-up interrupt input 0 1
open drain output 1 0
push-pull output 1 1

Table 13. Port configuration

Input Output
Port Pin name
OR = 0 OR = 1 OR = 0 OR = 1
PA7:6 floating true open-drain
Port A PA5:4 floating pull-up open drain push-pull
PA3 floating floating interrupt open drain push-pull
PB3 floating floating interrupt open drain push-pull
Port B
PB4, PB2:0 floating pull-up interrupt open drain push-pull
Port C PC7:0 floating pull-up open drain push-pull
PD7:6 floating true open-drain
Port D
PD5:0 floating pull-up open drain push-pull
PE1 floating floating interrupt open drain push-pull
Port E
PE0 floating pull-up open drain push-pull
PF7:6, 4 floating pull-up open drain push-pull
Port F PF2 floating floating interrupt open drain push-pull
PF1:0 floating pull-up interrupt open drain push-pull
CAUTION: In small packages, an internal pull-up is applied permanently to the non-bonded I/O pins. So they have to be
kept in input floating configuration to avoid unwanted consumption.

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I/O PORTS (Cont’d)

Table 14. I/O port register map and reset values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Reset Value
0 0 0 0 0 0 0 0
of all I/O port registers
0000h PADR
0001h PADDR MSB LSB
0002h PAOR
0003h PBDR
0004h PBDDR MSB LSB
0005h PBOR
0006h PCDR
0007h PCDDR MSB LSB
0008h PCOR
0009h PDDR
000Ah PDDDR MSB LSB
000Bh PDOR
000Ch PEDR
000Dh PEDDR MSB LSB
000Eh PEOR
000Fh PFDR
0010h PFDDR MSB LSB
0011h PFOR

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11 ON-CHIP PERIPHERALS

11.1 WINDOW WATCHDOG (WWDG)

11.1.1 Introduction counter is reloaded outside the window (see
Figure 4)
The Window Watchdog is used to detect the oc-
■ Hardware/Software Watchdog activation
currence of a software fault, usually generated by
external interference or by unforeseen logical con- (selectable by option byte)
ditions, which causes the application program to ■ Optional reset on HALT instruction
abandon its normal sequence. The Watchdog cir- (configurable by option byte)
cuit generates an MCU reset on expiry of a pro- 11.1.3 Functional Description
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6 The counter value stored in the WDGCR register
bit becomes cleared. An MCU reset is also gener- (bits T[6:0]), is decremented every 16384 fOSC2
ated if the 7-bit downcounter value (in the control cycles (approx.), and the length of the timeout pe-
register) is refreshed before the downcounter has riod can be programmed by the user in 64 incre-
reached the window register value. This implies ments.
that the counter must be refreshed in a limited win- If the watchdog is activated (the WDGA bit is set)
dow. and when the 7-bit downcounter (T[6:0] bits) rolls
11.1.2 Main Features over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
■ Programmable free-running downcounter ically 30µs. If the software reloads the counter
■ Conditional reset while the counter is greater than the value stored
– Reset (if watchdog activated) when the down- in the window register, then a reset is generated.
counter value becomes less than 40h
– Reset (if watchdog activated) if the down-
Figure 37. Watchdog Block Diagram
RESET WATCHDOG WINDOW REGISTER (WDGWR)

- W6 W5 W4 W3 W2 W1 W0

comparator
= 1 when
T6:0 > W6:0 CMP

Write WDGCR

WATCHDOG CONTROL REGISTER (WDGCR)

WDGA T6 T5 T4 T3 T2 T1 T0

MCC/RTC 6-BIT DOWNCOUNTER (CNT)

fOSC2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
MSB LSB TB[1:0] bits
(MCCSR
11 6 5 0
Register)

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WINDOW WATCHDOG (Cont’d)

The application program must write in the between a minimum and a maximum value due
WDGCR register at regular intervals during normal to the unknown status of the prescaler when writ-
operation to prevent an MCU reset. This operation ing to the WDGCR register (see Figure 3).
must occur only when the counter value is lower
than the window register value. The value to be The window register (WDGWR) contains the
stored in the WDGCR register must be between high limit of the window: To prevent a reset, the
FFh and C0h (see Figure 2): downcounter must be reloaded when its value is
– Enabling the watchdog: lower than the window register value and greater
When Software Watchdog is selected (by option than 3Fh. Figure 4 describes the window watch-
byte), the watchdog is disabled after a reset. It is dog process.
enabled by setting the WDGA bit in the WDGCR Note: The T6 bit can be used to generate a soft-
register, then it cannot be disabled again except ware reset (the WDGA bit is set and the T6 bit is
by a reset. cleared).
– Watchdog Reset on Halt option
When Hardware Watchdog is selected (by option If the watchdog is activated and the watchdog re-
byte), the watchdog is always active and the set on halt option is selected, then the HALT in-
WDGA bit is not used. struction will generate a Reset.
– Controlling the downcounter: 11.1.4 Using Halt Mode with the WDG
This downcounter is free-running: It counts down
even if the watchdog is disabled. When the If Halt mode with Watchdog is enabled by option
watchdog is enabled, the T6 bit must be set to byte (no watchdog reset on HALT instruction), it is
prevent generating an immediate reset. recommended before executing the HALT instruc-
The T[5:0] bits contain the number of increments tion to refresh the WDG counter, to avoid an unex-
which represents the time delay before the pected WDG reset immediately after waking up
watchdog produces a reset (see Figure 2. Ap- the microcontroller.
proximate Timeout Duration). The timing varies

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WINDOW WATCHDOG (Cont’d)

11.1.5 How to Program the Watchdog Timeout more precision is needed, use the formulae in Fig-
Figure 2 shows the linear relationship between the ure 3.
6-bit value to be loaded in the Watchdog Counter Caution: When writing to the WDGCR register, al-
(CNT) and the resulting timeout duration in milli- ways write 1 in the T6 bit to avoid generating an
seconds. This can be used for a quick calculation immediate reset.
without taking the timing variations into account. If

Figure 38. Approximate Timeout Duration

3F

38

30

28
CNT Value (hex.)

20

18

10

08

00
1.5 18 34 50 65 82 98 114 128
Watchdog timeout (ms) @ 8 MHz fOSC2

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WINDOW WATCHDOG (Cont’d)

Figure 39. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2 = 8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit TB0 Bit Selected MCCSR
MSB LSB
(MCCSR Reg.) (MCCSR Reg.) Timebase
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54

To calculate the minimum Watchdog Timeout (tmin):

IF CNT < MSB

------------- THEN t min = t min0 + 16384 × CNT × tosc2
4

ELSE t min = t min0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB

To calculate the maximum Watchdog Timeout (tmax):

IF CNT ≤ MSB
------------- THEN t max = t max0 + 16384 × CNT × t osc2
4

ELSE t max = t max0 + 16384 × ⎛⎝ CNT – 4CNT

----------------- ⎞ + ( 192 + LSB ) × 64 × -----------------
4CNT
× t osc2
MSB ⎠ MSB

Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog Max. Watchdog
Value of T[5:0] Bits in
Timeout (ms) Timeout (ms)
WDGCR Register (Hex.)
tmin tmax
00 1.496 2.048
3F 128 128.552

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WINDOW WATCHDOG (Cont’d)

Figure 40. Window Watchdog Timing Diagram
T[5:0] CNT downcounter

WDGWR

3Fh

time
Refresh not allowed Refresh Window (step = 16384/fOSC2)

T6 bit

Reset

11.1.6 Low Power Modes

Mode Description
SLOW No effect on Watchdog: The downcounter continues to decrement at normal speed.
WAIT No effect on Watchdog: The downcounter continues to decrement.
OIE bit in WDGHALT bit
MCCSR in Option
register Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
HALT rupt or a reset.
0 0 If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 0.1.8 below.
0 1 A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
ACTIVE
1 x oscillator interrupt or external interrupt, the Watchdog restarts counting im-
HALT mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.

11.1.7 Hardware Watchdog Option 11.1.8 Using Halt Mode with the WDG
If Hardware Watchdog is selected by option byte, (WDGHALT option)
the watchdog is always active and the WDGA bit in The following recommendation applies if Halt
the WDGCR is not used. Refer to the Option Byte mode is used when the watchdog is enabled.
description. – Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.

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WINDOW WATCHDOG (Cont’d)

11.1.9 Interrupts WINDOW REGISTER (WDGWR)
None. Read/Write
Reset Value: 0111 1111 (7Fh)
11.1.10 Register Description 7 0
CONTROL REGISTER (WDGCR)
- W6 W5 W4 W3 W2 W1 W0
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
7 0
Bits 6:0 = W[6:0] 7-bit window value
WDGA T6 T5 T4 T3 T2 T1 T0 These bits contain the window value to be com-
pared to the downcounter.

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cy-
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).

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WINDOW WATCHDOG(Cont’d)
Table 15. Watchdog Timer Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

WDGCR WDGA T6 T5 T4 T3 T2 T1 T0
2A
Reset Value 0 1 1 1 1 1 1 1
WDGWR - W6 W5 W4 W3 W2 W1 W0
30
Reset Value 0 1 1 1 1 1 1 1

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11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ- external devices. It is controlled by the MCO bit in
ent functions: the MCCSR register.
■ a programmable CPU clock prescaler CAUTION: When selected, the clock out pin sus-
■ a clock-out signal to supply external devices
pends the clock during ACTIVE-HALT mode.
■ a real time clock timer with interrupt capability
11.2.3 Real Time Clock Timer (RTC)
Each function can be used independently and si- The counter of the real time clock timer allows an
multaneously. interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
11.2.1 Programmable CPU Clock Prescaler ing directly on fOSC2 are available. The whole
The programmable CPU clock prescaler supplies functionality is controlled by four bits of the MCC-
the clock for the ST7 CPU and its internal periph- SR register: TB[1:0], OIE and OIF.
erals. It manages SLOW power saving mode (See When the RTC interrupt is enabled (OIE bit set),
Section 9.2 "SLOW MODE" on page 44 for more the ST7 enters ACTIVE-HALT mode when the
details). HALT instruction is executed. See Section 9.5
The prescaler selects the fCPU main clock frequen- "ACTIVE-HALT MODE" on page 47 for more de-
cy and is controlled by three bits in the MCCSR tails.
register: CP[1:0] and SMS. 11.2.4 Beeper
11.2.2 Clock-out Capability The beep function is controlled by the MCCBCR
The clock-out capability is an alternate function of register. It can output three selectable frequencies
an I/O port pin that outputs a fOSC2 clock to drive on the BEEP pin (I/O port alternate function).

Figure 41. Main Clock Controller (MCC/RTC) Block Diagram

BC1 BC0

MCCBCR
BEEP
BEEP SIGNAL
SELECTION

MCO

12-BIT MCC RTC TO

DIV 64
COUNTER WATCHDOG
TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR MCC/RTC INTERRUPT

fOSC2
DIV 2, 4, 8, 16 1
fCPU CPU CLOCK
TO CPU AND
0 PERIPHERALS

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ST72340, ST72344, ST72345

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

11.2.5 Low Power Modes
Mode Description
Bits 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is
WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These
from WAIT mode. two bits are set and cleared by software
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen. fCPU in SLOW mode CP1 CP0
HALT MCC/RTC interrupt cause the device to exit fOSC2 / 2 0 0
from ACTIVE-HALT mode.
fOSC2 / 4 0 1
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the fOSC2 / 8 1 0
HALT
MCU is woken up by an interrupt with “exit fOSC2 / 16 1 1
from HALT” capability.

11.2.6 Interrupts Bit 4 = SMS Slow mode select

The MCC/RTC interrupt event generates an inter- This bit is set and cleared by software.
rupt if the OIE bit of the MCCSR register is set and 0: Normal mode. fCPU = fOSC2
the interrupt mask in the CC register is not active 1: Slow mode. fCPU is given by CP1, CP0
(RIM instruction). See Section 9.2 "SLOW MODE" on page 44 and
Section 11.1 "WINDOW WATCHDOG (WWDG)"
Enable Exit Exit on page 58 for more details.
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Bits 3:2 = TB[1:0] Time base control
Time base overflow
OIF OIE Yes No 1) These bits select the programmable divider time
event
base. They are set and cleared by software.
Note: Time Base
Counter
The MCC/RTC interrupt wakes up the MCU from TB1 TB0
Prescaler f
ACTIVE-HALT mode, not from HALT mode. OSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1
11.2.7 Register Description 80000 20ms 10ms 1 0
MCC CONTROL/STATUS REGISTER (MCCSR) 200000 50ms 25ms 1 1
Read/Write
A modification of the time base is taken into ac-
Reset Value: 0000 0000 (00h) count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
7 0 use this time base as a real time clock.

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
Bit 7 = MCO Main clock out selection 0: Oscillator interrupt disabled
This bit enables the MCO alternate function on the 1: Oscillator interrupt enabled
PF0 I/O port. It is set and cleared by software. This interrupt can be used to exit from ACTIVE-
0: MCO alternate function disabled (I/O pin free for HALT mode.
general-purpose I/O) When this bit is set, calling the ST7 software HALT
1: MCO alternate function enabled (fCPU on I/O instruction enters the ACTIVE-HALT power saving
port) mode.
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag MCC BEEP CONTROL REGISTER (MCCBCR)
This bit is set by hardware and cleared by software Read/Write
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected Reset Value: 0000 0000 (00h)
elapsed time (TB1:0).
0: Timeout not reached 7 0
1: Timeout reached
0 0 0 0 0 0 BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit. Bits 7:2 = Reserved, must be kept cleared.

Bits 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with fOSC2=8MHz

0 0 Off
0 1 ~2-KHz
Output
1 0 ~1-KHz Beep signal
~50% duty cycle
1 1 ~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the
consumption.
Table 16. Main Clock Controller Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SICSR AVDIE AVDF LVDRF LOCKED WDGRF
002Bh
Reset Value 0 0 0 x 0 0 0 x
MCCSR MCO CP1 CP0 SMS TB1 TB0 OIE OIF
002Ch
Reset Value 0 0 0 0 0 0 0 0
MCCBCR BC1 BC0
002Dh
Reset Value 0 0 0 0 0 0 0 0

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11.3 16-BIT TIMER

11.3.1 Introduction When reading an input signal on a non-bonded
The timer consists of a 16-bit free-running counter pin, the value will always be ‘1’.
driven by a programmable prescaler. 11.3.3 Functional Description
It may be used for a variety of purposes, including 11.3.3.1 Counter
pulse length measurement of up to two input sig- The main block of the Programmable Timer is a
nals (input capture) or generation of up to two out- 16-bit free running upcounter and its associated
put waveforms (output compare and PWM). 16-bit registers. The 16-bit registers are made up
Pulse lengths and waveform periods can be mod- of two 8-bit registers called high & low.
ulated from a few microseconds to several milli- Counter Register (CR):
seconds using the timer prescaler and the CPU
clock prescaler. – Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some devices of the ST7 family have two on-chip
16-bit timers. They are completely independent, – Counter Low Register (CLR) is the least sig-
and do not share any resources. They are syn- nificant byte (LS Byte).
chronized after a Device reset as long as the timer Alternate Counter Register (ACR)
clock frequencies are not modified. – Alternate Counter High Register (ACHR) is the
This description covers one or two 16-bit timers. In most significant byte (MS Byte).
the devices with two timers, register names are – Alternate Counter Low Register (ACLR) is the
prefixed with TA (Timer A) or TB (Timer B). least significant byte (LS Byte).
11.3.2 Main Features These two read-only 16-bit registers contain the
■ Programmable prescaler: fCPU divided by 2, 4 or 8. same value but with the difference that reading the
■ Overflow status flag and maskable interrupt
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
■ External clock input (must be at least 4 times
(see note at the end of paragraph titled 16-bit read
slower than the CPU clock speed) with the choice sequence).
of active edge
Writing in the CLR register or ACLR register resets
■ Output compare functions with
the free running counter to the FFFCh value.
– 2 dedicated 16-bit registers Both counters have a reset value of FFFCh (this is
– 2 dedicated programmable signals the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
– 2 dedicated status flags FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ Input capture functions with
The timer clock depends on the clock control bits
– 2 dedicated 16-bit registers of the CR2 register, as illustrated in Table 17 Clock
– 2 dedicated active edge selection signals Control Bits. The value in the counter register re-
peats every 131 072, 262 144 or 524 288 CPU
– 2 dedicated status flags clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt The timer frequency can be fCPU/2, fCPU/4, fCPU/8
■ Pulse width modulation mode (PWM) or an external frequency.
■ One pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 42.

*Note: Some timer pins may not available (not
bonded) in some devices. Refer to the device pin
out description.

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16-BIT TIMER (Cont’d)

Figure 42. Timer Block Diagram

INTERNAL BUS

fCPU
16-BIT TIMER PERIPHERAL INTERFACE

8 high 8 low
8-bit 8 8 8 8 8 8 8 8
buffer
high

high

high

high
low

low

low

low
EXEDG
16

1/2 OUTPUT OUTPUT INPUT INPUT

COUNTER
COMPARE COMPARE CAPTURE CAPTURE
1/4
REGISTER REGISTER REGISTER REGISTER REGISTER
1/8
1 2 1 2
EXTCLK ALTERNATE
pin COUNTER
16 16
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16

OVERFLOW
OUTPUT COMPARE EDGE DETECT ICAP1
DETECT
CIRCUIT CIRCUIT1 pin
CIRCUIT

6 EDGE DETECT ICAP2

CIRCUIT2 pin

LATCH1 OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
(Control/Status Register) LATCH2 OCMP2
CSR pin

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 1) CR1 (Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See Device Interrupt Vector Table)

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16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter Clearing the overflow interrupt request is done in
Register or the Alternate Counter Register). two steps:
Beginning of the sequence 1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Read LS Byte Notes: The TOF bit is not cleared by accesses to
At t0 MS Byte is buffered ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
Other it allows simultaneous use of the overflow function
instructions and reading the free running counter at random
times (for example, to measure elapsed time) with-
Read Returns the buffered out the risk of clearing the TOF bit erroneously.
At t0 +∆t LS Byte LS Byte value at t0 The timer is not affected by WAIT mode.
Sequence completed In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
The user must read the MS Byte first, then the LS previous count (Device awakened by an interrupt)
Byte value is buffered automatically. or from the reset count (Device awakened by a
Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times. 11.3.3.2 External Clock
After a complete reading sequence, if only the The external clock (where available) is selected if
CLR register or ACLR register are read, they re- CC0=1 and CC1=1 in CR2 register.
turn the LS Byte of the count value at the time of
The status of the EXEDG bit in the CR2 register
the read.
determines the type of level transition on the exter-
Whatever the timer mode used (input capture, out- nal clock pin EXTCLK that will trigger the free run-
put compare, one pulse mode or PWM mode) an ning counter.
overflow occurs when the counter rolls over from
The counter is synchronised with the falling edge
FFFFh to 0000h then:
of the internal CPU clock.
– The TOF bit of the SR register is set.
A minimum of four falling edges of the CPU clock
– A timer interrupt is generated if: must occur between two consecutive active edges
– TOIE bit of the CR1 register is set and of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
– I bit of the CC register is cleared. clock frequency.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

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 ST72340, ST72344, ST72345

16-BIT TIMER (Cont’d)

Figure 43. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 44. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000 0001

TIMER OVERFLOW FLAG (TOF)

Figure 45. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-
ning.

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16-BIT TIMER (Cont’d)

11.3.3.3 Input Capture When an input capture occurs:
In this section, the index, i, may be 1 or 2 because – ICFi bit is set.
there are 2 input capture functions in the 16-bit – The ICiR register contains the value of the free
timer. running counter on the active transition on the
The two input capture 16-bit registers (IC1R and ICAPi pin (see Figure 47).
IC2R) are used to latch the value of the free run- – A timer interrupt is generated if the ICIE bit is set
ning counter after a transition detected by the and the I bit is cleared in the CC register. Other-
ICAPi pin (see figure 5). wise, the interrupt remains pending until both
MS Byte LS Byte conditions become true.
ICiR ICiHR ICiLR Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register. 1. Reading the SR register while the ICFi bit is set.
The active transition is software programmable 2. An access (read or write) to the ICiLR register.
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]). Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
Procedure: never be set until the ICiLR register is also
To use the input capture function select the follow- read.
ing in the CR2 register: 2. The ICiR register contains the free running
– Select the timer clock (CC[1:0]) (see Table 17 counter value which corresponds to the most
Clock Control Bits). recent input capture.
– Select the edge of the active transition on the 3. The 2 input capture functions can be used
ICAP2 pin with the IEDG2 bit (the ICAP2 pin together even if the timer also uses the 2 output
must be configured as floating input). compare functions.
And select the following in the CR1 register: 4. In One pulse Mode and PWM mode only the
– Set the ICIE bit to generate an interrupt after an input capture 2 can be used.
input capture coming from either the ICAP1 pin 5. The alternate inputs (ICAP1 & ICAP2) are
or the ICAP2 pin always directly connected to the timer. So any
– Select the edge of the active transition on the transitions on these pins activate the input cap-
ICAP1 pin with the IEDG1 bit (the ICAP1pin must ture function.
be configured as floating input). Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).

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16-BIT TIMER (Cont’d)

Figure 46. Input Capture Block Diagram

ICAP1 (Control Register 1) CR1

pin
EDGE DETECT EDGE DETECT ICIE IEDG1
ICAP2 CIRCUIT2 CIRCUIT1
pin (Status Register) SR

IC2R Register IC1R Register ICF1 ICF2 0 0 0

(Control Register 2) CR2

16-BIT
16-BIT FREE RUNNING CC1 CC0 IEDG2
COUNTER

Figure 47. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER FF01 FF02 FF03

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER FF03

Note: The active edge is the rising edge.

Note: The time between an event on the ICAPi pin

and the appearance of the corresponding flag is
from 2 to 3 CPU clock cycles. This depends on the
moment when the ICAP event happens relative to
the timer clock.

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16-BIT TIMER (Cont’d)

11.3.3.4 Output Compare – The OCMPi pin takes OLVLi bit value (OCMPi
In this section, the index, i, may be 1 or 2 because pin latch is forced low during reset).
there are 2 output compare functions in the 16-bit – A timer interrupt is generated if the OCIE bit is
timer. set in the CR2 register and the I bit is cleared in
This function can be used to control an output the CC register (CC).
waveform or indicate when a period of time has
elapsed. The OCiR register value required for a specific tim-
When a match is found between the Output Com- ing application can be calculated using the follow-
pare register and the free running counter, the out- ing formula:
put compare function:
– Assigns pins with a programmable value if the ∆t * fCPU
OCIE bit is set ∆ OCiR =
PRESC
– Sets a flag in the status register
Where:
– Generates an interrupt if enabled
∆t = Output compare period (in seconds)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) fCPU = CPU clock frequency (in hertz)
contain the value to be compared to the counter PRESC = Timer prescaler factor (2, 4 or 8 de-
register each timer clock cycle. pending on CC[1:0] bits, see Table 17
MS Byte LS Byte
Clock Control Bits)
OCiR OCiHR OCiLR
If the timer clock is an external clock, the formula
These registers are readable and writable and are is:
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h. ∆ OCiR = ∆t * fEXT
Timing resolution is one count of the free running Where:
counter: (fCPU/CC[1:0]).
∆t = Output compare period (in seconds)
fEXT = External timer clock frequency (in hertz)
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register: Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i 1. Reading the SR register while the OCFi bit is
signal. set.
– Select the timer clock (CC[1:0]) (see Table 17 2. An access (read or write) to the OCiLR register.
Clock Control Bits). The following procedure is recommended to pre-
And select the following in the CR1 register: vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs. – Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed. – Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register: – Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.

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16-BIT TIMER (Cont’d)

Notes:
1. After a processor write cycle to the OCiHR reg- Forced Compare Output capability
ister, the output compare function is inhibited When the FOLVi bit is set by software, the OLVLi
until the OCiLR register is also written. bit is copied to the OCMPi pin. The OLVi bit has to
2. If the OCiE bit is not set, the OCMPi pin is a be toggled in order to toggle the OCMPi pin when
general I/O port and the OLVLi bit will not it is enabled (OCiE bit=1). The OCFi bit is then not
appear when a match is found but an interrupt set by hardware, and thus no interrupt request is
could be generated if the OCIE bit is set. generated.
3. When the timer clock is fCPU/2, OCFi and FOLVLi bits have no effect in both one pulse mode
OCMPi are set while the counter value equals and PWM mode.
the OCiR register value (see Figure 49 on page
78). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 50 on page 78).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 48. Output Compare Block Diagram

16 BIT FREE RUNNING OC1E OC2E CC1 CC0

COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE Latch
OCIE FOLV2 FOLV1 OLVL2 OLVL1 OCMP1
CIRCUIT 1
Pin
16-bit 16-bit
Latch
2 OCMP2
OC1R Register Pin
OCF1 OCF2 0 0 0
OC2R Register
(Status Register) SR

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ST72340, ST72344, ST72345

16-BIT TIMER (Cont’d)

Figure 49. Output Compare Timing Diagram, fTIMER =fCPU/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

OUTPUT COMPARE REGISTER i (OCRi) 2ED3

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

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16-BIT TIMER (Cont’d)

11.3.3.5 One Pulse Mode Clearing the Input Capture interrupt request (i.e.
One Pulse mode enables the generation of a clearing the ICFi bit) is done in two steps:
pulse when an external event occurs. This mode is 1. Reading the SR register while the ICFi bit is set.
selected via the OPM bit in the CR2 register. 2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1 The OC1R register value required for a specific
function and the Output Compare1 function. timing application can be calculated using the fol-
Procedure: lowing formula:
To use one pulse mode: t * fCPU -5
OCiR Value =
1. Load the OC1R register with the value corre- PRESC
sponding to the length of the pulse (see the for- Where:
mula in the opposite column). t = Pulse period (in seconds)
2. Select the following in the CR1 register: fCPU = CPU clock frequency (in hertz)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse. PRESC = Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 17
– Using the OLVL2 bit, select the level to be ap- Clock Control Bits)
plied to the OCMP1 pin during the pulse. If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin OCiR = t * fEXT -5
must be configured as floating input).
Where:
3. Select the following in the CR2 register:
t = Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function. fEXT = External timer clock frequency (in hertz)
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 17 When the value of the counter is equal to the value
Clock Control Bits). of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 51).

One pulse mode cycle

Notes:
ICR1 = Counter 1. The OCF1 bit cannot be set by hardware in one
When pulse mode but the OCF2 bit can generate an
event occurs OCMP1 = OLVL2
on ICAP1 Output Compare interrupt.
Counter is reset
to FFFCh 2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
ICF1 bit is set PWM mode is the only active one.
When 3. If OLVL1=OLVL2 a continuous signal will be
Counter seen on the OCMP1 pin.
= OC1R OCMP1 = OLVL1
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
When a valid event occurs on the ICAP1 pin, the counter is reset each time a valid edge occurs
counter value is loaded in the ICR1 register. The on the ICAP1 pin and ICF1 can also generates
counter is then initialized to FFFCh, the OLVL2 bit interrupt if ICIE is set.
is output on the OCMP1 pin and the ICF1 bit is set. 5. When one pulse mode is used OC1R is dedi-
Because the ICF1 bit is set when an active edge cated to this mode. Nevertheless OC2R and
occurs, an interrupt can be generated if the ICIE OCF2 can be used to indicate a period of time
bit is set. has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.

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16-BIT TIMER (Cont’d)

Figure 51. One Pulse Mode Timing Example

IC1R 01F8 2ED3

01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD

COUNTER
2ED3

ICAP1

OCMP1 OLVL2 OLVL1 OLVL2

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 52. Pulse Width Modulation Mode Timing Example

COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC

OLVL2 OLVL1 OLVL2

OCMP1
compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

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 ST72340, ST72344, ST72345

16-BIT TIMER (Cont’d)

11.3.3.6 Pulse Width Modulation Mode Clock Control Bits).
Pulse Width Modulation (PWM) mode enables the Pulse Width Modulation cycle
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers. When
Counter OCMP1 = OLVL1
Pulse Width Modulation mode uses the complete = OC1R
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated. OCMP1 = OLVL2
When
In PWM mode, double buffering is implemented on Counter Counter is reset
the output compare registers. Any new values writ- = OC2R to FFFCh
ten in the OC1R and OC2R registers are loaded in
their respective shadow registers (double buffer) ICF1 bit is set
only at the end of the PWM period (OC2) to avoid
spikes on the PWM output pin (OCMP1). The If OLVL1=1 and OLVL2=0 the length of the posi-
shadow registers contain the reference values for tive pulse is the difference between the OC2R and
comparison in PWM “double buffering” mode. OC1R registers.
Note: There is a locking mechanism for transfer- If OLVL1=OLVL2 a continuous signal will be seen
ring the OCiR value to the buffer. After a write to on the OCMP1 pin.
the OCiHR register, transfer of the new compare The OCiR register value required for a specific tim-
value to the buffer is inhibited until OCiLR is also ing application can be calculated using the follow-
written. ing formula:
Unlike in Output Compare mode, the compare t * fCPU -5
function is always enabled in PWM mode. OCiR Value =
PRESC
Where:
Procedure t = Signal or pulse period (in seconds)
To use pulse width modulation mode: fCPU = CPU clock frequency (in hertz)
1. Load the OC2R register with the value corre- PRESC = Timer prescaler factor (2, 4 or 8 depend-
sponding to the period of the signal using the ing on CC[1:0] bits, see Table 17 Clock
formula in the opposite column. Control Bits)
2. Load the OC1R register with the value corre- If the timer clock is an external clock the formula is:
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo- OCiR = t * fEXT -5
site column.
Where:
3. Select the following in the CR1 register:
t = Signal or pulse period (in seconds)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful fEXT = External timer clock frequency (in hertz)
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be ap- The Output Compare 2 event causes the counter
plied to the OCMP1 pin after a successful to be initialized to FFFCh (See Figure 52)
comparison with OC2R register. Notes:
4. Select the following in the CR2 register: 1. The OCF1 and OCF2 bits cannot be set by
– Set OC1E bit: the OCMP1 pin is then dedicat- hardware in PWM mode therefore the Output
ed to the output compare 1 function. Compare interrupt is inhibited.
– Set the PWM bit. 2. The ICF1 bit is set by hardware when the coun-
– Select the timer clock (CC[1:0]) (see Table 17 ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.

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16-BIT TIMER (Cont’d)

3. In PWM mode the ICAP1 pin can not be used ICF1 can also generates interrupt if ICIE is set.
to perform input capture because it is discon- 4. When the Pulse Width Modulation (PWM) and
nected to the timer. The ICAP2 pin can be used One Pulse Mode (OPM) bits are both set, the
to perform input capture (ICF2 can be set and PWM mode is the only active one.
IC2R can be loaded) but the user must take
care that the counter is reset each period and
11.3.4 Low Power Modes
Mode Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the Device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter
HALT reset value when the Device is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.

11.3.5 Interrupts
Enable Exit Exit
Event
Interrupt Event Control from from
Flag
Bit Wait Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 Yes No
ICIE
Input Capture 2 event ICF2 Yes No
Output Compare 1 event (not available in PWM mode) OCF1 Yes No
OCIE
Output Compare 2 event (not available in PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

11.3.6 Summary of Timer modes

AVAILABLE RESOURCES
MODES
Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2
Input Capture (1 and/or 2) Yes Yes Yes Yes
Output Compare (1 and/or 2) Yes Yes Yes Yes
One Pulse Mode No Not Recommended1) No Partially 2)
3)
PWM Mode No Not Recommended No No
1)
See note 4 in Section 11.3.3.5 "One Pulse Mode" on page 79
2) See note 5 in Section 11.3.3.5 "One Pulse Mode" on page 79
3)
See note 4 in Section 11.3.3.6 "Pulse Width Modulation Mode" on page 81

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16-BIT TIMER (Cont’d)

11.3.7 Register Description Bit 4 = FOLV2 Forced Output Compare 2.
Each Timer is associated with three control and This bit is set and cleared by software.
status registers, and with six pairs of data registers 0: No effect on the OCMP2 pin.
(16-bit values) relating to the two input captures, 1: Forces the OLVL2 bit to be copied to the
the two output compares, the counter and the al- OCMP2 pin, if the OC2E bit is set and even if
ternate counter. there is no successful comparison.

CONTROL REGISTER 1 (CR1) Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.
Read/Write 0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h) 1: Forces OLVL1 to be copied to the OCMP1 pin, if
7 0 the OC1E bit is set and even if there is no suc-
cessful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = ICIE Input Capture Interrupt Enable. This bit is copied to the OCMP2 pin whenever a
0: Interrupt is inhibited. successful comparison occurs with the OC2R reg-
1: A timer interrupt is generated whenever the ister and OCxE is set in the CR2 register. This val-
ICF1 or ICF2 bit of the SR register is set. ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited. Bit 1 = IEDG1 Input Edge 1.
1: A timer interrupt is generated whenever the This bit determines which type of level transition
OCF1 or OCF2 bit of the SR register is set. on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF Bit 0 = OLVL1 Output Level 1.
bit of the SR register is set. The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

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16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2) Bit 4 = PWM Pulse Width Modulation.
Read/Write 0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
Reset Value: 0000 0000 (00h) programmable cyclic signal; the length of the
7 0
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com- Table 17. Clock Control Bits
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E Timer Clock CC1 CC0
bit, the Output Compare 1 function of the timer re- fCPU / 4 0 0
mains active. fCPU / 2 0 1
0: OCMP1 pin alternate function disabled (I/O pin fCPU / 8 1 0
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled. External Clock (where
1 1
available)

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the Note: If the external clock pin is not available, pro-
timer on the OCMP2 pin (OLV2 in Output Com- gramming the external clock configuration stops
pare mode). Whatever the value of the OC2E bit, the counter.
the Output Compare 2 function of the timer re-
mains active. Bit 1 = IEDG2 Input Edge 2.
0: OCMP2 pin alternate function disabled (I/O pin This bit determines which type of level transition
free for general-purpose I/O). on the ICAP2 pin will trigger the capture.
1: OCMP2 pin alternate function enabled. 0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active. Bit 0 = EXEDG External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be This bit determines which type of level transition
used to trigger one pulse on the OCMP1 pin; the on the external clock pin EXTCLK will trigger the
active transition is given by the IEDG1 bit. The counter register.
length of the generated pulse depends on the 0: A falling edge triggers the counter register.
contents of the OC1R register. 1: A rising edge triggers the counter register.

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16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR) Note: Reading or writing the ACLR register does
Read Only not clear TOF.
Reset Value: 0000 0000 (00h)
The three least significant bits are not used. Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
7 0 1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value). Bit 3 = OCF2 Output Compare Flag 2.
1: An input capture has occurred on the ICAP1 pin 0: No match (reset value).
or the counter has reached the OC2R value in 1: The content of the free running counter has
PWM mode. To clear this bit, first read the SR matched the content of the OC2R register. To
register, then read or write the low byte of the clear this bit, first read the SR register, then read
IC1R (IC1LR) register. or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value). Bit 2 = TIMD Timer disable.
1: The content of the free running counter has This bit is set and cleared by software. When set, it
matched the content of the OC1R register. To freezes the timer prescaler and counter and disa-
clear this bit, first read the SR register, then read bled the output functions (OCMP1 and OCMP2
or write the low byte of the OC1R (OC1LR) reg- pins) to reduce power consumption. Access to the
ister. timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
Bit 5 = TOF Timer Overflow Flag. 0: Timer enabled
0: No timer overflow (reset value). 1: Timer prescaler, counter and outputs disabled
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg- Bits 1:0 = Reserved, must be kept cleared.
ister, then read or write the low byte of the CR
(CLR) register.

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16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR) OUTPUT COMPARE 1 HIGH REGISTER
Read Only (OC1HR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 1000 0000 (80h)
high part of the counter value (transferred by the This is an 8-bit register that contains the high part
input capture 1 event). of the value to be compared to the CHR register.
7 0 7 0

MSB LSB MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR) OUTPUT COMPARE 1 LOW REGISTER

Read Only (OC1LR)
Reset Value: Undefined Read/Write
This is an 8-bit read only register that contains the Reset Value: 0000 0000 (00h)
low part of the counter value (transferred by the in- This is an 8-bit register that contains the low part of
put capture 1 event). the value to be compared to the CLR register.
7 0 7 0

MSB LSB MSB LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER ALTERNATE COUNTER HIGH REGISTER
(OC2HR) (ACHR)
Read/Write Read Only
Reset Value: 1000 0000 (80h) Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part This is an 8-bit register that contains the high part
of the value to be compared to the CHR register. of the counter value.
7 0 7 0

MSB LSB MSB LSB

OUTPUT COMPARE 2 LOW REGISTER ALTERNATE COUNTER LOW REGISTER

(OC2LR) (ACLR)
Read/Write Read Only
Reset Value: 0000 0000 (00h) Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of This is an 8-bit register that contains the low part of
the value to be compared to the CLR register. the counter value. A write to this register resets the
counter. An access to this register after an access
7 0 to CSR register does not clear the TOF bit in the
CSR register.
MSB LSB
7 0

COUNTER HIGH REGISTER (CHR) MSB LSB

Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value. Read Only
Reset Value: Undefined
7 0 This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
MSB LSB Input Capture 2 event).
7 0

COUNTER LOW REGISTER (CLR) MSB LSB

Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of INPUT CAPTURE 2 LOW REGISTER (IC2LR)
the counter value. A write to this register resets the
counter. An access to this register after accessing Read Only
the CSR register clears the TOF bit. Reset Value: Undefined
This is an 8-bit read only register that contains the
7 0 low part of the counter value (transferred by the In-
put Capture 2 event).
MSB LSB
7 0

MSB LSB

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16-BIT TIMER (Cont’d)

Table 18. 16-Bit Timer Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
Timer A: 32 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Timer B: 42 Reset Value 0 0 0 0 0 0 0 0
Timer A: 31 CR2 OC1E OC2E1 OPM PWM CC1 CC0 IEDG2 EXEDG
Timer B: 41 Reset Value 0 0 0 0 0 0 0 0
Timer A: 33 CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD - -
Timer B: 43 Reset Value x x x x x 0 x x
Timer A: 34 IC1HR MSB LSB
Timer B: 44 Reset Value x x x x x x x x
Timer A: 35 IC1LR MSB LSB
Timer B: 45 Reset Value x x x x x x x x
Timer A: 36 OC1HR MSB LSB
Timer B: 46 Reset Value 1 0 0 0 0 0 0 0
Timer A: 37 OC1LR MSB LSB
Timer B: 47 Reset Value 0 0 0 0 0 0 0 0
Timer A: 3E OC2HR MSB LSB
Timer B: 4E Reset Value 1 0 0 0 0 0 0 0
Timer A: 3F OC2LR MSB LSB
Timer B: 4F Reset Value 0 0 0 0 0 0 0 0
Timer A: 38 CHR MSB LSB
Timer B: 48 Reset Value 1 1 1 1 1 1 1 1
Timer A: 39 CLR MSB LSB
Timer B: 49 Reset Value 1 1 1 1 1 1 0 0
Timer A: 3A ACHR MSB LSB
Timer B: 4A Reset Value 1 1 1 1 1 1 1 1
Timer A: 3B ACLR MSB LSB
Timer B: 4B Reset Value 1 1 1 1 1 1 0 0
Timer A: 3C IC2HR MSB LSB
Timer B: 4C Reset Value x x x x x x x x
Timer A: 3D IC2LR MSB LSB
Timer B: 4D Reset Value x x x x x x x x

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ON-CHIP PERIPHERALS (cont’d)

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction 11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full- Figure 1 on page 3 shows the serial peripheral in-
duplex, synchronous, serial communication with terface (SPI) block diagram. There are three regis-
external devices. An SPI system may consist of a ters:
master and one or more slaves or a system in – SPI Control Register (SPICR)
which devices may be either masters or slaves.
– SPI Control/Status Register (SPICSR)
11.4.2 Main Features
– SPI Data Register (SPIDR)
■ Full duplex synchronous transfers (on three
lines) The SPI is connected to external devices through
■ Simplex synchronous transfers (on two lines)
four pins:
■ Master or slave operation
– MISO: Master In / Slave Out data
■ 6 master mode frequencies (fCPU/4 max.) – MOSI: Master Out / Slave In data
■ fCPU/2 max. slave mode frequency (see note) – SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware

■ Programmable clock polarity and phase

– SS: Slave select:
This input signal acts as a ‘chip select’ to let
■ End of transfer interrupt flag
the SPI master communicate with slaves indi-
■ Write collision, Master Mode Fault and Overrun vidually and to avoid contention on the data
flags lines. Slave SS inputs can be driven by stand-
Note: In slave mode, continuous transmission is ard I/O ports on the master Device.
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.

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SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)

Figure 53. Serial Peripheral Interface Block Diagram

Data/Address Bus

SPIDR Read
Interrupt
request
Read Buffer

MOSI
7 SPICSR 0
MISO 8-Bit Shift Register
SPIF WCOL OVR MODF 0 SOD SSM SSI

Write
SOD
bit 1
SS
SPI 0
SCK STATE
CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER
CONTROL

SERIAL CLOCK
GENERATOR
SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.1 Functional Description the MISO pin. This implies full duplex communica-
A basic example of interconnections between a tion with both data out and data in synchronized
single master and a single slave is illustrated in with the same clock signal (which is provided by
Figure 2. the master device via the SCK pin).
The MOSI pins are connected together and the To use a single data line, the MISO and MOSI pins
MISO pins are connected together. In this way must be connected at each node (in this case only
data is transferred serially between master and simplex communication is possible).
slave (most significant bit first). Four possible data/clock timing relationships may
The communication is always initiated by the mas- be chosen (see Figure 5 on page 7) but master
ter. When the master device transmits data to a and slave must be programmed with the same tim-
slave device via MOSI pin, the slave device re- ing mode.
sponds by sending data to the master device via
Figure 54. Single Master/ Single Slave Application

MASTER SLAVE
MSBit LSBit MSBit LSBit
MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
SS SS
+5V
Not used if SS is managed
by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.2 Slave Select Management In Slave Mode:
As an alternative to using the SS pin to control the There are two cases depending on the data/clock
Slave Select signal, the application can choose to timing relationship (see Figure 3):
manage the Slave Select signal by software. This If CPHA = 1 (data latched on second clock edge):
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 4). – SS internal must be held low during the entire
transmission. This implies that in single slave
In software management, the external SS pin is applications the SS pin either can be tied to
free for other application uses and the internal SS VSS, or made free for standard I/O by manag-
signal level is driven by writing to the SSI bit in the ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
SPICSR register.
If CPHA = 0 (data latched on first clock edge):
In Master mode:
– SS internal must be held low during byte
– SS internal must be held high continuously transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 0.1.5.3).
Figure 55. Generic SS Timing Diagram

MOSI/MISO Byte 1 Byte 2 Byte 3

Master SS

Slave SS
(if CPHA = 0)

Slave SS
(if CPHA = 1)

Figure 56. Hardware/Software Slave Select Management

SSM bit

SSI bit 1
SS internal
SS external pin 0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.3 Master Mode Operation Note: While the SPIF bit is set, all writes to the
In master mode, the serial clock is output on the SPIDR register are inhibited until the SPICSR reg-
SCK pin. The clock frequency, polarity and phase ister is read.
are configured by software (refer to the description 11.4.3.5 Slave Mode Operation
of the SPICSR register). In slave mode, the serial clock is received on the
Note: The idle state of SCK must correspond to SCK pin from the master device.
the polarity selected in the SPICSR register (by To operate the SPI in slave mode:
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0). 1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
To operate the SPI in master mode, perform the configuring the CPOL and CPHA bits (see
following steps in order: Figure 5).
Note: The slave must have the same CPOL
1. Write to the SPICR register: and CPHA settings as the master.
– Select the clock frequency by configuring the – Manage the SS pin as described in Section
SPR[2:0] bits. 0.1.3.2 and Figure 3. If CPHA = 1 SS must be
– Select the clock polarity and clock phase by held low continuously. If CPHA = 0 SS must
configuring the CPOL and CPHA bits. Figure be held low during byte transmission and
5 shows the four possible configurations. pulled up between each byte to let the slave
Note: The slave must have the same CPOL write in the shift register.
and CPHA settings as the master. 2. Write to the SPICR register to clear the MSTR
2. Write to the SPICSR register: bit and set the SPE bit to enable the SPI I/O
– Either set the SSM bit and set the SSI bit or functions.
clear the SSM bit and tie the SS pin high for 11.4.3.6 Slave Mode Transmit Sequence
the complete byte transmit sequence.
3. Write to the SPICR register: When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
– Set the MSTR and SPE bits then shifted out serially to the MISO pin most sig-
Note: MSTR and SPE bits remain set only if nificant bit first.
SS is high).
Important note: if the SPICSR register is not writ- The transmit sequence begins when the slave de-
ten first, the SPICR register setting (MSTR bit) vice receives the clock signal and the most signifi-
may be not taken into account. cant bit of the data on its MOSI pin.
The transmit sequence begins when software When data transfer is complete:
writes a byte in the SPIDR register. – The SPIF bit is set by hardware.
11.4.3.4 Master Mode Transmit Sequence – An interrupt request is generated if SPIE bit is
When software writes to the SPIDR register, the set and interrupt mask in the CCR register is
data byte is loaded into the 8-bit shift register and cleared.
then shifted out serially to the MOSI pin most sig- Clearing the SPIF bit is performed by the following
nificant bit first. software sequence:
When data transfer is complete: 1. An access to the SPICSR register while the
– The SPIF bit is set by hardware. SPIF bit is set
– An interrupt request is generated if the SPIE 2. A write or a read to the SPIDR register
bit is set and the interrupt mask in the CCR Notes: While the SPIF bit is set, all writes to the
register is cleared. SPIDR register are inhibited until the SPICSR reg-
Clearing the SPIF bit is performed by the following ister is read.
software sequence: The SPIF bit can be cleared during a second
1. An access to the SPICSR register while the transmission; however, it must be cleared before
SPIF bit is set the second SPIF bit in order to prevent an Overrun
condition (see Section 0.1.5.2).
2. A read to the SPIDR register

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.4 Clock Phase and Clock Polarity Figure 5 shows an SPI transfer with the four com-
Four possible timing relationships may be chosen binations of the CPHA and CPOL bits. The dia-
by software, using the CPOL and CPHA bits (See gram may be interpreted as a master or slave tim-
Figure 5). ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
Note: The idle state of SCK must correspond to master and the slave device.
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if Note: If CPOL is changed at the communication
CPOL = 0). byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 57. Data Clock Timing Diagram
CPHA = 1

SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

CPHA = 0
SCK
(CPOL = 1)

SCK
(CPOL = 0)

MISO MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from master)

MOSI MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

(from slave)

SS
(to slave)
CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5 Error Flags 11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF) An overrun condition occurs when the master de-
Master mode fault occurs when the master de- vice has sent a data byte and the slave device has
vice’s SS pin is pulled low. not cleared the SPIF bit issued from the previously
transmitted byte.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set. – The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph- In this case, the receiver buffer contains the byte
eral. sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
– The MSTR bit is reset, thus forcing the device bytes are lost.
into slave mode.
The OVR bit is cleared by reading the SPICSR
Clearing the MODF bit is done through a software register.
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set. A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
2. A write to the SPICR register. taking place with an external device. When this
Notes: To avoid any conflicts in an application happens, the transfer continues uninterrupted and
with multiple slaves, the SS pin must be pulled the software write will be unsuccessful.
high during the MODF bit clearing sequence. The Write collisions can occur both in master and slave
SPE and MSTR bits may be restored to their orig- mode. See also Section 0.1.3.2 Slave Select Man-
inal state during or after this clearing sequence. agement.
Hardware does not allow the user to set the SPE Note: A "read collision" will never occur since the
and MSTR bits while the MODF bit is set except in received data byte is placed in a buffer in which
the MODF bit clearing sequence. access is always synchronous with the CPU oper-
In a slave device, the MODF bit can not be set, but ation.
in a multimaster configuration the device can be in The WCOL bit in the SPICSR register is set if a
slave mode with the MODF bit set. write collision occurs.
The MODF bit indicates that there might have No SPI interrupt is generated when the WCOL bit
been a multimaster conflict and allows software to is set (the WCOL bit is a status flag only).
handle this using an interrupt routine and either
perform a reset or return to an application default Clearing the WCOL bit is done through a software
state. sequence (see Figure 6).

Figure 58. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step

RESULT
2nd Step SPIF = 0
Read SPIDR WCOL = 0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR
1st Step
RESULT Note: Writing to the SPIDR regis-
ter instead of reading it does not
2nd Step Read SPIDR WCOL = 0 reset the WCOL bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5.4 Single Master and Multimaster For more security, the slave device may respond
Configurations to the master with the received data byte. Then the
There are two types of SPI systems: master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
– Single Master System nected and the slave has not written to its SPIDR
– Multimaster System register.
Single Master System Other transmission security methods can use
A typical single master system may be configured ports for handshake lines or data bytes with com-
using a device as the master and four devices as mand fields.
slaves (see Figure 7). Multimaster System
The master device selects the individual slave de- A multimaster system may also be configured by
vices by using four pins of a parallel port to control the user. Transfer of master control could be im-
the four SS pins of the slave devices. plemented using a handshake method through the
The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages
master device ports will be forced to be inputs at through the serial peripheral interface system.
that time, thus disabling the slave devices. The multimaster system is principally handled by
Note: To prevent a bus conflict on the MISO line, the MSTR bit in the SPICR register and the MODF
the master allows only one active slave device bit in the SPICSR register.
during a transmission.
Figure 59. Single Master / Multiple Slave Configuration

SS SS SS SS
SCK SCK SCK SCK
Slave Slave Slave Slave
Device Device Device Device

MOSI MISO MOSI MISO MOSI MISO MOSI MISO

MOSI MISO
SCK
Ports

Master
Device

5V SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.6 Low Power Modes the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
Mode Description
state immediately.
No effect on SPI.
WAIT SPI interrupt events cause the device to exit Caution: The SPI can wake up the device from
from WAIT mode. HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
SPI registers are frozen.
low when the device enters HALT mode. So, if
In HALT mode, the SPI is inactive. SPI oper-
Slave selection is configured as external (see Sec-
ation resumes when the device is woken up
tion 0.1.3.2), make sure the master drives a low
by an interrupt with “exit from HALT mode”
level on the SS pin when the slave enters HALT
capability. The data received is subsequently
mode.
HALT read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If 11.4.7 Interrupts
several data are received before the wake-
up event, then an overrun error is generated. Enable Exit Exit
Event
This error can be detected after the fetch of Interrupt Event Control from from
Flag
the interrupt routine that woke up the Device. Bit Wait Halt
SPI End of
SPIF Yes
11.4.6.1 Using the SPI to wake up the device Transfer Event
from Halt mode Master Mode SPIE Yes
MODF
Fault Event No
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter- Overrun Error OVR
rupt. The data received is subsequently read from
the SPIDR register when the software is running Note: The SPI interrupt events are connected to
(interrupt vector fetch). If multiple data transfers the same interrupt vector (see Interrupts chapter).
have been performed before software clears the They generate an interrupt if the corresponding
SPIF bit, then the OVR bit is set by hardware. Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring

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11.4.8 Register Description

SPI CONTROL REGISTER (SPICR) Bit 3 = CPOL Clock Polarity
Read/Write This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
Reset Value: 0000 xxxx (0xh) CPOL bit affects both the master and slave
7 0
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
Bit 7 = SPIE Serial Peripheral Interrupt Enable setting the SPE bit.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 2 = CPHA Clock Phase
1: An SPI interrupt is generated whenever an End
This bit is set and cleared by software.
of Transfer event, Master Mode Fault or Over-
0: The first clock transition is the first data capture
run error occurs (SPIF = 1, MODF = 1 or
edge.
OVR = 1 in the SPICSR register)
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable Note: The slave must have the same CPOL and
This bit is set and cleared by software. It is also CPHA settings as the master.
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the Bits 1:0 = SPR[1:0] Serial Clock Frequency
SPI peripheral is not initially connected to the ex- These bits are set and cleared by software. Used
ternal pins. with the SPR2 bit, they select the baud rate of the
0: I/O pins free for general purpose I/O SPI serial clock SCK output by the SPI in master
1: SPI I/O pin alternate functions enabled mode.
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable Table 19. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to Serial Clock SPR2 SPR1 SPR0
set the baud rate. Refer to Table 1 SPI Master fCPU/4 1
Mode SCK Frequency. 0
0: Divider by 2 enabled fCPU/8 0
0
1: Divider by 2 disabled fCPU/16 1
Note: This bit has no effect in slave mode. fCPU/32 1
0
fCPU/64 1
0
Bit 4 = MSTR Master Mode fCPU/128 1
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only) Bit 2 = SOD SPI Output Disable
Reset Value: 0000 0000 (00h) This bit is set and cleared by software. When set, it
7 0 disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
SPIF WCOL OVR MODF - SOD SSM SSI
0: SPI output enabled (if SPE = 1)
1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag Bit 1 = SSM SS Management
(Read only) This bit is set and cleared by software. When set, it
This bit is set by hardware when a transfer has disables the alternate function of the SPI SS pin
been completed. An interrupt is generated if and uses the SSI bit value instead. See Section
SPIE = 1 in the SPICR register. It is cleared by 0.1.3.2 Slave Select Management.
a software sequence (an access to the SPICSR 0: Hardware management (SS managed by exter-
register followed by a write or a read to the nal pin)
SPIDR register). 1: Software management (internal SS signal con-
0: Data transfer is in progress or the flag has been trolled by SSI bit. External SS pin free for gener-
cleared. al-purpose I/O)
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the Bit 0 = SSI SS Internal Mode
SPIDR register are inhibited until the SPICSR reg- This bit is set and cleared by software. It acts as a
ister is read. ‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only) 1: Slave deselected
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se- SPI DATA I/O REGISTER (SPIDR)
quence. It is cleared by a software sequence (see Read/Write
Figure 6). Reset Value: Undefined
0: No write collision occurred
1: A write collision has been detected 7 0

Bit 5 = OVR SPI Overrun error (Read only) D7 D6 D5 D4 D3 D2 D1 D0

This bit is set by hardware when the byte currently
being received in the shift register is ready to be The SPIDR register is used to transmit and receive
transferred into the SPIDR register while SPIF = 1 data on the serial bus. In a master device, a write
(See Section 0.1.5.2). An interrupt is generated if to this register will initiate transmission/reception
SPIE = 1 in the SPICR register. The OVR bit is of another byte.
cleared by software reading the SPICSR register.
0: No overrun error Notes: During the last clock cycle the SPIF bit is
1: Overrun error detected set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
Bit 4 = MODF Mode Fault flag (Read only) actually being read.
This bit is set by hardware when the SS pin is While the SPIF bit is set, all writes to the SPIDR
pulled low in master mode (see Section 0.1.5.1 register are inhibited until the SPICSR register is
Master Mode Fault (MODF)). An SPI interrupt can read.
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac- Warning: A write to the SPIDR register places
cess to the SPICSR register while MODF = 1 fol- data directly into the shift register for transmission.
lowed by a write to the SPICR register). A read to the SPIDR register returns the value lo-
0: No master mode fault detected cated in the buffer and not the content of the shift
1: A fault in master mode has been detected register (see Figure 1).
Bit 3 = Reserved, must be kept cleared.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 20. SPI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SPIDR MSB LSB
0021h
Reset Value x x x x x x x x
SPICR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0022h
Reset Value 0 0 0 0 x x x x
SPICSR SPIF WCOL OR MODF SOD SSM SSI
0023h
Reset Value 0 0 0 0 0 0 0 0

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11.5 SCI SERIAL COMMUNICATION INTERFACE

11.5.1 Introduction 11.5.3 General Description
The Serial Communications Interface (SCI) offers The interface is externally connected to another
a flexible means of full-duplex data exchange with device by three pins (see Figure 1). Any SCI bidi-
external equipment requiring an industry standard rectional communication requires a minimum of
NRZ asynchronous serial data format. The SCI of- two pins: Receive Data In (RDI) and Transmit Data
fers a very wide range of baud rates using two Out (TDO):
baud rate generator systems. – SCLK: Transmitter clock output. This pin outputs
11.5.2 Main Features the transmitter data clock for synchronous trans-
■ Full duplex, asynchronous communications mission (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on
■ NRZ standard format (Mark/Space)
the last data bit). This can be used to control pe-
■ Dual baud rate generator systems ripherals that have shift registers (e.g. LCD driv-
■ Independently programmable transmit and ers). The clock phase and polarity are software
receive baud rates up to 500K baud programmable.
■ Programmable data word length (8 or 9 bits) – TDO: Transmit Data Output. When the transmit-
■ Receive buffer full, Transmit buffer empty and ter is disabled, the output pin returns to its I/O
End of Transmission flags port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
■ 2 receiver wake-up modes:
pin is at high level.
– Address bit (MSB)
– RDI: Receive Data Input is the serial data input.
– Idle line Oversampling techniques are used for data re-
■ Muting function for multiprocessor configurations covery by discriminating between valid incoming
■ Separate enable bits for Transmitter and
data and noise.
Receiver Through these pins, serial data is transmitted and
■ 4 error detection flags: received as frames comprising:
– Overrun error – An Idle Line prior to transmission or reception
– Noise error – A start bit
– Frame error – A data word (8 or 9 bits) least significant bit first
– Parity error – A Stop bit indicating that the frame is complete.
■ 5 interrupt sources with flags: This interface uses two types of baud rate generator:
– Transmit data register empty – A conventional type for commonly-used baud
rates,
– Transmission complete
– An extended type with a prescaler offering a very
– Receive data register full
wide range of baud rates even with non-standard
– Idle line received oscillator frequencies.
– Overrun error detected
■ Parity control:

– Transmits parity bit

– Checks parity of received data byte
■ Reduced power consumption mode

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

Figure 60. SCI Block Diagram

Write Read (DATA REGISTER) SCIDR

Transmit Data Register (TDR) Receive Data Register (RDR)

TDO

Transmit Shift Register Receive Shift Register

RDI

R8 T8 SCID M WAKE PCE PS PIE SCICR1

WAKE
TRANSMIT UP RECEIVER RECEIVER
CONTROL UNIT CONTROL CLOCK

SCICR2 SCISR
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PE

SCI
INTERRUPT
CONTROL

TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/16 /PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4 Functional Description 11.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface, Word length may be selected as being either 8 or 9
is shown in Figure 1. It contains six dedicated reg- bits by programming the M bit in the SCICR1 reg-
isters: ister (see Figure 2).
– 2 control registers (SCICR1 and SCICR2) The TDO pin is in low state during the start bit.
– A status register (SCISR) The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR) An Idle character is interpreted as an entire frame
– An extended prescaler receiver register of “1”s followed by the start bit of the next frame
(SCIERPR) which contains data.
– An extended prescaler transmitter register A Break character is interpreted on receiving “0”s
(SCIETPR) for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
Refer to the register descriptions in Section 0.1.7 tra “1” bit to acknowledge the start bit.
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 61. Word Length Programming

9-bit Word length (M bit is set)

Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit
CLOCK
**

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

** LBCL bit controls last data clock pulse

8-bit Word length (M bit is reset)
Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
CLOCK ****
**

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

** LBCL bit controls last data clock pulse

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.2 Transmitter When a transmission is taking place, a write in-
The transmitter can send data words of either 8 or struction to the SCIDR register stores the data in
9 bits depending on the M bit status. When the M the TDR register and which is copied in the shift
bit is set, word length is 9 bits and the 9th bit (the register at the end of the current transmission.
MSB) has to be stored in the T8 bit in the SCICR1 When no transmission is taking place, a write in-
register. struction to the SCIDR register places the data di-
When the transmit enable bit (TE) is set, the data rectly in the shift register, the data transmission
in the transmit shift register is output on the TDO starts, and the TDRE bit is immediately set.
pin. When a frame transmission is complete (after the
Character Transmission stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
During an SCI transmission, data shifts out least the I bit is cleared in the CCR register.
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be- Clearing the TC bit is performed by the following
tween the internal bus and the transmit shift regis- software sequence:
ter (see Figure 2). 1. An access to the SCISR register
2. A write to the SCIDR register
Procedure
Note: The TDRE and TC bits are cleared by the
– Select the M bit to define the word length. same software sequence.
– Select the desired baud rate using the SCIBRR Break Characters
and the SCIETPR registers.
Setting the SBK bit loads the shift register with a
– Set the TE bit to send an idle frame as first trans- break character. The break frame length depends
mission. on the M bit (see Figure 2).
– Access the SCISR register and write the data to As long as the SBK bit is set, the SCI send break
send in the SCIDR register (this sequence clears frames to the TDO pin. After clearing this bit by
the TDRE bit). Repeat this sequence for each software the SCI insert a logic 1 bit at the end of
data to be transmitted. the last break frame to guarantee the recognition
Clearing the TDRE bit is always performed by the of the start bit of the next frame.
following software sequence: Idle Characters
1. An access to the SCISR register
2. A write to the SCIDR register Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
The TDRE bit is set by hardware and it indicates:
Clearing and then setting the TE bit during a trans-
– The TDR register is empty. mission sends an idle frame after the current word.
– The data transfer is beginning. Note: Resetting and setting the TE bit causes the
– The next data can be written in the SCIDR regis- data in the TDR register to be lost. Therefore the
ter without overwriting the previous data. best time to toggle the TE bit is when the TDRE bit
This flag generates an interrupt if the TIE bit is set is set, that is, before writing the next byte in the
and the I bit is cleared in the CCR register. SCIDR.

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.3 Receiver – The RDR content is not lost.
The SCI can receive data words of either 8 or 9 – The shift register is overwritten.
bits. When the M bit is set, word length is 9 bits – An interrupt is generated if the RIE bit is set and
and the MSB is stored in the R8 bit in the SCICR1 the I bit is cleared in the CCR register.
register.
The OR bit is reset by an access to the SCISR reg-
Character reception ister followed by a SCIDR register read operation.
During a SCI reception, data shifts in least signifi- Noise Error
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be- Oversampling techniques are used for data recov-
tween the internal bus and the received shift regis- ery by discriminating between valid incoming data
ter (see Figure 1). and noise.
Procedure Normal data bits are considered valid if three con-
secutive samples (8th, 9th, 10th) have the same
– Select the M bit to define the word length. bit value, otherwise the NF flag is set. In the case
– Select the desired baud rate using the SCIBRR of start bit detection, the NF flag is set on the basis
and the SCIERPR registers. of an algorithm combining both valid edge detec-
– Set the RE bit, this enables the receiver which tion and three samples (8th, 9th, 10th). Therefore,
begins searching for a start bit. to prevent the NF flag getting set during start bit re-
ception, there should be a valid edge detection as
When a character is received: well as three valid samples.
– The RDRF bit is set. It indicates that the content When noise is detected in a frame:
of the shift register is transferred to the RDR.
– The NF flag is set at the rising edge of the RDRF
– An interrupt is generated if the RIE bit is set and bit.
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
– The error flags can be set if a frame error, noise SCIDR register.
or an overrun error has been detected during re-
ception. – No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
Clearing the RDRF bit is performed by the following generates an interrupt.
software sequence done by:
The NF flag is reset by a SCISR register read op-
1. An access to the SCISR register eration followed by a SCIDR register read opera-
2. A read to the SCIDR register. tion.
The RDRF bit must be cleared before the end of the During reception, if a false start bit is detected (e.g.
reception of the next character to avoid an overrun 8th, 9th, 10th samples are 011,101,110), the
error. frame is discarded and the receiving sequence is
Break Character not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
When a break character is received, the SCI han- accessible to the user). This NF flag is accessible
dles it as a framing error. along with the RDRF bit when a next valid frame is
Idle Character received.
When an idle frame is detected, there is the same Note: If the application Start Bit is not long enough
procedure as a data received character plus an in- to match the above requirements, then the NF
terrupt if the ILIE bit is set and the I bit is cleared in Flag may get set due to the short Start Bit. In this
the CCR register. case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
Overrun Error
See also Section 0.1.4.10 .
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can- Framing Error
not be transferred from the shift register to the A framing error is detected when:
RDR register until the RDRF bit is cleared.
– The stop bit is not recognized on reception at the
When a overrun error occurs: expected time, following either a de-synchroni-
– The OR bit is set. zation or excessive noise.
– A break is received.

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When the framing error is detected: – No interrupt is generated. However this bit rises
– the FE bit is set by hardware at the same time as the RDRF bit which itself
generates an interrupt.
– Data is transferred from the Shift register to the
SCIDR register. The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER

RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

fCPU

TRANSMITTER RATE
CONTROL
/16 /PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE
CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.4 Conventional Baud Rate Generation other than zero. The baud rates are calculated as
The baud rates for the receiver and transmitter (Rx follows:
and Tx) are set independently and calculated as
follows fCPU fCPU
Tx = Rx =
: 16 ETPR*(PR*TR) 16*ERPR*(PR*RR)
*
fCPU fCPU
Tx = Rx = with:
(16*PR)*TR (16*PR)*RR
ETPR = 1, ..., 255 (see SCIETPR register)
with: ERPR = 1, ..., 255 (see SCIERPR register)
PR = 1, 3, 4 or 13 (see SCP[1:0] bits) 11.5.4.6 Receiver Muting and Wake-up Feature
TR = 1, 2, 4, 8, 16, 32, 64,128 In multiprocessor configurations it is often desira-
(see SCT[2:0] bits) ble that only the intended message recipient
RR = 1, 2, 4, 8, 16, 32, 64,128 should actively receive the full message contents,
thus reducing redundant SCI service overhead for
(see SCR[2:0] bits) all non addressed receivers.
All these bits are in the SCIBRR register. The non-addressed devices may be placed in
Example: If fCPU is 8 MHz (normal mode) and if sleep mode by means of the muting function.
PR = 13 and TR = RR = 1, the transmit and re- Setting the RWU bit by software puts the SCI in
ceive baud rates are 38400 baud. sleep mode:
Note: The baud rate registers MUST NOT be None of the reception status bits can be set.
changed while the transmitter or the receiver is en-
abled. All the receive interrupts are inhibited.
11.5.4.5 Extended Baud Rate Generation A muted receiver can be woken up in one of the
following two ways:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal- – by Idle Line detection if the WAKE bit is reset,
er, whereas the conventional Baud Rate Genera- – by Address Mark detection if the WAKE bit is set.
tor retains industry standard software compatibili- A receiver wakes-up by Idle Line detection when
ty. the Receive line has recognized an Idle Frame.
The extended baud rate generator block diagram Then the RWU bit is reset by hardware but the
is shown in Figure 3. IDLE bit is not set.
The output clock rate sent to the transmitter or to A receiver wakes-up by Address Mark detection
the receiver is the output from the 16 divider divid- when it received a “1” as the most significant bit of
ed by a factor ranging from 1 to 255 set in the SCI- a word, thus indicating that the message is an ad-
ERPR or the SCIETPR register. dress. The reception of this particular word wakes
Note: The extended prescaler is activated by set- up the receiver, resets the RWU bit and sets the
ting the SCIETPR or SCIERPR register to a value RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.7 Parity control Reception mode: If the PCE bit is set then the in-
Parity control (generation of parity bit in transmis- terface checks if the received data byte has an
sion and parity checking in reception) can be ena- even number of “1s” if even parity is selected
bled by setting the PCE bit in the SCICR1 register. (PS = 0) or an odd number of “1s” if odd parity is
Depending on the frame length defined by the M selected (PS = 1). If the parity check fails, the PE
bit, the possible SCI frame formats are as listed in flag is set in the SCISR register and an interrupt is
Table 1. generated if PIE is set in the SCICR1 register.
11.5.4.8 SCI Clock Tolerance
Table 21. Frame Formats
During reception, each bit is sampled 16 times.
M bit PCE bit SCI frame The majority of the 8th, 9th and 10th samples is
0 | SB | 8 bit data | STB | considered as the bit value. For a valid bit detec-
0 tion, all the three samples should have the same
1 | SB | 7-bit data | PB | STB |
value otherwise the noise flag (NF) is set. For ex-
0 | SB | 9-bit data | STB |
1 ample: if the 8th, 9th and 10th samples are 0, 1
1 | SB | 8-bit data PB | STB | and 1 respectively, then the bit value is “1”, but the
Legend: Noise Flag bit is set because the three samples
SB: Start Bit values are not the same.
STB: Stop Bit Consequently, the bit length must be long enough
PB: Parity Bit so that the 8th, 9th and 10th samples have the de-
Note: In case of wake up by an address mark, the sired bit value. This means the clock frequency
MSB bit of the data is taken into account and not should not vary more than 6/16 (37.5%) within one
the parity bit bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
Even parity: The parity bit is calculated to obtain
bit, 1 data byte, 1 stop bit), the clock deviation
an even number of “1s” inside the frame made of
must not exceed 3.75%.
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit. Note: The internal sampling clock of the microcon-
troller samples the pin value on every falling edge.
Example: data = 00110101; 4 bits set => parity bit Therefore, the internal sampling clock and the time
is 0 if even parity is selected (PS bit = 0).
the application expects the sampling to take place
Odd parity: The parity bit is calculated to obtain may be out of sync. For example: If the baud rate
an odd number of “1s” inside the frame made of is 15.625 kbaud (bit length is 64µs), then the 8th,
the 7 or 8 LSB bits (depending on whether M is 9th and 10th samples will be at 28µs, 32µs and
equal to 0 or 1) and the parity bit. 36µs respectively (the first sample starting ideally
Example: data = 00110101; 4 bits set => parity bit at 0µs). But if the falling edge of the internal clock
is 1 if odd parity is selected (PS bit = 1). occurs just before the pin value changes, the sam-
ples would then be out of sync by ~4us. This
Transmission mode: If the PCE bit is set then the means the entire bit length must be at least 40µs
MSB bit of the data written in the data register is (36µs for the 10th sample + 4µs for synchroniza-
not transmitted but is changed by the parity bit. tion with the internal sampling clock).

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.4.9 Clock Deviation Causes 11.5.4.10 Noise Error Causes
The causes which contribute to the total deviation See also description of Noise error in Section
are: 0.1.4.3 .
– DTRA: Deviation due to transmitter error (Local Start bit
oscillator error of the transmitter or the trans- The noise flag (NF) is set during start bit reception
mitter is transmitting at a different baud rate). if one of the following conditions occurs:
– DQUANT: Error due to the baud rate quantiza- 1. A valid falling edge is not detected. A falling
tion of the receiver. edge is considered to be valid if the three con-
– DREC: Deviation of the local oscillator of the secutive samples before the falling edge occurs
receiver: This deviation can occur during the are detected as '1' and, after the falling edge
reception of one complete SCI message as- occurs, during the sampling of the 16 samples,
suming that the deviation has been compen- if one of the samples numbered 3, 5 or 7 is
sated at the beginning of the message. detected as a “1”.
– DTCL: Deviation due to the transmission line 2. During sampling of the 16 samples, if one of the
(generally due to the transceivers) samples numbered 8, 9 or 10 is detected as a
All the deviations of the system should be added “1”.
and compared to the SCI clock tolerance: Therefore, a valid Start Bit must satisfy both the
DTRA + DQUANT + DREC + DTCL < 3.75% above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and 10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.

Figure 63. Bit Sampling in Reception Mode

RDI LINE

sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.5 Low Power Modes Enable Exit Exit
Event
Interrupt Event Control from from
Mode Description Flag
Bit Wait Halt
No effect on SCI.
Transmit Data Register
WAIT SCI interrupts cause the device to exit from TDRE TIE
Empty
Wait mode.
Transmission Com-
SCI registers are frozen. TC TCIE
plete
HALT In Halt mode, the SCI stops transmitting/re- Received Data Ready
ceiving until Halt mode is exited. RDRF Yes No
to be Read
RIE
Overrun Error Detect-
11.5.6 Interrupts ed
OR
The SCI interrupt events are connected to the Idle Line Detected IDLE ILIE
same interrupt vector. Parity Error PE PIE
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter- rupt mask in the CC register is reset (RIM instruc-
tion).

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

11.5.7 Register Description Note: The IDLE bit is not set again until the RDRF
STATUS REGISTER (SCISR) bit has been set itself (that is, a new idle line oc-
Read Only curs).
Reset Value: 1100 0000 (C0h)
7 0 Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE TC RDRF IDLE OR NF FE PE
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
Bit 7 = TDRE Transmit data register empty. register. It is cleared by a software sequence (an
This bit is set by hardware when the content of the access to the SCISR register followed by a read to
TDR register has been transferred into the shift the SCIDR register).
register. An interrupt is generated if the TIE bit = 1 0: No Overrun error
in the SCICR2 register. It is cleared by a software 1: Overrun error is detected
sequence (an access to the SCISR register fol- Note: When this bit is set, the RDR register con-
lowed by a write to the SCIDR register). tent is not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register Bit 2 = NF Noise flag.
until the TDRE bit is cleared. This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
Bit 6 = TC Transmission complete. by a read to the SCIDR register).
This bit is set by hardware when transmission of a 0: No noise is detected
frame containing Data is complete. An interrupt is 1: Noise is detected
generated if TCIE = 1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it ap-
cleared by a software sequence (an access to the pears at the same time as the RDRF bit which it-
SCISR register followed by a write to the SCIDR self generates an interrupt.
register).
0: Transmission is not complete
1: Transmission is complete Bit 1 = FE Framing error.
Note: TC is not set after the transmission of a Pre- This bit is set by hardware when a desynchroniza-
amble or a Break. tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag. the SCIDR register).
This bit is set by hardware when the content of the 0: No Framing error is detected
RDR register has been transferred to the SCIDR 1: Framing error or break character is detected
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se- Note: This bit does not generate an interrupt as it
quence (an access to the SCISR register followed appears at the same time as the RDRF bit which it-
by a read to the SCIDR register). self generates an interrupt. If the word currently
0: Data is not received being transferred causes both frame error and
1: Received data is ready to be read overrun error, it is transferred and only the OR bit
is set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is de- Bit 0 = PE Parity error.
tected. An interrupt is generated if the ILIE = 1 in This bit is set by hardware when a parity error oc-
the SCICR2 register. It is cleared by a software se- curs in receiver mode. It is cleared by a software
quence (an access to the SCISR register followed sequence (a read to the status register followed by
by a read to the SCIDR register). an access to the SCIDR data register). An inter-
0: No Idle Line is detected rupt is generated if PIE = 1 in the SCICR1 register.
1: Idle Line is detected 0: No parity error
1: Parity error

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

CONTROL REGISTER 1 (SCICR1)
Read/Write Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is
set or cleared by software.
7 0 0: Idle Line
1: Address Mark
R8 T8 SCID M WAKE PCE PS PIE

Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8. This bit selects the hardware parity control (gener-
This bit is used to store the 9th bit of the received ation and detection). When the parity control is en-
word when M = 1. abled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
Bit 6 = T8 Transmit data bit 8. cleared by software. Once it is set, PCE is active
This bit is used to store the 9th bit of the transmit- after the current byte (in reception and in transmis-
ted word when M = 1. sion).
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans- Bit 1 = PS Parity selection.
fer in order to reduce power consumption.This bit This bit selects the odd or even parity when the
is set and cleared by software. parity generation/detection is enabled (PCE bit
0: SCI enabled set). It is set and cleared by software. The parity is
1: SCI prescaler and outputs disabled selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software. Bit 0 = PIE Parity interrupt enable.
0: 1 Start bit, 8 Data bits, 1 Stop bit This bit enables the interrupt capability of the hard-
1: 1 Start bit, 9 Data bits, 1 Stop bit ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
1: Parity error interrupt enabled
transfer (both transmission and reception).

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

CONTROL REGISTER 2 (SCICR2)
Read/Write Bit 2 = RE Receiver enable.
Reset Value: 0000 0000 (00h) This bit enables the receiver. It is set and cleared
by software.
7 0 0: Receiver is disabled
1: Receiver is enabled and begins searching for a
TIE TCIE RIE ILIE TE RE RWU SBK start bit

Bit 7 = TIE Transmitter interrupt enable. Bit 1 = RWU Receiver wake-up.

This bit is set and cleared by software. This bit determines if the SCI is in mute mode or
0: Interrupt is inhibited not. It is set and cleared by software and can be
1: An SCI interrupt is generated whenever cleared by hardware when a wake-up sequence is
TDRE = 1 in the SCISR register recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software. Notes:
0: Interrupt is inhibited – Before selecting Mute mode (by setting the RWU
1: An SCI interrupt is generated whenever TC = 1 bit) the SCI must first receive a data byte, other-
in the SCISR register wise it cannot function in Mute mode with wake-
up by Idle line detection.
Bit 5 = RIE Receiver interrupt enable. – In Address Mark Detection Wake-Up configura-
This bit is set and cleared by software. tion (WAKE bit = 1) the RWU bit cannot be mod-
0: Interrupt is inhibited ified by software while the RDRF bit is set.
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
Bit 4 = ILIE Idle line interrupt enable. set and cleared by software.
This bit is set and cleared by software. 0: No break character is transmitted
0: Interrupt is inhibited 1: Break characters are transmitted
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register. Note: If the SBK bit is set to “1” and then to “0”, the
transmitter sends a BREAK word at the end of the
current word.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

DATA REGISTER (SCIDR) Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
Reset Value: Undefined bus clock to yield the transmit rate clock in conven-
Contains the Received or Transmitted data char- tional Baud Rate Generator mode.
acter, depending on whether it is read from or writ-
TR dividing factor SCT2 SCT1 SCT0
ten to.
1 0
7 0 0
2 1
0
4 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1
8 1
The Data register performs a double function (read 16 0
0
and write) since it is composed of two registers, 32 1
one for transmission (TDR) and one for reception 1
64 0
(RDR). 1
128 1
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1). Note: This TR factor is used only when the ETPR
The RDR register provides the parallel interface fine tuning factor is equal to 00h; otherwise, TR is
between the input shift register and the internal replaced by the (TR*ETPR) dividing factor.
bus (see Figure 1).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (SCIBRR) These 3 bits, in conjunction with the SCP1 and
Read/Write SCP0 bits define the total division applied to the
bus clock to yield the receive rate clock in conven-
Reset Value: 0000 0000 (00h) tional Baud Rate Generator mode.
7 0 RR dividing factor SCR2 SCR1 SCR0
1 0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 0
2 1
0
4 0
Bits 7:6 = SCP[1:0] First SCI Prescaler 1
These 2 prescaling bits allow several standard 8 1
clock division ranges: 16 0
0
PR Prescaling factor SCP1 SCP0 32 1
1
1 0 64 0
0 1
3 1 128 1
4 0
1 Note: This RR factor is used only when the ERPR
13 1
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.

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SCI SERIAL COMMUNICATION INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIERPR) REGISTER (SCIETPR)
Read/Write Read/Write
Reset Value: 0000 0000 (00h) Reset Value:0000 0000 (00h)
7 0 7 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register. Prescaler Register.
The extended Baud Rate Generator is activated The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis- when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the Figure 3) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255). SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af- The extended baud rate generator is not active af-
ter a reset. ter a reset.

Table 22. Baud Rate Selection

Conditions
Baud
Symbol Parameter Accuracy vs. Standard Unit
fCPU Prescaler Rate
Standard
Conventional Mode
TR (or RR) = 128, PR = 13 300 ~300.48
TR (or RR) = 32, PR = 13 1200 ~1201.92
TR (or RR) = 16, PR =13 2400 ~2403.84
~0.16% TR (or RR) = 8, PR = 13 4800 ~4807.69
fTx Communication TR (or RR) = 4, PR = 13 9600 ~9615.38
8 MHz TR (or RR) = 16, PR = 3 10400 ~10416.67 Hz
fRx frequency
TR (or RR) = 2, PR = 13 19200 ~19230.77
TR (or RR) = 1, PR = 13 38400 ~38461.54
Extended Mode
~0.79% ETPR (or ERPR) = 35, 14400 ~14285.71
TR (or RR) = 1, PR = 1

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SERIAL COMMUNICATION INTERFACE (Cont’d)

Table 23. SCI Register Map and Reset Values
Address Register
7 6 5 4 3 2 1 0
(Hex.) Label
SCISR TDRE TC RDRF IDLE OR NF FE PE
0050h
Reset Value 1 1 0 0 0 0 0 0
SCIDR MSB LSB
0051h
Reset Value x x x x x x x x
SCIBRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0052h
Reset Value 0 0 0 0 0 0 0 0
SCICR1 R8 T8 SCID M WAKE PCE PS PIE
0053h
Reset Value x 0 0 0 0 0 0 0
SCICR2 TIE TCIE RIE ILIE TE RE RWU SBK
0054h
Reset Value 0 0 0 0 0 0 0 0
SCIERPR MSB LSB
0056h
Reset Value 0 0 0 0 0 0 0 0
SCIPETPR MSB LSB
0057h
Reset Value 0 0 0 0 0 0 0 0

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11.6 I2C BUS INTERFACE (I2C)

11.6.1 Introduction handshake. The interrupts are enabled or disabled
The I2C Bus Interface serves as an interface be- by software. The interface is connected to the I2C
tween the microcontroller and the serial I2C bus. It bus by a data pin (SDAI) and by a clock pin (SCLI).
provides both multimaster and slave functions, It can be connected both with a standard I2C bus
and controls all I2C bus-specific sequencing, pro- and a Fast I2C bus. This selection is made by soft-
tocol, arbitration and timing. It supports fast I2C ware.
mode (400kHz). Mode Selection
11.6.2 Main Features The interface can operate in the four following
2
■ Parallel-bus/I C protocol converter modes:
■ Multi-master capability – Slave transmitter/receiver
■ 7-bit/10-bit Addressing – Master transmitter/receiver
■ Transmitter/Receiver flag By default, it operates in slave mode.
■ End-of-byte transmission flag The interface automatically switches from slave to
■ Transfer problem detection master after it generates a START condition and
from master to slave in case of arbitration loss or a
I2C Master Features:
STOP generation, allowing then Multi-Master ca-
■ Clock generation pability.
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
■ End of byte transmission flag generates the clock signal. A serial data transfer
■ Transmitter/Receiver Flag always begins with a start condition and ends with
■ Start bit detection flag
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
I2C Slave Features: nising its own address (7 or 10-bit), and the Gen-
■ Stop bit detection eral Call address. The General Call address de-
2
■ I C bus busy flag tection may be enabled or disabled by software.
■ Detection of misplaced start or stop condition Data and addresses are transferred as 8-bit bytes,
2
■ Programmable I C Address detection
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
■ Transfer problem detection
in 10-bit mode). The address is always transmitted
■ End-of-byte transmission flag in Master mode.
■ Transmitter/Receiver flag A 9th clock pulse follows the 8 clock cycles of a
11.6.3 General Description byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
In addition to receiving and transmitting data, this
ure 64.
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
Figure 64. I2C BUS Protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION
VR02119B

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I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by The SCL frequency (Fscl) is controlled by a pro-
software. grammable clock divider which depends on the
The I2C interface address and/or general call ad- I2C bus mode.
dress can be selected by software. When the I2C cell is enabled, the SDA and SCL
The speed of the I2C interface may be selected ports must be configured as floating inputs. In this
between Standard (up to 100KHz) and Fast I2C case, the value of the external pull-up resistor
(up to 400KHz). used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 65. I2C Interface Block Diagram
DATA REGISTER (DR)

SDA or SDAI DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

OWN ADDRESS REGISTER 2 (OAR2)

SCL or SCLI CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1) CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

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I2C BUS INTERFACE (Cont’d)

11.6.4 Functional Description – EVF and BTF bits are set with an interrupt if the
Refer to the CR, SR1 and SR2 registers in Section ITE bit is set.
11.6.7. for the bit definitions. Then the interface waits for a read of the SR1 reg-
By default the I2C interface operates in Slave ister followed by a read of the DR register, holding
mode (M/SL bit is cleared) except when it initiates the SCL line low (see Figure 66 Transfer se-
a transmit or receive sequence. quencing EV2).
First the interface frequency must be configured
using the FRi bits in the OAR2 register. Slave Transmitter
Following the address reception and after SR1
11.6.4.1 Slave Mode register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
As soon as a start condition is detected, the register.
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call The slave waits for a read of the SR1 register fol-
address (if selected by software). lowed by a write in the DR register, holding the
Note: In 10-bit addressing mode, the comparision SCL line low (see Figure 66 Transfer sequencing
includes the header sequence (11110xx0) and the EV3).
two most significant bits of the address. When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface – The EVF and BTF bits are set by hardware with
generates an acknowledge pulse if the ACK bit is an interrupt if the ITE bit is set.
set.
Address not matched: the interface ignores it Closing slave communication
and waits for another Start condition.
After the last data byte is transferred a Stop Con-
Address matched: the interface generates in se- dition is generated by the master. The interface
quence: detects this condition and sets:
– Acknowledge pulse if the ACK bit is set. – EVF and STOPF bits with an interrupt if the ITE
– EVF and ADSL bits are set with an interrupt if the bit is set.
ITE bit is set. Then the interface waits for a read of the SR2 reg-
Then the interface waits for a read of the SR1 reg- ister (see Figure 66 Transfer sequencing EV4).
ister, holding the SCL line low (see Figure 66
Transfer sequencing EV1). Error Cases
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction – BERR: Detection of a Stop or a Start condition
Bit) if the slave must enter Receiver or Transmitter during a byte transfer. In this case, the EVF and
mode. the BERR bits are set with an interrupt if the ITE
bit is set.
In 10-bit mode, after receiving the address se- If it is a Stop then the interface discards the data,
quence the slave is always in receive mode. It will released the lines and waits for another Start
enter transmit mode on receiving a repeated Start condition.
condition followed by the header sequence with If it is a Start then the interface discards the data
matching address bits and the least significant bit and waits for the next slave address on the bus.
set (11110xx1) .
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
Slave Receiver rupt if the ITE bit is set.
Following the address reception and after SR1 The AF bit is cleared by reading the I2CSR2 reg-
register has been read, the slave receives bytes ister. However, if read before the completion of
from the SDA line into the DR register via the inter- the transmission, the AF flag will be set again,
nal shift register. After each byte the interface gen- thus possibly generating a new interrupt. Soft-
erates in sequence: ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
– Acknowledge pulse if the ACK bit is set

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to correctly handle a second interrupt during the Then the master waits for a read of the SR1 regis-
9th pulse of a transmitted byte. ter followed by a write in the DR register, holding
Note: In both cases, SCL line is not held low; how- the SCL line low (see Figure 66 Transfer se-
ever, the SDA line can remain low if the last bits quencing EV9).
transmitted are all 0. It is then necessary to re- Then the second address byte is sent by the inter-
lease both lines by software. The SCL line is not face.
held low while AF=1 but by other flags (SB or BTF)
that are set at the same time. After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
How to release the SDA / SCL lines – The EVF bit is set by hardware with interrupt
Set and subsequently clear the STOP bit while generation if the ITE bit is set.
BTF is set. The SDA/SCL lines are released after Then the master waits for a read of the SR1 regis-
the transfer of the current byte. ter followed by a write in the CR register (for exam-
SMBus Compatibility ple set PE bit), holding the SCL line low (see Fig-
ST7 I2C is compatible with SMBus V1.1 protocol. It ure 66 Transfer sequencing EV6).
supports all SMBus adressing modes, SMBus bus
protocols and CRC-8 packet error checking. Refer Next the master must enter Receiver or Transmit-
to AN1713: SMBus Slave Driver For ST7 I2C Pe- ter mode.
ripheral.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
11.6.4.2 Master Mode a repeated Start condition and resend the header
To switch from default Slave mode to Master sequence with the least significant bit set
mode a Start condition generation is needed. (11110xx1).

Start condition Master Receiver

Setting the START bit while the BUSY bit is Following the address transmission and after SR1
cleared causes the interface to switch to Master and CR registers have been accessed, the master
mode (M/SL bit set) and generates a Start condi- receives bytes from the SDA line into the DR reg-
tion. ister via the internal shift register. After each byte
the interface generates in sequence:
Once the Start condition is sent:
– Acknowledge pulse if the ACK bit is set
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set. – EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the Then the interface waits for a read of the SR1 reg-
Slave address, holding the SCL line low (see ister followed by a read of the DR register, holding
Figure 66 Transfer sequencing EV5). the SCL line low (see Figure 66 Transfer se-
quencing EV7).
To close the communication: before reading the
Slave address transmission last byte from the DR register, set the STOP bit to
Then the slave address is sent to the SDA line via generate the Stop condition. The interface goes
the internal shift register. automatically back to slave mode (M/SL bit
In 7-bit addressing mode, one address byte is cleared).
sent. Note: In order to generate the non-acknowledge
In 10-bit addressing mode, sending the first byte pulse after the last received data byte, the ACK bit
including the header sequence causes the follow- must be cleared just before reading the second
ing event: last data byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.

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I2C BUS INTERFACE (Cont’d)

Master Transmitter sion.
Following the address transmission and after SR1 Multimaster Mode
register has been read, the master sends bytes Normally the BERR bit would be set whenever
from the DR register to the SDA line via the inter- unauthorized transmission takes place while
nal shift register. transfer is already in progress. However, an is-
sue will arise if an external master generates an
The master waits for a read of the SR1 register fol- unauthorized Start or Stop while the I2C master
lowed by a write in the DR register, holding the is on the first pulse pulse of a 9-bit transaction. It
SCL line low (see Figure 66 Transfer sequencing is possible to work around this by polling the
EV8). BUSY bit during I2C master mode transmission.
When the acknowledge bit is received, the The resetting of the BUSY bit can then be han-
interface sets: dled in a similar manner as the BERR flag being
set.
– EVF and BTF bits with an interrupt if the ITE bit
is set. – AF: Detection of a non-acknowledge bit. In this
To close the communication: after writing the last case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
byte to the DR register, set the STOP bit to gener-
set the Start or Stop bit.
ate the Stop condition. The interface goes auto-
The AF bit is cleared by reading the I2CSR2 reg-
matically back to slave mode (M/SL bit cleared).
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
Error Cases thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
– BERR: Detection of a Stop or a Start condition at 0 before reading the SR2 register, or be able
during a byte transfer. In this case, the EVF and to correctly handle a second interrupt during the
BERR bits are set by hardware with an interrupt 9th pulse of a transmitted byte.
if ITE is set.
Note that BERR will not be set if an error is de- – ARLO: Detection of an arbitration lost condition.
tected during the first pulse of each 9-bit transac- In this case the ARLO bit is set by hardware (with
tion: an interrupt if the ITE bit is set and the interface
Single Master Mode goes automatically back to slave mode (the M/SL
If a Start or Stop is issued during the first pulse of bit is cleared).
a 9-bit transaction, the BERR flag will not be set Note: In all these cases, the SCL line is not held
and transfer will continue however the BUSY flag low; however,the SDA line can remain low if the
will be reset. To work around this, slave devices last bits transmitted are all 0. It is then necessary
should issue a NACK when they receive a mis- to release both lines by software. The SCL line is
placed Start or Stop. The reception of a NACK or not held low while AF=1 but by other flags (SB or
BUSY by the master in the middle of communica- BTF) that are set at the same time.
tion gives the possibility to reinitiate transmis-

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I2C BUS INTERFACE (Cont’d)

Figure 66. Transfer Sequencing
7-bit Slave receiver:
S Address A Data1 A Data2 A DataN A P
.....
EV1 EV2 EV2 EV2 EV4

7-bit Slave transmitter:

S Address A Data1 A Data2 A DataN NA P
.....
EV1 EV3 EV3 EV3 EV3-1 EV4

7-bit Master receiver:

S Address A Data1 A Data2 A DataN NA P
.....
EV5 EV6 EV7 EV7 EV7

7-bit Master transmitter:

S Address A Data1 A Data2 A DataN A P
.....
EV5 EV6 EV8 EV8 EV8 EV8

10-bit Slave receiver:

S Header A Address A Data1 A DataN A P
.....
EV1 EV2 EV2 EV4

10-bit Slave transmitter:

Sr Header A Data1 A .... DataN A P
EV1 EV3 EV3 . EV3-1 EV4

10-bit Master transmitter

S Header A Address A Data1 A DataN A P
.....
EV5 EV9 EV6 EV8 EV8 EV8

10-bit Master receiver:

Sr Header A Data1 A DataN A P
.....
EV5 EV6 EV7 EV7
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

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I2C BUS INTERFACE (Cont’d)

11.6.5 Low Power Modes
Mode Description
No effect on I2C interface.
WAIT
I2C interrupts cause the device to exit from WAIT mode.
I2C registers are frozen.
HALT In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

11.6.6 Interrupts
Figure 67. Event Flags and Interrupt Generation

ADD10 ITE
BTF
ADSL
SB INTERRUPT
AF
STOPF
ARLO EVF
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.

Enable Exit Exit

Event
Interrupt Event Control from from
Flag
Bit Wait Halt
10-bit Address Sent Event (Master mode) ADD10 Yes No
End of Byte Transfer Event BTF Yes No
Address Matched Event (Slave mode) ADSL Yes No
Start Bit Generation Event (Master mode) SB Yes No
ITE
Acknowledge Failure Event AF Yes No
Stop Detection Event (Slave mode) STOPF Yes No
Arbitration Lost Event (Multimaster configuration) ARLO Yes No
Bus Error Event BERR Yes No

Note: The I2C interrupt events are connected to

the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).

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I2C BUS INTERFACE (Cont’d)

11.6.7 Register Description – In slave mode:
I2C CONTROL REGISTER (CR) 0: No start generation
Read / Write 1: Start generation when the bus is free
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
7 0 This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
0 0 PE ENGC START ACK STOP ITE bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable. Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. This bit is set and cleared by software. It is also
0: Peripheral disabled cleared by hardware in master mode. Note: This
1: Master/Slave capability bit is not cleared when the interface is disabled
Notes: (PE=0).
– When PE=0, all the bits of the CR register and – In master mode:
the SR register except the Stop bit are reset. All 0: No stop generation
outputs are released while PE=0 1: Stop generation after the current byte transfer
– When PE=1, the corresponding I/O pins are se- or after the current Start condition is sent. The
lected by hardware as alternate functions. STOP bit is cleared by hardware when the Stop
– To enable the I2C interface, write the CR register condition is sent.
TWICE with PE=1 as the first write only activates – In slave mode:
the interface (only PE is set).
0: No stop generation
1: Release the SCL and SDA lines after the cur-
Bit 4 = ENGC Enable General Call. rent byte transfer (BTF=1). In this mode the
This bit is set and cleared by software. It is also STOP bit has to be cleared by software.
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac- Bit 0 = ITE Interrupt enable.
knowledged (01h ignored). This bit is set and cleared by software and cleared
0: General Call disabled
by hardware when the interface is disabled
1: General Call enabled (PE=0).
0: Interrupts disabled
Note: In accordance with the I2C standard, when
1: Interrupts enabled
GCAL addressing is enabled, an I2C slave can Refer to Figure 67 for the relationship between the
only receive data. It will not transmit data to the events and the interrupt.
master. SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 66) is de-
Bit 3 = START Generation of a Start condition. tected.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation

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I2C BUS INTERFACE (Cont’d)

I2C STATUS REGISTER 1 (SR1) tection of Stop condition (STOPF=1), loss of bus
Read Only arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
Reset Value: 0000 0000 (00h) 0: Data byte received (if BTF=1)
7 0 1: Data byte transmitted

EVF ADD10 TRA BUSY BTF ADSL M/SL SB Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
Bit 7 = EVF Event flag. condition and cleared by hardware on detection of
This bit is set by hardware as soon as an event oc- a Stop condition. It indicates a communication in
curs. It is cleared by software reading SR2 register progress on the bus. The BUSY flag of the I2CSR1
in case of error event or as described in Figure 66. register is cleared if a Bus Error occurs.
It is also cleared by hardware when the interface is 0: No communication on the bus
disabled (PE=0). 1: Communication ongoing on the bus
0: No event
1: One of the following events has occurred: Bit 3 = BTF Byte transfer finished.
– BTF=1 (Byte received or transmitted) This bit is set by hardware as soon as a byte is cor-
– ADSL=1 (Address matched in Slave mode rectly received or transmitted with interrupt gener-
while ACK=1) ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
– SB=1 (Start condition generated in Master ister. It is also cleared by hardware when the inter-
mode) face is disabled (PE=0).
– AF=1 (No acknowledge received after byte – Following a byte transmission, this bit is set after
transmission) reception of the acknowledge clock pulse. In
– STOPF=1 (Stop condition detected in Slave case an address byte is sent, this bit is set only
mode) after the EV6 event (See Figure 66). BTF is
– ARLO=1 (Arbitration lost in Master mode) cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– BERR=1 (Bus error, misplaced Start or Stop
condition detected) – Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
– ADD10=1 (Master has sent header byte) ACK=1. BTF is cleared by reading SR1 register
– Address byte successfully transmitted in Mas- followed by reading the byte from DR register.
ter mode. The SCL line is held low while BTF=1.
0: Byte transfer not done
Bit 6 = ADD10 10-bit addressing in Master mode. 1: Byte transfer succeeded
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed Bit 2 = ADSL Address matched (Slave mode).
by a write in the DR register of the second address This bit is set by hardware as soon as the received
byte. It is also cleared by hardware when the pe- slave address matched with the OAR register con-
ripheral is disabled (PE=0). tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
0: No ADD10 event occurred. ing SR1 register or by hardware when the inter-
1: Master has sent first address byte (header) face is disabled (PE=0).
The SCL line is held low while ADSL=1.
Bit 5 = TRA Transmitter/Receiver. 0: Address mismatched or not received
When BTF is set, TRA=1 if a data byte has been 1: Received address matched
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-

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I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface Bit 2 = ARLO Arbitration lost.
is in Master mode (writing START=1). It is cleared This bit is set by hardware when the interface los-
by hardware after detecting a Stop condition on es the arbitration of the bus to another master. An
the bus or a loss of arbitration (ARLO=1). It is also interrupt is generated if ITE=1. It is cleared by soft-
cleared when the interface is disabled (PE=0). ware reading SR2 register or by hardware when
0: Slave mode the interface is disabled (PE=0).
1: Master mode
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start The SCL line is not held low while ARLO=1.
condition is generated (following a write 0: No arbitration lost detected
START=1). An interrupt is generated if ITE=1. It is 1: Arbitration lost detected
cleared by software reading SR1 register followed Note:
by writing the address byte in DR register. It is also – In a Multimaster environment, when the interface
cleared by hardware when the interface is disa- is configured in Master Receive mode it does not
bled (PE=0). perform arbitration during the reception of the
0: No Start condition Acknowledge Bit. Mishandling of the ARLO bit
1: Start condition generated from the I2CSR2 register may occur when a sec-
ond master simultaneously requests the same
I2C STATUS REGISTER 2 (SR2) data from the same slave and the I2C master
Read Only does not acknowledge the data. The ARLO bit is
Reset Value: 0000 0000 (00h) then left at 0 instead of being set.
7 0
Bit 1 = BERR Bus error.
0 0 0 AF STOPF ARLO BERR GCAL This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
Bit 7:5 = Reserved. Forced to 0 by hardware. terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
Bit 4 = AF Acknowledge failure. 0: No misplaced Start or Stop condition
This bit is set by hardware when no acknowledge 1: Misplaced Start or Stop condition
is returned. An interrupt is generated if ITE=1. It is Note:
cleared by software reading SR2 register or by – If a Bus Error occurs, a Stop or a repeated Start
hardware when the interface is disabled (PE=0). condition should be generated by the Master to
re-synchronize communication, get the transmis-
The SCL line is not held low while AF=1 but by oth- sion acknowledged and the bus released for fur-
er flags (SB or BTF) that are set at the same time. ther communication
0: No acknowledge failure
1: Acknowledge failure
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
Bit 3 = STOPF Stop detection (Slave mode). dress is detected on the bus while ENGC=1. It is
This bit is set by hardware when a Stop condition cleared by hardware detecting a Stop condition
is detected on the bus after an acknowledge (if (STOPF=1) or when the interface is disabled
ACK=1). An interrupt is generated if ITE=1. It is (PE=0).
cleared by software reading SR2 register or by 0: No general call address detected on bus
hardware when the interface is disabled (PE=0). 1: general call address detected on bus
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected

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I2C BUS INTERFACE (Cont’d)

I2C CLOCK CONTROL REGISTER (CCR) I2C DATA REGISTER (DR)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 D7 D6 D5 D4 D3 D2 D1 D0

Bit 7 = FM/SM Fast/Standard I2C mode.

This bit is set and cleared by software. It is not Bit 7:0 = D[7:0] 8-bit Data Register.
cleared when the interface is disabled (PE=0). These bits contain the byte to be received or trans-
0: Standard I2C mode mitted on the bus.
1: Fast I2C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
Bit 6:0 = CC[6:0] 7-bit clock divider. ister.
These bits select the speed of the bus (FSCL) de- – Receiver mode: the first data byte is received au-
pending on the I2C mode. They are not cleared tomatically in the DR register using the least sig-
when the interface is disabled (PE=0). nificant bit of the address.
Refer to the Electrical Characteristics section for Then, the following data bytes are received one
the table of values. by one after reading the DR register.
Note: The programmed FSCL assumes no load on
SCL and SDA lines.

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I2C BUS INTERFACE (Cont’d)

I2C OWN ADDRESS REGISTER (OAR1) I2C OWN ADDRESS REGISTER (OAR2)
Read / Write Read / Write
Reset Value: 0000 0000 (00h) Reset Value: 0100 0000 (40h)
7 0 7 0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 FR1 FR0 0 0 0 ADD9 ADD8 0

7-bit Addressing Mode Bit 7:6 = FR[1:0] Frequency bits.

Bit 7:1 = ADD[7:1] Interface address. These bits are set by software only when the inter-
These bits define the I2C bus address of the inter- face is disabled (PE=0). To configure the interface
face. They are not cleared when the interface is to I2C specified delays select the value corre-
disabled (PE=0). sponding to the microcontroller frequency FCPU.
fCPU FR1 FR0
Bit 0 = ADD0 Address direction bit. < 6 MHz 0 0
This bit is don’t care, the interface acknowledges 6 to 8 MHz 0 1
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored. Bit 5:3 = Reserved

10-bit Addressing Mode Bit 2:1 = ADD[9:8] Interface address.

Bit 7:0 = ADD[7:0] Interface address. These are the most significant bits of the I2C bus
These are the least significant bits of the I2C bus address of the interface (10-bit mode only). They
address of the interface. They are not cleared are not cleared when the interface is disabled
when the interface is disabled (PE=0). (PE=0).

Bit 0 = Reserved.

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I²C BUS INTERFACE (Cont’d)

Table 24. I2C Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

I2CCR PE ENGC START ACK STOP ITE

0058h
Reset Value 0 0 0 0 0 0 0 0
I2CSR1 EVF ADD10 TRA BUSY BTF ADSL M/SL SB
0059h
Reset Value 0 0 0 0 0 0 0 0
I2CSR2 AF STOPF ARLO BERR GCAL
005Ah
Reset Value 0 0 0 0 0 0 0 0
I2CCCR FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0
005Bh
Reset Value 0 0 0 0 0 0 0 0
I2COAR1 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
005Ch
Reset Value 0 0 0 0 0 0 0 0
I2COAR2 FR1 FR0 ADD9 ADD8
005Dh
Reset Value 0 1 0 0 0 0 0 0
I2CDR MSB LSB
005Eh
Reset Value 0 0 0 0 0 0 0 0

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11.7 I2C TRIPLE SLAVE INTERFACE WITH DMA (I2C3S)

11.7.1 Introduction ■ Fast Mode (transfers 256 bytes at up to 400
The I2C3S interface provides three I2C slave func- kHz)
tions, supporting both standard (up to 100kHz) ■ Transfer error detection and handling
and fast I2C mode (100 to 400 kHz). Special fea- ■ 3 interrupt flags per address for maximum
tures are provided for: flexibility
2 2 Two interrupt request lines (one for Slaves 1
■ Full-speed emulation of standard I C E PROMs ■

■ Receiving commands to perform user-defined

and 2, the other for Slave 3)
operations such as IAP ■ Full emulation of standard I2C EEPROMs:
11.7.2 Main Features – Supports 5 read/write commands and com-
■ Three user configurable independent slave
bined format
addresses can be individually enabled – No I2C clock stretching
■ 2x 256 bytes and 1x 128 bytes buffers with fixed – Programmable page size (8/16 bytes) or full
addresses in RAM buffer
■ 7-bit Addressing – Configurable write protection
2
■ DMA transfer to/from I C bus and RAM ■ Data integrity and byte-pair coherency when
■ Standard (transfers 256 bytes at up to 100 kHz) reading 16-bit words from I2C bus

Figure 68. I2C3S Interface Block Diagram

I2C SLAVE ADDRESS 1

I2C SLAVE ADDRESS 2

DATA E2PROM
I2C SLAVE ADDRESS 3

DATA/ADDRESS BUS
256 BYTES
RAM

COMPARATOR SLAVE 1 BUFFER

256 BYTES

8-BIT
SDA or SDAI
SHIFT REGISTER SLAVE 2 BUFFER
256 BYTES
SCL or SCLI

SLAVE 3 BUFFER
128 BYTES
DMA

CONTROL LOGIC SHADOW

REGISTER

Slave 1 or 2 Interrupt
CPU
Slave 3 Interrupt

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I2C3S INTERFACE (Cont’d)

11.7.3 General Description slave addresses which are user programmable.
In addition to receiving and transmitting data, The three I2C slave addresses can be individually
I2C3S converts it from serial to parallel format and enabled/disabled by software.
vice versa. The interrupts are enabled or disabled Since the I2C3S interface always acts as a slave it
by software. The I2C3S is connected to the I2C does not generate a clock. Data and addresses
bus by a data pin (SDA) and by a clock pin (SCL). are transferred as 8-bit bytes, MSB first. The first
It can be connected both with a standard I2C bus byte following the start condition contains the
and a Fast I2C bus. The interface operates only in slave address. A 9th clock pulse follows the 8
Slave mode as transmitter/receiver. clock cycles of a byte transfer, during which the re-
In order to fully emulate standard I2C EEPROM ceiver must send an acknowledge bit to the trans-
devices with highest transfer speed, the peripheral mitter.
prevents I2C clock signal stretching and performs
data transfer between the shift register and the 11.7.3.2 SDA/SCL Line Control
RAM buffers using DMA.
When the I2C3S interface is enabled, the SDA and
11.7.3.1 Communication Flow SCL ports must be configured as floating inputs. In
A serial data transfer normally begins with a start this case, the value of the external pull-up resistor
condition and ends with a stop condition. Both used depends on the application.
start and stop conditions are generated by an ex- When the I2C3S interface is disabled, the SDA
ternal master. Refer to Figure 64 for the standard and SCL ports revert to being standard I/O port
protocol. The I2C3S is not a master and is not ca- pins.
pable of generating a start/stop condition on the
SDA line. The I2C3S is capable of recognising 3
Figure 69. I2C BUS Protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION
VR02119B

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I2C3S INTERFACE (Cont’d)

11.7.4 Functional Description A DMA request is issued to the DMA controller on
The three slave addresses 1, 2 and 3 can be used reception of a byte or just before transmission of a
as general purpose I2C slaves. They also support byte.
all features of standard I2C EEPROMs like the ST When a byte is written by DMA in RAM, the CPU is
M24Cxx family and are able to fully emulate them. stalled for max. 2 cycles. When several bytes are
Slaves 1 and 2 are mapped on the same interrupt transferred from the I2C bus to RAM, the DMA re-
vector. Slave 3 has a separate interrupt vector with leases between each byte and the CPU resumes
higher priority. processing until the DMA writes the next byte.
The three slave addresses are defined by writing 11.7.4.3 RAM Buffer Write Protection
the 7 MSBs of the address in the I2C3SSAR1, By setting the WP1/WP2 bits in the I2C3SCR2
I2C3SSAR2 and I2C3SSAR3 registers. The register it is possible to protect the RAM buffer of
slaves are enabled by setting the enable bits in the Slaves 1/2 respectively against write access from
same registers. the master.
Each slave has its own RAM buffer at a fixed loca- If a write operation is attempted, the slave address
tion in the ST7 RAM area. is acknowledged, the current address register is
– Slaves 1 and 2 have 256-byte buffers which can overwritten, data is also acknowledged but it is not
be individually protected from I2C master write written to the RAM. Both the current address and
accesses. byte count registers are incremented as in normal
operation.
– Slave 3 has a 128-byte RAM buffer without write
protection feature. In case of write access to a write protected ad-
dress, no interrupt is generated and the BusyW bit
All three slaves have individual read flags (RF) in the I2C3SCR2 register is not set.
and write flags (WF) with maskable interrupts.
These flags are set when the I2C master has com- Only write operations are disabled/enabled. Read
pleted a read or write operation. operations are not affected.
11.7.4.1 Paged operation 11.7.4.4 Byte-pair coherency for I2C Read
operations
To allow emulation of Standard I2C EEPROM de-
vices, pages can be defined in the RAM buffer. Byte-pair coherency allows the I2C master to read
The pages are configured using the PL[1:0] bits in a 16-bit word and ensures that it is not corrupted
the I2C3SCR1 register. 8/16-Byte page length has by a simultaneous CPU update. Two mechanisms
to be selected depending on the EEPROM device are implemented, covering the two possible cases:
to emulate. The Full Page option is to be used 1. CPU updates a word in RAM after the first byte
when no paging of the RAM buffer is required. The has been transferred to the I2C shift register
configuration is common to the 3 slave addresses. from RAM. In this case, the first byte read from
The Full Page configuration corresponds to 256 RAM would be the MSB of the old word and
bytes for address 1 and 2 and to 128 bytes for ad- 2nd byte would be the LSB of the new word.
dress 3. To prevent this corruption, the I2C3S uses
DMA to systematically read a 2-byte word when
Paging affects the handling of rollover when write
it receives a read command from the I2C mas-
operations are performed. In case the bottom of
ter. The MSB of the word should be at address
the page is reached, the write continues from the
2n. Using DMA, the MSB is moved from RAM
first address of the same page. Page length does
address 2n to the I2C shift register and the LSB
not affect read operations: rollover is done on the
from RAM address 2n+1 moved to a shadow
whole RAM buffer whatever the configured page
register in the I2C3S peripheral. The CPU is
length.
stalled for a maximum of 2 cycles during word
The Byte count register is reset when it reaches transfer.
256 bytes, whatever the page length, for all slave In case only one byte is read, the unused con-
addresses, including slave 3. tent of the shadow register will be automatically
11.7.4.2 DMA overwritten when a new read operation is per-
formed.
The I2C slaves use a DMA controller to write/read
data to/from their RAM buffer. In case a second byte is read in the same I2C
message (no Stop or Restart condition) the
content of the shadow register is transferred to
the shift register and transmitted to the master.

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I2C3S INTERFACE (Cont’d) 2. Enable Word mode by setting the B/W and
This process continues until a Stop or Restart BusyW bits in the I2C3SCR2 register. BusyW
condition occurs. bit is set to 1 when modifying any bits in Control
2. I2C3S attempts to read a word while the CPU is Register 2. Writing a 1 to this bit does not actu-
updating the RAM buffer. To prevent data cor- ally modify BusyW but prevents accidental
ruption, the CPU must switch operation to Word clearing of the bit.
mode prior to updating a word in the RAM 3. Write Byte 1 in an even address in RAM. The
buffer. Word mode is enabled by software using byte is not actually written in RAM but in a
the B/W bit in the I2C3SCR2 register. In Word shadow register. This address must be within
mode, when the CPU writes the MSB of a word the I2C RAM buffer of slave addresses 1, 2 or
to address 2n, it is stored in a shadow register 3.
rather than being actually written in RAM. When 4. Write Byte 2 in the next higher address in RAM.
the CPU writes the second byte (the LSB) at This byte is actually written in RAM. During the
address 2n+1, it is directly written in RAM. The next cycle, the shadow register content is writ-
next cycle after the write to address 2n+1, the ten in the lower address. The DMA request is
MSB is automatically written from the shadow disabled during this cycle.
register to RAM address 2n. DMA is disabled 5. Byte mode resumes automatically after writing
for a 1 cycle while the CPU is writing a word. byte 2 and DMA is re-enabled.
Word mode is disabled by hardware after the 6. Enable interrupts
word update is performed. It must be enabled
Note: Word mode does not guarantee byte-pair
before each word update by CPU.
coherency of words WRITTEN by the I2C master
Use the following procedure when the ST7 writes in RAM and read by the ST7. Byte pair coherency
a word in RAM: in this case must be handled by software.
1. Disable interrupts
Figure 70. 16-bit Word Write Operation Flowchart
HOST ST7 I2C3SNS ST7 CPU
SENDS ADDRESS DECODES I2C3SNS ADDRESS
AND WRITE BIT DECODES R/W BIT NORMAL EXECUTION
SETS WRITE FLAG

UPDATES CURRENT ADDRESS-

SENDS WRITE ADDRESS
REGISTER

ISSUES DMA REQUEST HALTS EXECUTION

N
WORD MODE?
1 Cycle
Y
Repeat Max
DELAYS WHILE CPU
COMPLETES WORD WRITE

SENDS 1 BYTE OF DATA WRITES ONE BYTE TO RAM RESUMES EXECUTION 1 Cycle
Max

SETS BUSYW IN CONTROL -

STOP CONDITION REGISTER + I2C3S DISABLED SERVICES I2C3SNS INTERRUPT
ISSUES INTERRUPT

RESETS I2C3SNS WRITE FLAG READS I2C3SNS STATUS REGISTER

ENABLES I2C3SNS UPDATES CONTROL REGISTER

Byte-Pair Coherency ensured by setting Word Mode

RAM start address depends on slave address

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Figure 71. 16-bit Word Read Operation Flowchart

HOST ST7 I2C3SNS ST7 CPU
SENDS ADDRESS DECODES I2C3SNS ADDRESS
AND READ BIT DECODES R/W BIT NORMAL EXECUTION
SETS READ FLAG

UPDATES CURRENT ADDRESS-

SENDS READ ADDRESS
REGISTER

ISSUES DMA REQUEST HALTS EXECUTION

N
WORD MODE?

DELAYS WHILE CPU

COMPLETES WORD WRITE

3 Cycles
Repeat
READS 1 WORD FROM RAM RESUMES EXECUTION Max
RECEIVES BYTE 1
BYTE 1 => SHIFT REG
BYTE 2 => SHADOW REG
RELEASES DMA

Y
STOP?

RECEIVES BYTE 2 SHADOW REG => SHIFT REG

STOP CONDITION UPDATES STATUS + DMA CNTL SERVICES I2C3SNS INTERRUPT

RESETS READ FLAG READS I2C3SNS STATUS REGISTER

Byte-Pair Coherency ensured by setting Word Mode + DMA on Words

RAM start address depends on slave address

11.7.4.5 Application Note the shift register. Then it is compared with the
Taking full advantage of its higher interrupt priority three addresses of the interface to decode which
Slave 3 can be used to allow the addressing mas- slave of the interface is being addressed.
ter to send data bytes as commands to the ST7. Address not matched: the interface ignores it
These commands can be decoded by the ST7 and waits for another Start condition.
software to perform various operations such as Address matched: the interface generates in se-
programming the Data E2PROM via IAP (In-Appli- quence the following:
cation Programming).
– An Acknowledge pulse
Slave 3 writes the command byte and other data in
the RAM and generates an interrupt. The ST7 then – Depending on the LSB of the slave address sent
decodes the command and processes the data as by the master, slaves enter transmitter or receiv-
decoded from the command byte. The ST7 also er mode.
writes a status byte in the RAM which the address- – Send an interrupt to the CPU after completion of
ing master can poll. the read/write operation after detecting the Stop/
11.7.5 Address Handling Restart condition on the SDA line.
As soon as a start condition is detected, the
address is received from the SDA line and sent to

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Notes: During this operation the I2C slave reads the data
– The Status Register has to be read to clear the pointed by the current address register. Refer to
event flag associated with the interrupt Figure 75.
– An interrupt will be generated only if the interrupt
enable bit is set in the Control Register Random Read: Random read requires a dummy
– Slaves 1 and 2 have a common interrupt and the byte write sequence to load in the byte address.
Slave 3 has a separate interrupt. The addressing device then generates restart
condition and resends the device address similar
– At the end of write operation, I2C3S is temporar- to current address read with the read/write bit high.
ily disabled by hardware by setting BusyW bit in Refer to Figure 76. Some types of I2C masters
CR2. The byte count register, status register and perform a dummy write with a stop condition and
current address register should be saved before then a current address read.
resetting BusyW bit.
In either case, the slave generates a DMA request,
. sends an acknowledge and serially clocks out the
11.7.5.1 Slave Reception (Write operations) data.
Byte Write: The Slave address is followed by an When the memory address limit is reached the
8-bit byte address. Upon receipt of this address an current address will roll over and the random read
acknowledge is generated, address is moved into will continue till the addressing master sends a
the current address register and the 8 bit data is stop condition.
clocked in. Once the data is shifted in, a DMA
request is generated and the data is written in the
RAM. The addressing device will terminate the Sequential Read: Sequential reads are initiated
write sequence with a stop condition. Refer to by either a current address read or a random
Figure 73 address read. After the addressing master
receives the data byte it responds with an
acknowledge. As long as the slave receives an
Page Write: A page write is initiated in similar way acknowledge it will continue to increment the
to a byte write, but the addressing device does not current address register and clock out sequential
send a stop condition after the first data byte. The data bytes.
page length is programmed using bits 7:6 (PL[1:0]) When the memory address limit is reached the
in the Control Register1. current address will roll over and the sequential
The current address register value is incremented read will continue till the addressing master sends
by one every time a byte is written. When this a stop condition. Refer to Figure 78
address reaches the page boundary, the next byte
will be written at the beginning of the same page.
Refer to Figure 74. 11.7.5.3 Combined Format:
If a master wants to continue communication
either with another slave or by changing the
11.7.5.2 Slave Transmission (Read Operations) direction of transfer then the master would
Current Address Read: The current address generate a restart and provide a different slave
register maintains the last address accessed address or the same slave address with the R/W
during the last read or write operation incremented bit reversed. Refer to Figure 79.
by one.

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I2C3S INTERFACE (Cont’d)

11.7.5.4 Rollover Handling The page boundaries are defined based on page
The RAM buffer of each slave is divided into pages size configuration using PL[1:0] bit in the
whose length is defined according to PL1:0 bits in I2C3SCR1 register. If an 8-byte page size is
I2C3SCR1. Rollover takes place in these pages as selected, the upper 5 bits of the RAM address are
described below. fixed and the lower 3 bits are incremented. For
example, if the page write starts at register
In the case of Page Write, if the number of data address 0x0C, the write will follow the sequence
bytes transmitted is more than the page length, the 0x0C, 0x0D, 0x0E, 0x0F, 0x08, 0x09, 0x0A, 0x0B.
current address will roll over to the first byte of the If a 16-byte page size is selected, the upper 4 bits
current page and the previous data will be of the RAM address are fixed and the lower 4 bits
overwritten. This page size is configured using are incremented. For example if the page write
PL[1:0] bit in the I2C3SCR1 register. starts at register address 0x0C, the write will follow
In case of Sequential Read, if the current address the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,
register value reaches the memory address limit 0x01, etc.
the address will roll over to the first address of the 11.7.5.5 Error Conditions
reserved area for the respective slave.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the BERR bit
There is no status flag to indicate the roll over. is set by hardware with an interrupt if ITER is set.
During a stop condition, the interface discards
the data, releases the lines and waits for another
Note: Start condition. However, a BERR on a Start
The reserved areas for slaves 1 and 2 have a limit condition will result in the interface discarding the
of 256 bytes. The area for slave 3 is 128 bytes. data and waiting for the next slave address on
The MSB of the address is hardwired, the the bus.
addressing master therefore needs to send only – NACK: Detection of a non-acknowledge bit not
an 8 bit address. followed by a Stop condition. In this case, NACK
bit is set by hardware with an interrupt if ITER is
set.
Figure 72. Transfer Sequencing

7-bit Slave receiver:

S Address A Data1 A Data2 A DataN A P
.....
WF BusyW

7-bit Slave transmitter:

S Address A Data1 A Data2 A DataN NA P
.....
RF

Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

WF = WF event, WFx bit is set (with interrupt if ITWEx=1, after Stop or Restart conditions), cleared by
reading the I2C3SSR register while no communication is ongoing.
RF = RF event, RFx is set (with interrupt if ITREx=1, after Stop or Restart conditions) , cleared by reading
the I2C3SSR register while no communication is ongoing.
BusyW = BusyW flag in the I2C3CR2 register set, cleared by software writing 0.
Note: The I2C3S supports a repeated start (Sr) in place of a stop condition (P).

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Figure 73. Byte Write

Start SA W Ack BA Ack Data Ack Stop

Figure 74. Page Write

Start SA W Ack BA Ack Data Ack Data Ack Stop

Figure 75. Current Address Read

Start SA R Ack Data Nack Stop

Figure 76. Random Read (Dummy write + restart + current address read)
Start SA W Ack BA Ack Start SA R Ack Data Nack Stop

Figure 77. Random Read (Dummy write + stop + start + current address read)

Start SA W Ack BA Ack Stop Start SA R Ack Data Nack Stop

Figure 78. Sequential Read

Start SA R Ack Data Ack Data Ack Data Nack Stop

Figure 79. Combined Format for Read

Start SA R Ack Data Nack Restart SA R Ack Data Nack Stop

Legend: SA - Slave Address W: Write

BA - Byte Address R: Read

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0.1.4I2C3S INTERFACE (Cont’d)

11.7.6 Low Power Modes
Mode Description
No effect on I2C interface.
WAIT
I2C interrupts causes the device to exit from WAIT mode.
I2C registers are frozen.
HALT In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
I2C registers are frozen.
ACTIVE In ACTIVE HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C
HALT interface resumes operation when the MCU is woken up by an interrupt with “exit from ACTIVE HALT mode”
capability.

11.7.7 Interrupt Generation

Figure 80. Event Flags and Interrupt Generation
Restart: Restart condition on SDA
Stop: Stop condition on SDA
Restart Dummy Write: True if no data is written in RAM
Stop Write Protect: True for Write operation and if slaves
Dummy Write Data Status Flag are write protected (since this is applicable for
Write Protect slaves 1 and 2. For slave 3 and for Read operation
write protect will always be 0)
Data Status Flag: Actual Interrupt is produced when
this condition is true

Data Status Flag

RF1
RF2
ITRE1/2

NACK
INTERRUPT 1

ITER (Slave address 1/2)

BERR
WF1
WF2
ITWE1/2
Data Status Flag

Data Status Flag

WF3
ITWE3

BERR
INTERRUPT 2

ITER
NACK (Slave address 3)
RF3
ITRE3
Data Status Flag

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Note: Read/Write interrupts are generated only after stop or restart conditions. Figure 80 shows the con-
ditions for the generation of the two interrupts.
Enable Exit Exit
Interrupt Event Control from from
Flag
Bit Wait Halt
Interrupt on write to Slave 1 WF1 ITWE1 Yes No
Interrupt on write to Slave 2 WF2 ITWE1 Yes No
Interrupt on write to Slave 3 WF3 ITWE2 Yes No
Interrupt on Read from Slave 1, Slave 2 or Slave 3. RF1- RF3 ITREx Yes No
BERR,
Errors ITER Yes No
NACK

11.7.8 Register Description

I2C 3S CONTROL REGISTER 1 (I2C3SCR1) Bit 2 = ITRE1/2 Interrupt enable on read from
Read / Write Slave 1 or 2
Reset Value: 0000 0000 (00h) This bit is set and cleared by software It is also
cleared by hardware when interface is disabled
7 0 (PE =0)
0: Interrupt on Read from Slave 1 or 2 disabled
ITRE1/ ITWE 1: Interrupt on Read from Slave 1 or 2 enabled
PL1 PL0 0 ITER ITRE3 ITWE3
2 1/2
Bit 1= ITWE3 Interrupt enable on write to Slave 3
This bit is set and cleared by software. It is also
Bits 7:6 = PL1:0 Page length configuration cleared by hardware when interface is disabled.
This bit is set and cleared by software. It is also 0: Interrupt after write to Slave 3 disabled
cleared by hardware when the interface is disa- 1: Interrupt after write to Slave 3 enabled
bled (PE=0).
PL1 PL0 Page length Bit 0 = ITWE1/2 Interrupt enable on write to Slave
0 0 8 1 or 2
This bit is set and cleared by software. It is also
0 1 16
cleared by hardware when interface is disabled
Full Page (256 bytes for slave 1 & 2, 128 software. It is also cleared by hardware when
1 0
bytes for slave 3) when interface is disabled.
1 1 NA 0: Interrupt after write to Slave 1 or 2 disabled
1: Interrupt after write to Slave 1 or 2 enabled
Bit 5 = Reserved, must be kept at 0.
I2C CONTROL REGISTER 2 (I2C3SCR2)
Bit 4 = ITER BERR / NACK Interrupt enable Read / Write
This bit is set and cleared by software. It is also Reset Value: 0000 0000 (00h)
cleared by hardware when the interface is disa-
bled (PE=0). 7 0
0: BERR / NACK interrupt disabled
1: BERR / NACK interrupt enabled 0 0 0 WP2 WP1 PE BusyW B/W

Note: In case of error, if ITER is enabled either in-

terrupt 1 or 2 is generated depending on which Bits 7:5 = Reserved, must be kept at 0.
slave flags the error (see Figure 80).
Bit 4= WP2 Write Protect enable for Slave 2
Bit 3= ITRE3 Interrupt enable on read from Slave 3 This bit is set and cleared by software. It is also
This bit is set and cleared by software It is also cleared by hardware when the interface is disa-
cleared by hardware when interface is disabled bled (PE=0)
(PE =0). 0: Write access to Slave 2 RAM buffer enabled
0: Interrupt on Read from Slave 3 disabled 1: Write access to Slave 2 RAM buffer disabled
1: Interrupt on Read from Slave 3 enabled

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I2C3S INTERFACE (Cont’d) Note: When word mode is enabled, all interrupts
Bit 3= WP1 Write Protect enable for Slave 1 should be masked while the word is being written
This bit is set and cleared by software. It is also in RAM.
cleared by hardware when the interface is disa-
bled (PE=0). I2C3S STATUS REGISTER (I2C3SSR)
0: Write access to Slave 1 RAM buffer enabled Read Only
1: Write access to Slave 1 RAM buffer disabled Reset Value: 0000 0000 (00h)
7 0
Notes: (Applicable for both WP2/ WP1)
– Only write operations are disabled/enabled. NACK BERR WF3 WF2 WF1 RF3 RF2 RF1
Read operations are not affected.
– If a write operation is attempted, the slave ad-
Bit 7= NACK Non Acknowledge not followed by
dress is acknowledged, the current address reg-
ister is overwritten, data is also acknowledged Stop
but it is not written to the RAM. This bit is set by hardware when a non acknowl-
edge returned by the master is not followed by a
– Both the current address and byte count regis-
ters are incremented as in normal operation. Stop or Restart condition. It is cleared by software
reading the SR register or by hardware when the
– No interrupt generated if slave is write protected interface is disabled (PE=0).
– BusyW will not be set if slave is write protected 0: No NACK error occurred
1: Non Acknowledge not followed by Stop
Bit 2= PE Peripheral enable Bit 6 = BERR Bus error
This bit is set and cleared by software. This bit is set by hardware when the interface de-
0: Peripheral disabled tects a misplaced Start or Stop condition. It is
1: Slave capability enabled cleared by software reading SR register or by
hardware when the interface is disabled (PE=0).
Note: To enable the I2C interface, write the CR
register TWICE with PE=1 as the first write only The SCL line is not held low while BERR=1.
activates the interface (only PE is set) 0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 1 = BusyW Busy on Write to RAM Buffer
This bit is set by hardware when a STOP/ RE-
START is detected after a write operation. The Bit 5 = WF3 Write operation to Slave 3
I2C3S peripheral is temporarily disabled till this bit This bit is set by hardware on reception of the di-
is reset. This bit is cleared by software. If this bit is rection bit in the I2C address byte for Slave 3. This
not cleared before the next slave address recep- bit is cleared when the status register is read when
there is no communication ongoing or when the
tion, further communication will be non-acknowl-
edged. This bit is set to 1 when modifying any bits peripheral is disabled (PE = 0)
in Control Register 2. Writing a 1 to this bit does 0: No write operation to Slave 3
not actually modify BusyW but prevents acciden- 1: Write operation performed to Slave 3
tally clearing of the bit.
0: No BusyW event occurred Bit 4 = WF2 Write operation to Slave 2
1: A STOP/ RESTART is detected after a write op- This bit is set by hardware on reception of the di-
eration rection bit in the I2C address byte for Slave 2. This
bit is cleared when the status register is read when
Bit 0 = B/W Byte / Word Mode there is no communication ongoing or when the
This control bit must be set by software before a peripheral is disabled (PE = 0)
word is updated in the RAM buffer and cleared by 0: No write operation to Slave 2
hardware after completion of the word update. In 1: Write operation performed to Slave 2
Word mode the CPU cannot be interrupted when it
is modifying the LSB byte and MSB byte of the
word. This mode is to ensure the coherency of Bit 3 = WF1 Write operation to Slave 1
data stored as words. This bit is set by hardware on reception of the di-
0: Byte mode rection bit in the I2C address byte for Slave 1. This
1: Word mode bit is cleared by software when the status register
is read when there is no communication ongoing

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or by hardware when the peripheral is disabled is not limited by the full page length. It is also
(PE = 0). cleared by hardware when interface is disabled
0: No write operation to Slave 1 (PE =0).
1: Write operation performed to Slave 1
I2C3S INTERFACE (Cont’d)
I2C SLAVE 1 ADDRESS REGISTER
Bit 2 = RF3 Read operation from Slave 3 (I2C3SSAR1)
This bit is set by hardware on reception of the di- Read / Write
rection bit in the I2C address byte for Slave 3. It is Reset Value : 0000 0000 (00h)
cleared by software reading the SR register when
there is no communication ongoing. It is also 7 0
cleared by hardware when the interface is disa-
bled (PE=0). ADDR ADDR ADDR ADDR ADDR ADDR ADDR
EN1
0: No read operation from Slave 3 7 6 5 4 3 2 1
1: Read operation performed from Slave 3
Bits 7:1 = ADDR[7:1] Address of Slave 1
This register contains the first 7 bits of Slave 1 ad-
Bit 1= RF2 Read operation from Slave 2 dress (excluding the LSB) and is user program-
This bit is set by hardware on reception of the di- mable. It is also cleared by hardware when inter-
rection bit in the I2C address byte for Slave 2. It is face is disabled (PE =0).
cleared by software reading the SR register when
there is no communication ongoing. It is also Bit 0= EN1 Enable bit for Slave Address 1
cleared by hardware when the interface is disa- This bit is used to enable/disable Slave Address 1.
bled (PE=0). It is also cleared by hardware when interface is
0: No read operation from Slave 2 disabled (PE =0).
1: Read operation performed from Slave 2 0: Slave Address 1 disabled
1: Slave Address 1 enabled
Bit 0= RF1 Read operation from Slave 1
This bit is set by hardware on reception of the di- I2C SLAVE 2 ADDRESS REGISTER
rection bit in the I2C address byte for Slave 1. It is (I2C3SSAR2)
cleared by software reading SR register when Read / Write
there is no communication ongoing. It is also Reset Value: 0000 0000 (00h)
cleared by hardware when the interface is disa- 7 0
bled (PE=0).
0: No read operation from Slave 1 ADDR ADDR ADDR ADDR ADDR ADDR ADDR
1: Read operation performed from Slave 1 EN2
7 6 5 4 3 2 1

I2C BYTE COUNT REGISTER (I2C3SBCR) Bits 7:1 = ADDR[7:1] Address of Slave 2.
Read only This register contains the first 7 bits of Slave 2 ad-
Reset Value: 0000 0000 (00h) dress (excluding the LSB) and is user programma-
ble. It is also cleared by hardware when interface
7 0 is disabled (PE =0).

NB7 NB6 NB5 NB4 NB3 NB2 NB1 NB0 Bit 0= EN2 Enable bit for Slave Address 2
This bit is used to enable/disable Slave Address 2.
Bits 7:0 = NB [7:0] Byte Count Register It is also cleared by hardware when interface is
This register keeps a count of the number of bytes disabled (PE =0).
received or transmitted through any of the three 0: Slave Address 2 disabled
addresses. This byte count is reset after reception 1: Slave Address 2 enabled
by a slave address of a new transfer and is incre-
mented after each byte is transferred. This register

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I2C3S INTERFACE (Cont’d)

I2C SLAVE 3 ADDRESS REGISTER I2C SLAVE 2 MEMORY CURRENT ADDRESS

(I2C3SSAR3) REGISTER (I2C3SCAR2)
Read / Write Read only
Reset Value: 0000 0000 (00h) Reset Value: 0000 0000 (00h)
7 0 7 0

ADDR ADDR ADDR ADDR ADDR ADDR ADDR CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
EN3
7 6 5 4 3 2 1

Bit 7:0 = CA[7:0] Current address of Slave 2 buffer

This register contains the 8-bit offset of Slave Ad-
Bit 7:1 = ADDR[7:1] Address of Slave 3 dress 2 reserved area in RAM. It is also cleared by
This register contains the first 7 bits of Slave 3 ad- hardware when interface is disabled (PE =0).
dress (excluding the LSB) and is user programma-
ble. It is also cleared by hardware when interface
is disabled (PE =0).
I2C SLAVE 3 MEMORY CURRENT ADDRESS
Bit 0= EN3 Enable bit for Slave Address 3 REGISTER (I2C3SCAR3)
This bit is used to enable/disable Slave Address 3. Read only
It is also cleared by hardware when interface is Reset Value: 0000 0000 (00h)
disabled (PE =0). 7 0
0: Slave Address 3 disabled
1: Slave Address 3 enabled
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

I2C SLAVE 1 MEMORY CURRENT ADDRESS

REGISTER (I2C3SCAR1) Bit 6:0 = CA[6:0] Current address of Slave 3 buffer
Read only This register contains the 8-bit offset of slave ad-
Reset Value: 0000 0000 (00h) dress 3 reserved area in RAM. It is also cleared by
hardware when interface is disabled (PE =0).
7 0
Note: Slave address 3 can store only 128 bytes.
For slave address 3, CA7 bit will remain 0. i.e. if
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 the Byte Address sent is 0x80 then the Current Ad-
dress register will hold the value 0x00 due to an
Bit 7:0 = CA[7:0] Current address of Slave 1 buffer overflow.
This register contains the 8 bit offset of Slave Ad-
dress 1 reserved area in RAM. It is also cleared by
hardware when interface is disabled (PE =0).

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Table 25. I2C3S Register Map

Address Register
7 6 5 4 3 2 1 0
(Hex.) Name

0060h I2C3SCR1 PL1 PL0 0 ITER ITRE3 ITRE1/2 ITWE3 ITWE1/2

0061h I2C3SCR2 0 0 0 WP2 WP1 PE BusyW B/W
0062h I2C3SSR NACK BERR WF3 WF2 WF1 RF3 RF2 RF1
0063h I2C3SBCR NB7 NB6 NB5 NB4 NB3 NB2 NB1 NB1

0064h I2C3SSAR1 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 EN1

0065h I2C3SCAR1 CA 7 .. CA0

0066h I2C3SSAR2 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 EN2

0067h I2C3SCAR2 CA 7 .. CA0

0068h I2C3SSAR3 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 EN3

0069h I2C3SCAR3 CA 7 .. CA0

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11.8 10-BIT A/D CONVERTER (ADC)

11.8.1 Introduction 11.8.2 Main Features

The on-chip Analog to Digital Converter (ADC) pe- ■ 10-bit conversion
ripheral is a 10-bit, successive approximation con- ■ Up to 16 channels with multiplexed input
verter with internal sample and hold circuitry. This ■ Linear successive approximation
peripheral has up to 16 multiplexed analog input
■ Data register (DR) which contains the results
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage ■ Conversion complete status flag
levels from up to 16 different sources. ■ On/off bit (to reduce consumption)
The result of the conversion is stored in a 10-bit The block diagram is shown in Figure 81.
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 81. ADC Block Diagram
fCPU DIV 4 0
fADC
DIV 2 1

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0

AIN1
ANALOG TO DIGITAL
ANALOG
MUX CONVERTER

AINx

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 0 0 D1 D0

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.8.3 Functional Description To read the 10 bits, perform the following steps:
The conversion is monotonic, meaning that the re- 1. Poll the EOC bit
sult never decreases if the analog input does not 2. Read the ADCDRL register
and never increases if the analog input does not.
3. Read the ADCDRH register. This clears EOC
If the input voltage (VAIN) is greater than VAREF automatically.
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in Note: The data is not latched, so both the low and
the ADCDRL register (without overflow indication). the high data register must be read before the next
conversion is complete, so it is recommended to
If the input voltage (VAIN) is lower than VSSA (low- disable interrupts while reading the conversion re-
level voltage reference) then the conversion result sult.
in the ADCDRH and ADCDRL registers is 00 00h.
To read only 8 bits, perform the following steps:
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD- 1. Poll the EOC bit
CDRL registers. The accuracy of the conversion is 2. Read the ADCDRH register. This clears EOC
described in the Electrical Characteristics Section. automatically.
RAIN is the maximum recommended impedance 11.8.3.3 Changing the conversion channel
for an analog input signal. If the impedance is too
The application can change channels during con-
high, this will result in a loss of accuracy due to
version. When software modifies the CH[3:0] bits
leakage and sampling not being completed in the
in the ADCCSR register, the current conversion is
allotted time.
stopped, the EOC bit is cleared, and the A/D con-
11.8.3.1 A/D Converter Configuration verter starts converting the newly selected chan-
The analog input ports must be configured as in- nel.
put, no pull-up, no interrupt. Refer to the «I/O 11.8.4 Low Power Modes
ports» chapter. Using these pins as analog inputs
Note: The A/D converter may be disabled by re-
does not affect the ability of the port to be read as setting the ADON bit. This feature allows reduced
a logic input.
power consumption when no conversion is need-
In the ADCCSR register: ed.
– Select the CS[3:0] bits to assign the analog Mode Description
channel to convert.
11.8.3.2 Starting the Conversion WAIT No effect on A/D Converter
In the ADCCSR register: A/D Converter disabled.
– Set the ADON bit to enable the A/D converter After wakeup from Halt mode, the A/D
and to start the conversion. From this time on, Converter requires a stabilization time
HALT
the ADC performs a continuous conversion of tSTAB (see Electrical Characteristics)
the selected channel. before accurate conversions can be
When a conversion is complete: performed.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit. 11.8.5 Interrupts
None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR) Bits 3:0 = CH[3:0] Channel Selection
Read/Write (Except bit 7 read only) These bits are set and cleared by software. They
select the analog input to convert.
Reset Value: 0000 0000 (00h)
Channel Pin* CH3 CH2 CH1 CH0
7 0 AIN0 0 0 0 0
AIN1 0 0 0 1
EOC SPEED ADON 0 CH3 CH2 CH1 CH0 AIN2 0 0 1 0
AIN3 0 0 1 1
Bit 7 = EOC End of Conversion AIN4 0 1 0 0
This bit is set by hardware. It is cleared by hard- AIN5 0 1 0 1
ware when software reads the ADCDRH register Reserved 0 1 1 0
or writes to any bit of the ADCCSR register. Reserved 0 1 1 1
0: Conversion is not complete AIN8 1 0 0 0
1: Conversion complete Reserved 1 0 0 1
AIN10 1 0 1 0
Bit 6 = SPEED ADC clock selection Reserved 1 0 1 1
This bit is set and cleared by software. AIN12 1 1 0 0
0: fADC = fCPU/4 AIN13 1 1 0 1
1: fADC = fCPU/2 AIN14 1 1 1 0
AIN15 1 1 1 1
Bit 5 = ADON A/D Converter on *The number of channels is device dependent. Refer to
This bit is set and cleared by software. the device pinout description.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Bit 4 = Reserved. Must be kept cleared. Read Only
Reset Value: 0000 0000 (00h)

7 0

D9 D8 D7 D6 D5 D4 D3 D2

Bits 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only
Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 D1 D0

Bits7:2 = Reserved. Forced by hardware to 0.

Bits 1:0 = D[1:0] LSB of Converted Analog Value

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10-BIT A/D CONVERTER (Cont’d)

Table 26. ADC Register Map and Reset Values

Address Register
7 6 5 4 3 2 1 0
(Hex.) Label

ADCCSR EOC SPEED ADON CH3 CH2 CH1 CH0

0070h
Reset Value 0 0 0 0 0 0 0 0
ADCDRH D9 D8 D7 D6 D5 D4 D3 D2
0071h
Reset Value 0 0 0 0 0 0 0 0
ADCDRL D1 D0
0072h
Reset Value 0 0 0 0 0 0 0 0

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12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
The ST7 Core features 17 different addressing so, most of the addressing modes may be subdi-
modes which can be classified in seven main vided in two submodes called long and short:
groups:
– Long addressing mode is more powerful be-
Addressing Mode Example cause it can use the full 64 Kbyte address space,
Inherent nop however it uses more bytes and more CPU cy-
cles.
Immediate ld A,#$55
– Short addressing mode is less powerful because
Direct ld A,$55 it can generally only access page zero (0000h -
Indexed ld A,($55,X) 00FFh range), but the instruction size is more
Indirect ld A,([$55],X) compact, and faster. All memory to memory in-
structions use short addressing modes only
Relative jrne loop (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
Bit operation bset byte,#5 INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 27. ST7 Addressing Mode Overview
Pointer Pointer
Destination/ Length
Mode Syntax Address Size
Source (Bytes)
(Hex.) (Hex.)
Inherent nop +0
Immediate ld A,#$55 +1
Short Direct ld A,$10 00..FF +1
Long Direct ld A,$1000 0000..FFFF +2
+ 0 (with X register)
No Offset Direct Indexed ld A,(X) 00..FF
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE +1
Long Direct Indexed ld A,($1000,X) 0000..FFFF +2
Short Indirect ld A,[$10] 00..FF 00..FF byte +2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2
1)
Relative Direct jrne loop PC-128/PC+127 +1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte +2
Bit Direct bset $10,#7 00..FF +1
Bit Indirect bset [$10],#7 00..FF 00..FF byte +2
Bit Direct Relative btjt $10,#7,skip 00..FF +2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

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ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent 12.1.3 Direct
All Inherent instructions consist of a single byte. In Direct instructions, the operands are referenced
The opcode fully specifies all the required informa- by their memory address.
tion for the CPU to process the operation. The direct addressing mode consists of two sub-
Inherent Instruction Function modes:
NOP No operation Direct (Short)
TRAP S/W Interrupt The address is a byte, thus requires only 1 byte af-
ter the opcode, but only allows 00 - FF addressing
Wait For Interrupt (Low Power space.
WFI
Mode)
Direct (Long)
Halt Oscillator (Lowest Power
HALT The address is a word, thus allowing 64 Kbyte ad-
Mode)
dressing space, but requires 2 bytes after the op-
RET Subroutine Return code.
IRET Interrupt Subroutine Return
12.1.4 Indexed (No Offset, Short, Long)
SIM Set Interrupt Mask
In this mode, the operand is referenced by its
RIM Reset Interrupt Mask memory address, which is defined by the unsigned
SCF Set Carry Flag addition of an index register (X or Y) with an offset.
RCF Reset Carry Flag The indirect addressing mode consists of three
submodes:
RSP Reset Stack Pointer
Indexed (No Offset)
LD Load
There is no offset (no extra byte after the opcode),
CLR Clear
and allows 00 - FF addressing space.
PUSH/POP Push/Pop to/from the stack
Indexed (Short)
INC/DEC Increment/Decrement
The offset is a byte, thus requires only 1 byte after
TNZ Test Negative or Zero the opcode and allows 00 - 1FE addressing space.
CPL, NEG 1 or 2 Complement Indexed (Long)
MUL Byte Multiplication The offset is a word, thus allowing 64 Kbyte ad-
SLL, SRL, SRA, RLC, dressing space and requires 2 bytes after the op-
Shift and Rotate Operations code.
RRC
SWAP Swap Nibbles 12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
12.1.2 Immediate by its memory address, located in memory (point-
Immediate instructions have 2 bytes, the first byte er).
contains the opcode, the second byte contains the The pointer address follows the opcode. The indi-
operand value. rect addressing mode consists of two submodes:
Immediate Instruction Function Indirect (Short)
LD Load The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
CP Compare
requires 1 byte after the opcode.
BCP Bit Compare
Indirect (Long)
AND, OR, XOR Logical Operations
The pointer address is a byte, the pointer size is a
ADC, ADD, SUB, SBC Arithmetic Operations word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

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ST7 ADDRESSING MODES (Cont’d)

12.1.6 Indirect Indexed (Short, Long) 12.1.7 Relative Mode (Direct, Indirect)
This is a combination of indirect and short indexed This addressing mode is used to modify the PC
addressing modes. The operand is referenced by register value by adding an 8-bit signed offset to it.
its memory address, which is defined by the un-
signed addition of an index register value (X or Y) Available Relative Direct/
Function
with a pointer value located in memory. The point- Indirect Instructions
er address follows the opcode. JRxx Conditional Jump
The indirect indexed addressing mode consists of CALLR Call Relative
two submodes:
Indirect Indexed (Short) The relative addressing mode consists of two sub-
modes:
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space, Relative (Direct)
and requires 1 byte after the opcode. The offset follows the opcode.
Indirect Indexed (Long) Relative (Indirect)
The pointer address is a byte, the pointer size is a The offset is defined in memory, of which the ad-
word, thus allowing 64 Kbyte addressing space, dress follows the opcode.
and requires 1 byte after the opcode.
Table 28. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD Load
CP Compare
AND, OR, XOR Logical Operations
Arithmetic Addition/subtrac-
ADC, ADD, SUB, SBC
tion operations
BCP Bit Compare

Short Instructions Only Function

CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
Bit Test and Jump Opera-
BTJT, BTJF
tions
SLL, SRL, SRA, RLC,
Shift and Rotate Operations
RRC
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine

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12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set be subdivided into 13 main groups as illustrated in
consisting of 63 instructions. The instructions may the following table:
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF

Using a prebyte PDY 90 Replace an X based instruction using

The instructions are described with 1 to 4 bytes. immediate, direct, indexed, or inherent
addressing mode by a Y one.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ- PIX 92 Replace an instruction using direct, di-
ent prebyte opcodes are defined. These prebytes rect bit or direct relative addressing
modify the meaning of the instruction they pre- mode to an instruction using the corre-
cede. sponding indirect addressing mode.
It also changes an instruction using X
The whole instruction becomes: indexed addressing mode to an instruc-
PC-2 End of previous instruction tion using indirect X indexed addressing
PC-1 Prebyte mode.
PC Opcode PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the 12.2.1 Illegal Opcode Reset
effective address In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
These prebytes enable instruction in Y as well as be executed does not correspond to any opcode
indirect addressing modes to be implemented. or prebyte value, a reset is generated. This, com-
They precede the opcode of the instruction in X or bined with the Watchdog, allows the detection and
the instruction using direct addressing mode. The recovery from an unexpected fault or interference.
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C
ADC Add with Carry A=A+M+C A M H N Z C
ADD Addition A=A+M A M H N Z C
AND Logical And A=A.M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 0
IRET Interrupt routine return Pop CC, A, X, PC H I N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. interrupt = 1
JRIL Jump if ext. interrupt = 0
JRH Jump if H = 1 H=1?
JRNH Jump if H = 0 H=0?
JRM Jump if I = 1 I=1?
JRNM Jump if I = 0 I=0?
JRMI Jump if N = 1 (minus) N=1?
JRPL Jump if N = 0 (plus) N=0?
JREQ Jump if Z = 1 (equal) Z=1?
JRNE Jump if Z = 0 (not equal) Z=0?
JRC Jump if C = 1 C=1?
JRNC Jump if C = 0 C=0?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2's compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A=A+M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C=0 0

RET Subroutine Return

RIM Enable Interrupts I=0 0

RLC Rotate left true C C <= Dst <= C reg, M N Z C

RRC Rotate right true C C => Dst => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Subtract with Carry A=A-M-C A M N Z C

SCF Set carry flag C=1 1

SIM Disable Interrupts I=1 1

SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C

SLL Shift left Logic C <= Dst <= 0 reg, M N Z C

SRL Shift right Logic 0 => Dst => C reg, M 0 Z C

SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C

SUB Subtraction A=A-M A M N Z C

SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z

TNZ Test for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1

WFI Wait for Interrupt 0

XOR Exclusive OR A = A XOR M A M N Z

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13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re- 13.1.5 Pin input voltage
ferred to VSS. The input voltage measurement on a pin of the de-
13.1.1 Minimum and Maximum values vice is described in Figure 83.
Unless otherwise specified the minimum and max- Figure 83. Pin input voltage
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C ST7 PIN
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design VIN
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
13.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range) and VDD=3.3V (for the
3V≤VDD≤3.6V voltage range). They are given only
as design guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 82.
Figure 82. Pin loading conditions

ST7 PIN

CL

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13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- tions is not implied. Exposure to maximum rating
mum ratings” may cause permanent damage to conditions for extended periods may affect device
the device. This is a stress rating only and func- reliability.
tional operation of the device under these condi-
13.2.1 Voltage Characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 7.0
V
VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3
VESD(HBM) Electrostatic discharge voltage (Human Body Model) see Section 13.9.3 on page 165

13.2.2 Current Characteristics

Symbol Ratings Maximum value Unit
IVDD 3)
Total current into VDD power lines (source) 75
IVSS Total current out of VSS ground lines (sink) 3) 150
Output current sunk by any standard I/O and control pin 20
IIO Output current sunk by any high sink I/O pin 40
Output current source by any I/Os and control pin - 25
Injected current on ISPSEL pin ±5 mA
Injected current on RESET pin ±5
IINJ(PIN) 2) & 4) Injected current on OSC1 and OSC2 pins ±5
Injected current on PB0 pin 5) +5
6)
Injected current on any other pin ±5
ΣIINJ(PIN) 2)
Total injected current (sum of all I/O and control pins) 6) ± 20

13.2.3 Thermal Characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJ Maximum junction temperature (see Table on page 180)

Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. No negative current injection allowed on PB0 pin.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-
mum current injection on four I/O port pins of the device.

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13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions
TA = -40 to +85°C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
fCPU = 8 MHz. max. 3.3 5.5
VDD Supply voltage V
fCPU = 4 MHz. max. 2.7 5.5
3.3V≤ VDD≤5.5V Up to 16
fOSC External clock frequency MHz
2.7V≤VDD<3.3V Up to 8

Note:
When the power supply is between 2.7 and 2.95V (VIT+(LVD) max), the device is either in the guaranteed
functional area or in reset state, thus allowing deterministic application behaviour. However the LVD may
generate a reset below 2.95V and the user should therefore not use the device below this level when the
LVD is enabled.
Figure 84. fCPU Maximum Operating Frequency Versus VDD Supply Voltage

fCPU [MHz]

8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA

4 FUNCTIONALITY
GUARANTEED
CAUTION: RESET MAY 2 IN THIS AREA
BE ACTIVATED BY LVD
IN THIS AREA
0 SUPPLY VOLTAGE [V]
2.7 3.3 3.6 4.0 4.5 5.0 5.5

13.3.2 Low Voltage Detector (LVD) Thresholds

TA = -40 to +85°C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
High Threshold 3.85 4.20 4.61
Reset release threshold
VIT+(LVD) Med. Threshold 3.24 3.56 3.90
(VDD rise)
Low Threshold 2.60 2.88 3.14
V
High Threshold 3.66 3.98 4.36
Reset generation threshold
VIT-(LVD) Med. Threshold 3.04 3.36 3.66
(VDD fall)
Low Threshold 2.45 2.71 2.95
Vhys(LVD) LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV
VtPOR VDD rise time rate 20 1) 100 1) ms/V
tg(VDD) VDD glitches filtered by LVD 150 ns
Note:
1. Not tested in production, guaranteed by design

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13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to +85°C unless otherwise specified
Symbol Parameter Conditions Min 1) Typ Max 1) Unit
High Threshold 4.15 4.50 4.91
1=>0 AVDF flag toggle threshold
VIT+(AVD) Med. Threshold 3.64 3.96 4.30
(VDD rise)
Low Threshold 3.00 3.28 3.54
V
High Threshold 3.96 4.28 4.66
0=>1 AVDF flag toggle threshold
VIT-(AVD) Med. Threshold 3.44 3.76 4.06
(VDD fall)
Low Threshold 2.85 3.11 3.35
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200 mV
Voltage drop between ADV flag set
∆VIT- VIT-(AVD)-VIT-(LVD) 450 mV
and LVD reset activated
Note:
1. Not tested in production, guaranteed by characterization.

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13.4 PLL CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit
VDD = 2.7 to 3.65V
0.95 1 1.05
2) PLL option x4 selected
fPLLIN PLL Input frequency MHz
VDD = 3.3 to 5.5V
0.90 1 1.10
PLL option x8 selected
PLL option x4 selected 1) 2.7 3.65
VDD(PLL) PLL operating range V
PLL option x8 selected 3.3 5.5
tw(JIT) PLL jitter period fRC = 1MHz 8 kHz
VDD = 3.0V 3.0
JITPLL PLL jitter (∆fCPU/fCPU) %
VDD = 5.0V 1.6
IDD(PLL) PLL current consumption TA=25°C 600 µA

Note:
1. To obtain a x4 multiplication ratio in the range 3.3 to 5.5V, the DIV2EN option bit must enabled.
2. Guaranteed by design.

13.4.1 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol Parameter Conditions Min Typ Max Unit
VDD(RC) Internal RC Oscillator operating voltage Refer to operating range 2.7 5.5
of VDD with TA, Section
VDD(x4PLL) x4 PLL operating voltage 13.3.1 on page 154 2.7 5.5 V
VDD(x8PLL) x8 PLL operating voltage 3.3 5.5
PLL
input
tSTARTUP PLL Startup time 60 clock
(fPLL)
cycles

13.5 INTERNAL RC OSCILLATOR CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C,VDD=5V 625
fRC kHz
quency 1) RCCR = RCCR02 ),TA=25°C,VDD=5V 1000
TA=25°C,VDD=5V -1 +1 %
Accuracy of Internal RC TA=25°C, VDD=4.5 to 5.5V3) -1 +1 %
ACCRC oscillator with TA=25 to +85°C,VDD=5V3) -3 +3 %
RCCR=RCCR02) TA=25 to +85°C,VDD=4.5 to 5.5V3) -3.5 +3.5 %
TA=-40 to +25°C,VDD=4.5 to 5.5V 3)
-3 +7 %
RC oscillator current con-
IDD(RC) TA=25°C,VDD=5V 6003) µA
sumption
tsu(RC) RC oscillator setup time TA=25°C,VDD=5V 102) µs

Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
2. See “Internal RC Oscillator” on page 30
3. Expected results. Data based on characterization, not tested in production

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Figure 85. Typical RC Frequency vs RCCR

Typical Rc freq (MHz) = f(RCCR) @ 25°C
1.7
1.6
Rc @ 5V
1.5
1.4 Rc @ 3V
1.3
F Cpu MHz

1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0 50 100 150 200 250
RCCR (decimal)

13.6 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for vice consumption, the two current values must be
the ST7 functional operating modes over tempera- added (except for HALT mode for which the clock
ture range does not take into account the clock is stopped).
source current consumption. To get the total de-
13.6.1 Supply Current
TA = -40 to +85°C unless otherwise specified
Symbol Parameter Conditions Typ Max Unit
Supply current in RUN mode fCPU=8MHz 1) 8.5 13
Supply current in WAIT mode fCPU=8MHz 2) 3.7 6
mA
fCPU=250kHz 3)
VDD=5.5V

Supply current in SLOW mode 4.1 7

IDD Supply current in SLOW WAIT mode fCPU=250kHz 4) 2.2 3.5
Supply current in HALT mode5) -40°C≤TA≤+85°C 1 10
Supply current in AWUFH mode 6)7) TA= +25°C 50 60 µA
Supply current in Active Halt mode 6)7) TA= +25°C 500 700
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1)
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
5. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.

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SUPPLY CURRENT CHARACTERISTICS

Figure 86. Typical IDD in RUN vs. fCPU Figure 89. Typical IDD in WAIT vs. fCPU
9
4
.5
8
1
3.5 0.5
7 2
1
4 3
2
IDD run (mA) vs Freq (MHz)

IDD wfi (mA) vs Fcpu (MHz)

6
4
8 2.5
6
5
8
2
4

1.5
3

1
2

0.5
1

0 0
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Vdd (V)
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Note: Graph displays data beyond the normal operating range of 3V - 5.5V

Figure 87. Typical IDD in RUN at fCPU = 8MHz Figure 90. Typical IDD in WAIT at fCPU= 8MHz
4

9
3.5 0.5
8 1
3
2
7 IDD wfi (mA) vs Fcpu (MHz)
4
IDD run (mA) at fCPU=8MHz

2.5
6 6
140°C 8
2
5
90°C
1.5
4
25°C
1
3
-5°C
0.5
2
-45°C
1 0
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Vdd (V)
0 Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Note:
2 Graph
2.5displays
3 data 3.5
beyond the
4 normal
4.5 operating
5 range
5.5 of 3V
6 - 5.5V6.5
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 91. Typical IDD in SLOW-WAIT vs. fCPU
Figure 88. Typical IDD in SLOW vs. fCPU 0.60
250KHz
0.90 0.50 125KHz
0.80 250KHz
0.40 62KHz
D
IDD (mA)

0.70 125KHz
0.60 0.30
IDD (mA)

TB

0.50 62KHz
0.20
D

0.40
0.30 0.10
TB

0.20
0.10 0.00
0.00 2.7 3.3 4 5 6
2.7 3.3 4 5 6 VDD (V)
VDD (V) Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Note: Graph displays data beyond the normal operating range of 3V - 5.5V

Figure 92. Typical IDD vs. Temp. at VDD = 5V and

fCPU = 8MHz
6.00

5.00
RUN
4.00 WAIT
Idd (mA)

SLOW
3.00
SLOW-WAIT
D

2.00

1.00
TB

0.00
-45 25 90 110
Temperature (°C)

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13.6.2 On-chip peripherals

Symbol Parameter Conditions Typ Unit
fCPU=4MHz VDD=3.0V 20
IDD(16-b timer) 16-bit Timer supply current 1)
fCPU=8MHz VDD=5.0V 100
fCPU=4MHz VDD=3.0V 250
IDD(SPI) SPI supply current 2)
fCPU=8MHz VDD=5.0V 800
fADC=2MHz VDD=3.0V 300
IDD(ADC) ADC supply current when converting 3) µA
fADC=4MHz VDD=5.0V 1000
fCPU=4MHz VDD=3.0V 100
IDD(I2C) I2C supply current 4)
fCPU=8MHz VDD=5.0V 500
fCPU=4MHz VDD=3.0V 250
IDD(SCI) SCI supply current 5)
fCPU=8MHz VDD=5.0V 800

Notes:
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM
mode at fcpu=8MHz.
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-
tion (data sent equal to 55h).
3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
4. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent I2C master
communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm
external pull-up on clock and data lines).
5. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
mit sequence.

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13.7 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.
13.7.1 General Timings
Symbol Parameter 1) Conditions Min Typ 2) Max Unit
2 3 12 tCPU
tc(INST) Instruction cycle time fCPU=8MHz
250 375 1500 ns
3) 10 22 tCPU
Interrupt reaction time
tv(IT) fCPU=8MHz
tv(IT) = ∆tc(INST) + 10 1.25 2.75 µs

13.7.2 External Clock Source

Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage 0.7xVDD VDD
V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
OSC1 high or low time 4) see Figure 93 15
tw(OSC1L)
ns
tr(OSC1)
OSC1 rise or fall time 4) 15
tf(OSC1)
IL OSCx Input leakage current VSS≤VIN≤VDD ±1 µA

Figure 93. Typical Application with an External Clock Source

90%
VOSC1H
10%

VOSC1L

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

OSC2
Not connected internally

fOSC
EXTERNAL
IL
CLOCK SOURCE
OSC1
ST72XXX

Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
4. Data based on design simulation and/or technology characteristics, not tested in production.
13.7.3 Auto Wakeup from Halt Oscillator (AWU)
Symbol Parameter Conditions Min Typ Max Unit
fAWU AWU Oscillator Frequency 50 125 250 kHz
tRCSRT AWU Oscillator startup time 50 µs

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

13.7.4 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four close as possible to the oscillator pins in order to
different Crystal/Ceramic resonator oscillators. All minimize output distortion and start-up stabiliza-
the information given in this paragraph is based on tion time. Refer to the crystal/ceramic resonator
characterization results with specified typical ex- manufacturer for more details (frequency, pack-
ternal components. In the application, the resona- age, accuracy...).
tor and the load capacitors have to be placed as
Symbol Parameter Conditions Min Max Unit
fOSC Oscillator Frequency 1) 1 16 MHz
RF Feedback resistor2) 20 40 kΩ
fOSC= 1 to 2 MHz 20 60
CL1 Recommended load capacitance ver-
fOSC= 2 to 4 MHz 20 50
sus equivalent serial resistance of the pF
CL2 fOSC= 4 to 8 MHz 15 35
crystal or ceramic resonator (RS)3)
fOSC= 8 to 16 MHz 15 35

Symbol Parameter Conditions Typ Max Unit

VDD=5V:
fOSC= 2MHz, C0 = 6pF, Cl1 = Cl2 = 68pF 426
i2 OSC2 driving current fOSC= 4MHz, C0 = 6pF, Cl1 = Cl2 = 68pF 425 µA
fOSC= 8MHz, C0 = 6pF, Cl1 = Cl2 = 40pF 456
fOSC= 16MHz, C0 = 7pF, Cl1 = Cl2 = 20pF 660

Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production. The relatively low value of the RF resistor, offers a
good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias con-
dition change. However, it is recommended to take this point into account if the µC is used in tough humidity conditions.
3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed
for high-frequency applications and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usu-
ally the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1
and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough esti-
mate of the combined pin and board capacitance).

Figure 94. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS fOSC
POWER DOWN
CL1 OSC1
LOGIC
LINEAR FEEDBACK
AMPLIFIER LOOP

RESONATOR VDD/2 i2
Ref
RF
CL2
OSC2
ST72XXX

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

fOSC
Supplier Typical Ceramic Resonators2)
(MHz)
2 CSTCC2M00G56Z-R0
SMD CSTCR4M00G53Z-R0
4
Lead CSTLS4M00G53Z-R0
Murata

SMD CSTCE8M00G52Z-R0
8
Lead CSTLS4M0052Z-R0
SMD CSTCE16M0V51Z-R0
16
Lead CSTLS16M0X51Z-R0

Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
For more information on these resonators, please consult www.murata.com

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13.8 MEMORY CHARACTERISTICS

TA = -40°C to 85°C, unless otherwise specified
13.8.1 RAM and Hardware Registers
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) HALT mode (or RESET) 1.6 V

13.8.2 FLASH Program Memory

Symbol Parameter Conditions Min Typ Max Unit
Refer to operating range of
VDD Operating voltage for Flash write/erase VDD with TA, Section 13.3.1 2.7 5.5 V
on page 154
tprog Programming time for 1~32 bytes 2) TA=−40 to +85°C 5 10 ms
tRET Data retention 4)
TA=+55°C3) 20 years
NRW Write erase cycles TA=+25°C 10K 7) cycles
Read / Write / Erase modes
2.6 mA
fCPU = 8MHz, VDD = 5.5V
IDD Supply current 6)
No Read/No Write Mode 100 µA
Power down mode / HALT 0 0.1 µA

13.8.3 EEPROM Data Memory

Symbol Parameter Conditions Min Typ Max Unit
Operating voltage for EEPROM Refer to operating range of VDD with
VDD 2.7 5.5 V
write/erase TA, Section 13.3.1 on page 154
Programming time for 1~32
tprog TA=−40 to +85°C 5 10 ms
bytes
tret Data retention 4) TA=+55°C 3) 20 years
NRW Write erase cycles TA=+25°C 300K 7) cycles

Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the TA decreases.
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.

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13.9 EMC CHARACTERISTICS tion environment and simplified MCU software. It

should be noted that good EMC performance is
Susceptibility tests are performed on a sample ba- highly dependent on the user application and the
sis during product characterization. software in particular.
13.9.1 Functional EMS (Electro Magnetic Therefore it is recommended that the user applies
Susceptibility) EMC software optimization and prequalification
Based on a simple running application on the tests in relation with the EMC level requested for
product (toggling 2 LEDs through I/O ports), the his application.
product is stressed by two electro magnetic events Software recommendations:
until a failure occurs (indicated by the LEDs).
The software flowchart must include the manage-
■ ESD: Electro-Static Discharge (positive and
ment of runaway conditions such as:
negative) is applied on all pins of the device until
a functional disturbance occurs. This test – Corrupted program counter
conforms with the IEC 1000-4-2 standard. – Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive – Critical Data corruption (control registers...)
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance Prequalification trials:
occurs. This test conforms with the IEC 1000-4- Most of the common failures (unexpected reset
4 standard. and program counter corruption) can be repro-
A device reset allows normal operations to be re- duced by manually forcing a low state on the RE-
sumed. The test results are given in the table be- SET pin or the Oscillator pins for 1 second.
low based on the EMS levels and classes defined To complete these trials, ESD stress can be ap-
in application note AN1709. plied directly on the device, over the range of
13.9.1.1 Designing hardened software to avoid specification values. When unexpected behaviour
noise problems is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
EMC characterization and optimization are per- tion note AN1015).
formed at component level with a typical applica-
Level/
Symbol Parameter Conditions
Class
Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25°C, fOSC=8MHz
VFESD TBD
functional disturbance conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V =5V, TA=+25°C, fOSC=8MHz
VFFTB through 100pF on VDD and VDD pins to induce a func- DD TBD
conforms to IEC 1000-4-4
tional disturbance

13.9.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Monitored Max vs. [fOSC/fCPU] Unit
Symbol Parameter Conditions
Frequency Band 8/4MHz 16/8MHz
0.1MHz to 30MHz TBD TBD
VDD=5V, TA=+25°C, 30MHz to 130MHz TBD TBD dBµV
SEMI Peak level SO20 package,
conforming to SAE J 1752/3 130MHz to 1GHz TBD TBD
SAE EMI Level TBD TBD -
Note:
1. Data based on characterization results, not tested in production.

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EMC CHARACTERISTICS (Cont’d)

13.9.3 Absolute Maximum Ratings (Electrical 13.9.3.1 Electro-Static Discharge (ESD)
Sensitivity) Electro-Static Discharges (a positive then a nega-
Based on two different tests (ESD and LU) using tive pulse separated by 1 second) are applied to
specific measurement methods, the product is the pins of each sample according to each pin
stressed in order to determine its performance in combination. The sample size depends on the
terms of electrical sensitivity. For more details, re- number of supply pins in the device (3 parts*(n+1)
fer to the application note AN1181. supply pin). Human Body Model can be simulated.
This test conforms to the JESD22-A114A/A115A
standard.
Absolute Maximum Ratings
Symbol Ratings Conditions Maximum value 1) Unit
Electro-static discharge voltage
VESD(HBM) TA=+25°C >2000 V
(Human Body Model)

Note:
1. Data based on characterization results, not tested in production.

13.9.3.2 Static and Dynamic Latch-Up ■ DLU: Electro-Static Discharges (one positive
■ LU: 3 complementary static tests are required then one negative test) are applied to each pin
on 6 parts to assess the latch-up performance. of 3 samples when the micro is running to
A supply overvoltage (applied to each power assess the latch-up performance in dynamic
supply pin) and a current injection (applied to mode. Power supplies are set to the typical
each input, output and configurable I/O pin) are values, the oscillator is connected as near as
performed on each sample. This test conforms possible to the pins of the micro and the
to the EIA/JESD 78 IC latch-up standard. For component is put in reset mode. This test
more details, refer to the application note conforms to the IEC1000-4-2 and SAEJ1752/3
AN1181. standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
Symbol Parameter Conditions Class
TA=+25°C A
LU Static latch-up class
TA=+85°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

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13.10 I/O PORT PIN CHARACTERISTICS

13.10.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage 1) VSS - 0.3 0.3xVDD
V
VIH Input high level voltage 1) 0.7xVDD VDD + 0.3
Schmitt trigger voltage
Vhys 400 mV
hysteresis 1)
IL Input leakage current VSS≤VIN≤VDD ±1
Static current consumption in- µA
IS duced by each floating input Floating input mode 400
pin2)
Weak pull-up equivalent VDD=5V 50 120 250
RPU VIN=VSS kΩ
resistor3) VDD=3V 160
CIO I/O pin capacitance 5 pF
Output high to low level fall
tf(IO)out 25
time 1) CL=50pF
ns
Output low to high level rise Between 10% and 90%
tr(IO)out 25
time 1)
tw(IT)in External interrupt pulse time 4) 1 tCPU

Notes:
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 95). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and tem-
perature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

Figure 95. Two typical Applications with unused I/O Pin

VDD ST7XXX
UNUSED I/O PORT
10kΩ 10kΩ
UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled-up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

13.10.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Output low level voltage for a standard I/O pin IIO=+5mA 1.0
when 8 pins are sunk at same time
(see Figure 98) IIO=+2mA 0.4
VOL 1)

VDD=5V
Output low level voltage for a high sink I/O pin IIO=+20mA 1.3
when 4 pins are sunk at same time
(see Figure 101) IIO=+8mA 0.75
Output high level voltage for an I/O pin IIO=-5mA VDD-1.5
VOH 2) when 4 pins are sourced at same time
(see Figure ) IIO=-2mA VDD-0.8
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time IIO=+2mA 0.7
VOL 1)3) (see Figure 97)
Output low level voltage for a high sink I/O pin V
IIO=+8mA 0.5
when 4 pins are sunk at same time
VDD=3.3V

Output high level voltage for an I/O pin

VOH 2)3) when 4 pins are sourced at same time (Figure IIO=-2mA VDD-0.8
108)
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time IIO=+2mA 0.9
VOL 1)3) (see Figure 99)
Output low level voltage for a high sink I/O pin
IIO=+8mA 0.6
when 4 pins are sunk at same time
VDD=2.7V

Output high level voltage for an I/O pin

VOH 2)3) when 4 pins are sourced at same time IIO=-2mA VDD-0.9
(see ...)

Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD.
3. Not tested in production, based on characterization results.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 96. Typical VOL at VDD=2.4V (std I/Os) Figure 99. Typical VOL at VDD=2.4V (high-sink I/
Os)
1000
VOL (mV) at VDD=2.4 V(STD)

800 1000

VOL (mV) at VDD=2.4 V(HS)

800
600
-45°C
25°C 600
400 -45°C
90°C
400 25°C
130°C
200
90°C
200
130°C
0
0 2 4 6 0
ILOAD (mA)
0 2 4 6 8 10 12 14 16 18 20
ILOAD (mA)
Figure 97. Typical VOL at VDD=3V (std I/Os)
Figure 100. Typical VOL at VDD=3V (high-sink
I/Os)
1000
VOL (mV) at VDD=2.4 V(STD)

800 1200
VOL (mV) at VDD=3 V(HS)

-45°C
600 1000
-45°C 25°C
25°C 800 90°C
400 90°C 130°C
130°C 600
200
400

0 200
0 2 4 6
ILOAD (mA) 0
0 2 4 6 8 10 12 14 16 18 20
Figure 98. Typical VOL at VDD=5V (std I/Os) ILOAD (mA)

Figure 101. Typical VOL at VDD=5V (high-sink

1000 I/Os)
VOL (mV) at VDD= 5 V(STD)

-45°C
800 25°C 700
90°C
600 -45°C
VOL (mV) at VDD=5 V(HS)

600 130°C
25°C
500
90°C
400
400 130°C

200 300

200
0
0 2 4 6 100
ILOAD (mA)
0
0 2 4 6 8 10 12 14 16 18 20
ILOAD (mA)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 102. Typical VOL vs. VDD (std I/Os, 2mA) Figure 105. Typical VOL vs. VDD (HS I/Os,
Iio=2mA)

1000 200
-45°C
VOL (mV) at Ilo=2mA (Std)

-45°C
25°C

VDD -Voh (mV) at Ilo=2mA

800 25°C 160
90°C
90°C
130°C
600 130°C 120

400
80

200
40

0
2.4 2.6 2.8 3 5 0
Ilo (mA) 2.5 3 3.5 4 5
Ilo (mA)
Figure 103. Typical VOL vs. VDD (std I/Os, 6mA)
Figure 106. Typical VOL vs. VDD (HS I/Os,
Iio=12mA)
500

000
-45°C
VDD -Voh (mV) at Ilo=6mA

400
25°C
800 90°C
300 130°C
600
200 -45°C
25°C 400
100 90°C
130°C
200
0
2.5 3 Ilo3.5
(mA) 4 5
0
2.4 2.6 2.8 3 5
Figure 104. Typical VOL vs. VDD (HS I/Os, Ilo (mA)
Iio=8mA)
Figure 107. Typical VDD-vOH at vDD=2.4V (std
1000 I/Os)
-45°C
25°C 1400
VOL(mV) at Ilo=8mA (HS)

800
90°C
VDD-VOH (mV) at VDD=2.4 V

1200
130°C
600
1000

400 800
-45°C
600 25°C
200 90°C
400
130°C
0 200
2.4 2.6 2.8 3 5
Ilo (mA) 0
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)

Figure 108. Typical VDD-VOH at VDD=3V (std

I/Os)

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1800
VDD-VOH (mV) at VDD=3 V

1500 -45°C
25°C
1200 90°C
130°C
900

600

300

0
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 109. Typical VDD-VOH at VDD=4V (std) Figure 110. Typical VDD-VOH at VDD=5V (std)

1200 1000
1100 900
-45°C

VDD-VOH (mV) at VDD=5 V

VDD-VOH (mV) at VDD=4 V

1000 800
-45°C 25°C
900 700
25°C 90°C
800
90°C 600 130°C
700
600 130°C 500
500 400
400 300
300 200
200
100
100
0
0
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 ILOAD (mA)
ILOAD (mA)

Figure 111. Typical VDD-VOH vs. VDD (High Sink)

200 500
-45°C
25°C
VDD -Voh (mV) at Ilo=2mA

VDD -Voh (mV) at Ilo=6mA

160 90°C 400

130°C
120 300

80 -45°C
200
25°C
90°C
40 100
130°C

0 0
2.5 3 3.5 4 5 2.5 3
Ilo (mA) Ilo3.5
(mA) 4 5

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13.11 CONTROL PIN CHARACTERISTICS

13.11.1 Asynchronous RESET Pin
TA = -40°C to 85°C, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage Vss - 0.3 0.3xVDD
V
VIH Input high level voltage 0.7xVDD VDD + 0.3
Vhys Schmitt trigger voltage hysteresis 1) 2 V
IIO=+5mA 0.5 1.0
VOL Output low level voltage 2) VDD=5V V
IIO=+2mA 0.2 0.4
VDD=5V 20 40 80
RON Pull-up equivalent resistor 3) 1) kΩ
VDD=3V 40 70 120
tw(RSTL)out Generated reset pulse duration Internal reset sources 26 µs
th(RSTL)in External reset pulse hold time 4)
20 µs
tg(RSTL)in Filtered glitch duration 200 ns

Notes:
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 112. RESET pin protection when LVD is enabled.1)2)3)4)
VDD ST72XXX

Required Optional RON

(note 3) INTERNAL
EXTERNAL RESET
RESET Filter

0.01µF 1MΩ WATCHDOG

PULSE
GENERATOR ILLEGAL OPCODE 5)
LVD RESET

Figure 113. RESET pin protection when LVD is disabled.1)

VDD ST72XXX

RON
USER INTERNAL
EXTERNAL RESET
RESET Filter
CIRCUIT
0.01µF WATCHDOG
PULSE
GENERATOR
ILLEGAL OPCODE 5)
Required

Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the VIL max. level specified in Section 13.11.1 on page 172. Otherwise the reset will not be taken into account
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
Section 13.2.2 on page 153.
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to the reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: Please refer to “Illegal Opcode Reset” on page 149 for more details on illegal opcode reset conditions.

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13.12 COMMUNICATION INTERFACE CHARACTERISTICS

13.12.1 I2C and I²C3SNS Interfaces Refer to I/O port characteristics for more details on
Subject to general operating conditions for VDD, the input/output alternate function characteristics
fOSC, and TA unless otherwise specified. (SDAI and SCLI). The ST7 I2C and I2C3SNS inter-
faces meet the electrical and timing requirements
of the Standard I2C communication protocol.
TA = -40°C to 85°C, unless otherwise specified
Symbol Parameter Conditions Min Max Unit
fSCL I²C SCL frequency 1) 400 kHz
fCPU=4 MHz to 8 MHz ,
fSCL3SNS I²C3SNS SCL frequency VDD= 2.7V to 5.5V 400 kHz
Note:
1. The I2C and I2C3SNS interfaces will not function below the minimum clock speed of 4 MHz.

The following table gives the values to be written in

the I2CCCR register to obtain the required I2C
SCL line frequency.
Table 29. SCL Frequency Table (Multimaster I2C Interface)
I2CCCR Value
fCPU=4 MHz. fCPU=8 MHz.
fSCL
VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V
RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ
400 NA NA NA NA 84h 84h 84h 84h
300 NA NA NA NA 86h 86h 85h 87h
200 84h 84h 84h 84h 8Ah 8Ah 8Bh 8Ch
100 11h 10h 11h 11h 25h 24h 28h 28h
50 25h 24h 25h 26h 4Bh 4Ch 53h 54h
20 60h 5Fh 60h 62h FFh FFh FFh FFh

Legend:
RP = External pull-up resistance
fSCL = I2C speed
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.

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13.13 10-BIT ADC CHARACTERISTICS

TA = -40°C to 85°C, unless otherwise specified
ADC Accuracy
Symbol Parameter Conditions 1)2) Typ Max 3) Unit
|ET| Total unadjusted error 4 8
fCPU=8 MHz,
|EO| Offset error fADC=4 MHz -1 -2
LSB
|EG| Gain Error RAIN< 10kΩ, -2 -4
VDD= 2.7V to 5.5V
|ED| Differential linearity error 3 6

Note:
1. Data based on characterization results over the whole temperature range.
2. ADC accuracy vs negative injection current: Injecting negative current on any of the analog input pins may reduce the
accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in Section 13.11 on page 172
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.10 does not affect the ADC
accuracy.
3. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C
to +125°C (± 3σ distribution limits).

Figure 114. ADC Accuracy Characteristics

Digital Result ADCDR EG

(1) Example of an actual transfer curve
1023
(2) The ideal transfer curve
1022 V –V (3) End point correlation line
DD SS
1LSB = --------------------------------
1021 IDEAL 1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
Vin (LSBIDEAL)
0
1 2 3 4 5 6 7 1021 1022 1023 1024
VSS VDD

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ADC Characteristics
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Conditions Min Typ 1) Max Unit
fADC ADC clock frequency 0.4 4 MHz
VAIN Conversion voltage range 2) VSSA VDDA V
3)
RAIN External input resistor 10 kΩ
CADC Internal sample and hold capacitor 6 pF
4)
tSTAB Stabilization time after ADC enable 0
µs
Conversion time (Sample+Hold) 3.5
fCPU=8MHz, fADC=4MHz
tADC - Sample capacitor loading time 4
1/fADC
- Hold conversion time 10
Analog Part 1
IADC mA
Digital Part 0.2

Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.

Figure 115. Typical A/D Converter Application

VDD
ST72XXX
VT
RAIN 0.6V
AINx 2kΩ(max) 10-Bit A/D
VAIN Conversion

CAIN VT
0.6V IL CADC
±1µA 6pF

Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).

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14 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST JESD97. The maximum ratings related to solder-
offers these devices in ECOPACK® packages. ing conditions are also marked on the inner box la-
These packages have a Lead-free second level in- bel.
terconnect. The category of second Level Inter- ECOPACK is an ST trademark. ECOPACK speci-
connect is marked on the package and on the in- fications are available at: www.st.com.
ner box label, in compliance with JEDEC Standard

14.1 PACKAGE MECHANICAL DATA

Figure 116. 32-Pin Low Profile Quad Flat Package (7x7)

mm inches1)
Dim.
D A Min Typ Max Min Typ Max
D1 A2 A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A1 A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.30 0.37 0.45 0.012 0.015 0.018
e C 0.09 0.20 0.004 0.008
D 9.00 0.354
E1 E
b D1 7.00 0.276
E 9.00 0.354
E1 7.00 0.276
c e 0.80 0.031
L1
θ 0° 3.5° 7° 0° 3.5° 7°
L
h L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of Pins
N 32
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.

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PACKAGE CHARACTERISTICS (Cont’d)

Figure 117. 40-Lead Very thin Fine pitch Quad Flat No-Lead Package

A2
A

SEATING
A3 mm inches1)
PLANE A1 Dim.
Min Typ Max Min Typ Max
D
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0.02 0.05 0.001 0.002
A2 0.65 1.00 0.026 0.039
A3 0.20 0.008
b 0.18 0.25 0.30 0.007 0.010 0.012
D 5.85 6.00 6.15 0.230 0.236 0.242
D2
D2 2.75 2.9 3.05 0.108 0.114 0.120
E 5.85 6 6.15 0.230 0.236 0.242
E2 E E2 2.75 2.9 3.05 0.108 0.114 0.120
e 0.50 0.020
PIN #1 ID TYPE C
RADIUS L 0.30 0.40 0.50 0.012 0.016 0.020
2 Number of Pins
1 N 40
L Note 1. Values in inches are converted from mm
and rounded to 3 decimal digits.
b e

Figure 118. 44-Pin Low Profile Quad Flat Package

mm inches1)
Dim.
D A Min Typ Max Min Typ Max
D1 A2 A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.30 0.37 0.45 0.012 0.015 0.018
b
C 0.09 0.20 0.004 0.000 0.008
D 12.00 0.472
e D1 10.00 0.394
E1 E
E 12.00 0.472
E1 10.00 0.394
e 0.80 0.031
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 c
L1 1.00 0.039
L
h Number of Pins
N 44
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.

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PACKAGE CHARACTERISTICS (Cont’d)

Figure 119. 48-Pin Low profile Quad Flat Package

mm inches1)
Dim.
Min Typ Max Min Typ Max
D A A 1.60 0.063
D1 A2 A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b 0.17 0.22 0.27 0.007 0.009 0.011
b C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
E1 E e
E 9.00 0.354
E1 7.00 0.276
e 0.50 0.020
c θ 0° 3.5° 7° 0° 3.5° 7°
L1
L 0.45 0.60 0.75 0.018 0.024 0.030
L
θ L1 1.00 0.039
Number of Pins
N 48
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.

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PACKAGE CHARACTERISTICS (Cont’d)

Table 30. THERMAL CHARACTERISTICS

Symbol Ratings Value 3) Unit

LQFP32 60
RthJA Package thermal resistance (junction to ambient) LQFP44 54 °C/W
LQFP48 73
TJmax Maximum junction temperature 1) 150 °C
LQFP32 415
PDmax Power dissipation 2) LQFP44 460 mW
LQFP48 340

Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the
chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the application.
3. Values given for a 4-layer board. PDmax computed for TA = 125°C.

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15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- ST72F34x FLASH devices are shipped to custom-
grammable versions (FLASH) as well as in factory ers with a default content (FFh). This implies that
coded versions (FASTROM). FLASH devices have to be configured by the cus-
ST7P234x devices are Factory Advanced Service tomer using the Option Bytes.
Technique ROM (FASTROM) versions: they are
factory-programmed XFlash devices.

15.1 OPTION BYTES

The four option bytes allow the hardware configu- OPT3:2 = SEC[1:0] Sector 0 size definition
ration of the microcontroller to be selected. These option bits indicate the size of sector 0 ac-
The option bytes can be accessed only in pro- cording to the following table.
gramming mode (for example using a standard Sector 0 Size SEC1 SEC0
ST7 programming tool).
0.5k 0 0
1k 0 1
OPTION BYTE 0
2k 1 0
OPT7 = WDG HALT Watchdog Reset on Halt 4k 1 1
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active. OPT1 = FMP_R Read-out protection
0: No Reset generation when entering Halt mode Readout protection, when selected provides a pro-
1: Reset generation when entering Halt mode tection against program memory content extrac-
tion and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
OPT6 = WDG SW Hardware or Software is selected will cause the whole memory to be
Watchdog erased first and the device can be reprogrammed.
This option bit selects the watchdog type. Refer to the ST7 Flash Programming Reference
0: Hardware (watchdog always enabled) Manual and Section 4.5 on page 17 for more de-
1: Software (watchdog to be enabled by software) tails
0: Read-out protection off
1: Read-out protection on
OPT5:4 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se- OPT0 = FMP_W FLASH write protection
lected threshold as shown in Table 31. This option indicates if the FLASH program mem-
ory is write protected.
Warning: When this option is selected, the pro-
Table 31. LVD Threshold Configuration
gram memory (and the option bit itself) can never
Configuration LVD1 LVD0 be erased or programmed again.
LVD Off 1 1 0: Write protection off
1: Write protection on
Highest Voltage Threshold (∼4.1V) 1 0
Medium Voltage Threshold (∼3.5V) 0 1
Lowest Voltage Threshold (∼2.8V) 0 0

OPTION BYTE 0 OPTION BYTE 1

7 0 7 0
WDG WDG FMP FMP RST OSCRANGE DIV2 PLL PLL
LVD1 LVD0 SEC1 SEC0 OSC
HALT SW R W C 2:0 EN x4x8 OFF
Default
1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1
Value

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OPTION BYTES (Cont’d)

OPTION BYTE 1
OPT7 = RSTC RESET clock cycle selection OPT2 = DIV2EN PLL Divide by 2 enable
This option bit selects the number of CPU cycles 0: PLL division by 2 enabled
inserted during the RESET phase and when exit- 1: PLL division by 2 disabled
ing HALT mode. For resonator oscillators, it is ad-
vised to select 4096 due to the long crystal stabili- Note: DIV2EN must be kept disabled when PLLx4
zation time. is enabled
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT1 = PLLx4x8 PLL Factor selection
0: PLLx4
OPT6:4 = OSCRANGE[2:0] Oscillator range 1: PLLx8
When the internal RC oscillator is not selected
(Option OSC=1), these option bits select the range
OPT0 = PLLOFF PLL disable
of the resonator oscillator current source or the ex-
0: PLL enabled
ternal clock source. 1: PLL disabled (by-passed)
OSCRANGE
2 1 0 These option bits must be configured as described
LP 1~2MHz 0 0 0
in Table 32 depending on the voltage range and
Typ. the expected CPU frequency
frequency MP 2~4MHz 0 0 1
range with MS 4~8MHz 0 1 0
Resonator Table 32. List of valid option combinations
HS 8~16MHz 0 1 1
Option Bits
Reserved 1 0 0 Target
VDD DIV2 PLL PLL
Ratio
1 0 1 EN OFF x4x8
x41) 2.7V - 3.65V x 0 0
External Clock 1 1 0
x4 0 0 1
1 1 1 3.3V - 5.5V
x8 1 0 1

Note:
OPT3 = OSC RC Oscillator selection 1. For a target ratio of x4 between 3.3V - 3.65V,
0: RC oscillator on this is the recommended configuration.
1: RC oscillator off

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OPTION BYTES (Cont’d)

OPTION BYTE 2 OPTION BYTE 3

OPT7:0 = Reserved. Must be kept at 1.
OPT7:6= PKG1:0 Package selection
These option bits select the package.
Version Selected Package PKG 1 PKG 0
K LQFP32 0 0
S LQFP44 0 1
C LQFP48 1 x

OPT5 = I2C3S I2C3SNS selection

0: I2C3SNS selected
1: I2C3SNS not selected

OPT4:0 = Reserved. Must be kept at 1.

OPTION BYTE 2 OPTION BYTE 3

7 0 7 0

Reserved PKG1 PKG0 I2C3S Reserved

Default
1 1 1 1 1 1 1 1 x x x 1 1 1 1 1
Value

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15.2 DEVICE ORDERING INFORMATION

Table 33. Supported part numbers

Program Data
RAM Temp.
Part Number Peripherals Memory EEPROM Package
(Bytes) Range
(Bytes) (Bytes)
ST72F340K2T6 LQFP32
8K FLASH 512
ST72F340S2T6 LQFP44
Common peripherals
ST72F340K4T6 LQFP32
16K FLASH 1K
ST72F340S4T6 LQFP44
ST72F344K2T6 LQFP32
Common peripherals 8K FLASH 512
ST72F344S2T6 + LQFP44
256 -40°C to 85°C
ST72F344K4T6 10-bit ADC, LQFP32
int high-accuracy 1MHz RC 16K FLASH 1K
ST72F344S4T6 LQFP44
Common peripherals
+
ST72F345C4T6 I²C3SNS 16K FLASH 1K LQFP48
10-bit ADC,
int high-accuracy 1MHz RC

Contact ST sales office for product availability

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ST7234x FASTROM MICROCONTROLLER OPTION LIST

(Last update: October 2006)

Customer ..........................................................................
Address ..........................................................................
..........................................................................
Contact ..........................................................................
Phone No ..........................................................................
Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- --------------------------------------------------- ---------------------------------------------------
| |
FASTROM DEVICE: 8K 16K
| |
--------------------------------- --------------------------------------------------- ---------------------------------------------------
LQFP32 | [ ] ST72P344K4T | [ ] ST72P344K2T
LQFP44 | [ ] ST72P344S4T | [ ] ST72P344S2T
LQFP48 | [ ] ST72P345C4T |
Conditioning for LQFP (check only one option): [ ] Tape & Reel [ ] Tube
Version/ Temperature range (please refer to datasheet for specific sales conditions):
[ ] 0°C to +70°C [ ] -10°C to +85°C [ ] -40°C to +85°C
Special Marking: [ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: LQFP32, LQFP48: 7 char. max "_ _ _ _ _ _ _ "
LQFP44: 10 char. max "_ _ _ _ _ _ _ _ _ _"
Clock Source Selection: [ ] External resonator or quartz
[ ] Internal RC Oscillator
[ ] External Clock:
[ ] LP: Low power (1 to 2 MHz)
[ ] MP: Medium power (2 to 4 MHz)
[ ] MS: Medium speed (4 to 8 MHz)
[ ] HS: High speed (8 to 16 MHz)

PLL: [ ] Disabled [ ] Enabled

[ ] PLL x 4 (*)
[ ] PLL x 8
DIV2: [ ] Disabled [ ] Enabled (*)

LVD Reset: [ ] Disabled [ ] Highest threshold

[ ] Medium threshold
[ ] Lowest threshold
Reset delay: [ ] 256 cycles [ ] 4096 cycles

Watchdog Selection: [ ] Software Activation [ ] Hardware Activation

Watchdog Reset on Halt: [ ] Disabled [ ] Enabled
Readout Protection: [ ] Disabled [ ] Enabled
FLASH Write Protection (**): [ ] Disabled [ ] Enabled
FLASH Sector 0 size (**): [ ] 0.5K [ ] 1K [ ]2K [ ] 4K
I2C3SNS (for ST72F345 only): [ ] Disabled [ ] Enabled

(*) DIV2 and PLLx4 cannot be enabled at the same time

(**) not available on first silicon version with waiver (contact ST local marketing)
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date: ..........................................................................
Signature: ..........................................................................

Please download the latest version of this option list from:

http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

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15.3 DEVELOPMENT TOOLS

Development tools for the ST7 microcontrollers in- RLink in-circuit debugger/programmer. These
clude a complete range of hardware systems and tools are supported by the ST7 Toolset from
software tools from STMicroelectronics and third- STMicroelectronics, which includes the STVD7 in-
party tool suppliers. The range of tools includes tegrated development environment (IDE) with
solutions to help you evaluate microcontroller pe- high-level language debugger, editor, project man-
ripherals, develop and debug your application, and ager and integrated programming interface.
program your microcontrollers. 15.3.3 Programming tools
15.3.1 Starter kits During the development cycle, the ST7-EMU3 se-
ST offers complete, affordable starter kits. Starter ries emulators and the RLink provide in-circuit
kits are complete, affordable hardware/software programming capability for programming the Flash
tool packages that include features and samples microcontroller on your application board.
to help you quickly start developing your applica- ST also provides a low-cost dedicated in-circuit
tion. programmer, the ST7-STICK, as well as ST7
15.3.2 Development and debugging tools Socket Boards which provide all the sockets re-
Application development for ST7 is supported by quired for programming any of the devices in a
fully optimizing C Compilers and the ST7 Assem- specific ST7 sub-family on a platform that can be
bler-Linker toolchain, which are all seamlessly in- used with any tool with in-circuit programming ca-
tegrated in the ST7 integrated development envi- pability for ST7.
ronments in order to facilitate the debugging and For production programming of ST7 devices, ST’s
fine-tuning of your application. The Cosmic C third-party tool partners also provide a complete
Compiler is available in a free version that outputs range of gang and automated programming solu-
up to 16KBytes of code. tions, which are ready to integrate into your pro-
The range of hardware tools includes full-featured duction environment.
ST7-EMU3 series emulators and the low-cost

15.3.4 Order codes for ST72F34x development tools

Table 34. Development tool order codes
Programming Tool
MCU Starter kit Emulator In-circuit debugger/ Dedicated programmer
programmer
ST72F340 STX-RLINK 2) ST7SB20J/xx 3)5)
ST72F344 ST72F34x-SK/RAIS 1) ST7MDT40-EMU3
ST72F345 ST7-STICK 3)4) ST7SB40-QP48/xx 3)6)

Notes:
1. USB connection to PC
2. RLink with ST7 tool set
3. Add suffix /EU, /UK or /US for the power supply for your region
4. Parallel port connection to PC
5. Only available for LQFP32 and LQFP44 packages
6. Only available for LQFP48 package

For additional ordering codes for spare parts and

accessories, refer to the online product selector at
www.st.com/mcu.

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16 KNOWN LIMITATIONS

16.1 External interrupt missed LD A,#01

To avoid any risk if generating a parasitic interrupt, LD sema,A ; set the semaphore to '1'
the edge detector is automatically disabled for one LD A,PFDR
clock cycle during an access to either DDR and AND A,#02
OR. Any input signal edge during this period will
not be detected and will not generate an interrupt. LD X,A ; store the level before writing to
PxOR/PxDDR
This case can typically occur if the application re-
freshes the port configuration registers at intervals LD A,#$90
during runtime. LD PFDDR,A ; Write to PFDDR
Workaround LD A,#$ff
The workaround is based on software checking LD PFOR,A ; Write to PFOR
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a LD A,PFDR
level change (depending on the sensitivity pro- AND A,#02
grammed for this pin) the interrupt routine is in- LD Y,A ; store the level after writing to
voked using the call instruction with three extra PxOR/PxDDR
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the LD A,X ; check for falling edge
IRET instruction at the end of the interrupt service cp A,#02
routine). jrne OUT
But detection of the level change does not make TNZ Y
sure that edge occurs during the critical 1 cycle du-
ration and the interrupt has been missed. This may jrne OUT
lead to occurrence of same interrupt twice (one LD A,sema ; check the semaphore status if
hardware and another with software call). edge is detected
To avoid this, a semaphore is set to '1' before CP A,#01
checking the level change. The semaphore is
jrne OUT
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore call call_routine; call the interrupt routine
status is checked and if it is '1' this means that the OUT:LD A,#00
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction. LD sema,A
.call_routine ; entry to call_routine
There is another possible case i.e. if writing to PUSH A
PxOR or PxDDR is done with global interrupts dis- PUSH X
abled (interrupt mask bit set). In this case, the PUSH CC
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is .ext1_rt ; entry to interrupt routine
done after the global interrupts are enabled (inter- LD A,#00
rupt mask bit reset) and by checking the status of LD sema,A
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in- IRET
voked with the call instruction. Case 2: Writing to PxOR or PxDDR with Global In-
To implement the workaround, the following soft- terrupts Disabled:
ware sequence is to be followed for writing into the SIM ; set the interrupt mask
PxOR/PxDDR registers. The example is for for
LD A,PFDR
Port PF1 with falling edge interrupt sensitivity. The
software sequence is given for both cases (global AND A,#$02
interrupt disabled/enabled). LD X,A ; store the level before writing to
Case 1: Writing to PxOR or PxDDR with Global In- PxOR/PxDDR
terrupts Enabled: LD A,#$90

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LD PFDDR,A; Write into PFDDR 16.2 Clearing active interrupts outside

LD A,#$ff interrupt routine
LD PFOR,A ; Write to PFOR When an active interrupt request occurs at the
LD A,PFDR same time as the related flag is being cleared, an
unwanted reset may occur.
AND A,#$02
Note: clearing the related interrupt mask will not
LD Y,A ; store the level after writing to PxOR/ generate an unwanted reset
PxDDR
Concurrent interrupt context
LD A,X ; check for falling edge
The symptom does not occur when the interrupts
cp A,#$02 are handled normally, i.e.
jrne OUT when:
TNZ Y – The interrupt flag is cleared within its own inter-
jrne OUT rupt routine
LD A,#$01 – The interrupt flag is cleared within any interrupt
LD sema,A ; set the semaphore to '1' if edge is routine
detected – The interrupt flag is cleared in any part of the
RIM ; reset the interrupt mask code while this interrupt is disabled
LD A,sema ; check the semaphore status If these conditions are not met, the symptom can
be avoided by implementing the following se-
CP A,#$01 quence:
jrne OUT Perform SIM and RIM operation before and after
call call_routine; call the interrupt routine resetting an active interrupt request.
RIM Example:
OUT: RIM SIM
JP while_loop reset interrupt flag
.call_routine ; entry to call_routine RIM
PUSH A Nested interrupt context:
PUSH X The symptom does not occur when the interrupts
are handled normally, i.e.
PUSH CC
when:
.ext1_rt ; entry to interrupt routine
– The interrupt flag is cleared within its own inter-
LD A,#$00
rupt routine
LD sema,A
– The interrupt flag is cleared within any interrupt
IRET routine with higher or identical priority level
16.1.1 Unexpected Reset Fetch – The interrupt flag is cleared in any part of the
If an interrupt request occurs while a "POP CC" in- code while this interrupt is disabled
struction is executed, the interrupt controller does If these conditions are not met, the symptom can
not recognise the source of the interrupt and, by be avoided by implementing the following se-
default, passes the RESET vector address to the quence:
CPU.
PUSH CC
Workaround
SIM
To solve this issue, a "POP CC" instruction must
reset interrupt flag
always be preceded by a "SIM" instruction.
POP CC

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16.3 16-bit Timer PWM Mode 16.5 In-Application Programming

In PWM mode, the first PWM pulse is missed after Not available on the first silicon revision currently
writing the value FFFCh in the OC1R register in production (rev Z). This limitation will be correct-
(OC1HR, OC1LR). It leads to either full or no PWM ed on the next silicon revision. Refer to Table 35
during a period, depending on the OLVL1 and Silicon revision identification.
OLVL2 settings.
16.6 Programming of EEPROM data
16.4 SCI Wrong Break duration
Description
Description In user mode, when programming EEPROM data
A single break character is sent by setting and re- memory, the read access to the program memory
setting the SBK bit in the SCICR2 register. In between E000h and FFFFh can be corrupted.
some cases, the break character may have a long- Impact on application
er duration than expected:
The EEPROM programming routine must be locat-
- 20 bits instead of 10 bits if M=0 ed outside this program memory area.
- 22 bits instead of 11 bits if M=1 Any access to the interrupt vector table can result
In the same way, as long as the SBK bit is set, in an unexpected code being executed, so the in-
break characters are sent to the TDO pin. This terrupts must be masked.
may lead to generate one break more than expect- Workaround
ed.
The sequence to program the EEPROM data (re-
Occurrence fer to Section 5.3 on page 19) must be executed
The occurrence of the problem is random and pro- within C000h-DFFFh area or from the RAM. It is as
portional to the baudrate. With a transmit frequen- follows:
cy of 19200 baud (fCPU=8MHz and SCI- set E2LAT bit
BRR=0xC9), the wrong break duration occurrence
is around 1%. write up to 32 bytes in E2PROM area
SIM ; to disable the interrupts
Workaround set E2PGM bit
If this wrong duration is not compliant with the wait for E2PGM=0
communication protocol in the application, soft- RIM ; to enable the interrupts
ware can request that an Idle line be generated
return to the program memory
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa- 16.7 Flash Write/Erase Protection
bling interrupts.
Not available on the first silicon revision currently
The exact sequence is:
in production (rev Z). This limitation will be correct-
- Disable interrupts ed on the next silicon revision. Refer to Table 35
- Reset and Set TE (IDLE request) Silicon revision identification.
- Set and Reset SBK (Break Request)
- Re-enable interrupts
Table 35. Silicon revision identification

Trace code internal sales types

Device Status
marked on device on box label
72F344xxxx$x2
In Production “xxxxxxxxZ”
ST72F344xxxx 72F345xxxx$x2
ST72F345xxxx 72F344xxxx$x4
Under qualification “xxxxxxxxX”
72F345xxxx$x4

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17 REVISION HISTORY
Date Revision Main changes
29-April-2006 1 First release on internet
Removed references to BGA56 and QFN40 packages
TQFP package naming changed to LQFP (Low-profile Quad Flat)
Changed number of I/O ports on first page
PDVD (Power Down Voltage Detector) replaced by AVD (Auxiliary Voltage Detector)
Modified note 3 to Table 2 on page 12
Added PF4 to Figure 3 on page 6 and Figure 4 on page 7
“MEMORY ACCESS” on page 19
Modified Figure 8, Figure 9 on page 20 and Figure 10 on page 21
Changed RCCR table in Section 7.2 on page 29 (fRC=1MHz)
References to PDVDF, PDVDIE corrected to AVDF, AVDIE: Section 7.5.2 on page 34
Current characteristics Section 13.2.2 on page 153 updated
General operating conditions table updated, Section 13.3.1 on page 154
Data updated in Section 13.3.2 on page 154, note replaced
Table modified in Section 13.3.3 on page 155
Notes adjusted for table in Section 13.4 on page 156
Modified Section 13.5 on page 156 (for VDD=5V)
Table in Section 13.6.1 on page 157 modified
23-Oct-2006 2 Updated Section 13.6.2 on page 159
Added Section 13.7.2 and Figure 93 on page 160
Table in Section 13.8.2 on page 163 modified
Absolute maximum ratings and electrical sensitivity table updated, Section 13.9.3 on
page 165
Added note 1 to VIL and VIH in Section 13.10.1 on page 166
Table in Section 13.10.2 on page 167 modified (for VDD= 3.3V and VDD=2.7V)
Modified graphs in Section 13.10.2 on page 167
tg(RSTL)in updated in Section 13.11 on page 172
Updated Table 29 on page 174
Updated Table 30 on page 180
Modified default values for option byte 2 and 3 on page 183
Added option list on page 185
Added “DEVELOPMENT TOOLS” on page 186
Added known limitations: “In-Application Programming” on page 189, “Programming
of EEPROM data” on page 189, and “Flash Write/Erase Protection” on page 189
Modified Section 16.6 on page 189
Changed status of the document (datasheet instead of preliminary data)

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Notes:

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