Panya Niwati

CSE-2(M)

ASSIGNMENT-2 06915002718

Q1. Draw and explain the architecture of 8086.

A Microprocessor is an Integrated Circuit with all the functions of a CPU

however, it cannot be used standalone since unlike a microcontroller it has no
memory or peripherals.
8086 does not have a RAM or ROM inside it. However, it has internal
registers for storing intermediate and final results and interfaces with memory
located outside it through the System Bus.
In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline
Packaged IC.
The size of the internal registers (present within the chip) indicates how much
information the processor can operate on at a time (in this case 16-bit
registers) and how it moves data around internally within the chip, sometimes
also referred to as the internal data bus.
8086 provides the programmer with 14 internal registers, each 16 bits or 2
Bytes wide.

Memory segmentation:
• To increase execution speed and fetching speed, 8086 segments the
memory.
• It’s 20-bit address bus can address 1MB of memory, it segments it
into 4 64kB segments.
• 8086 works only with four 64KB segments within the whole 1MB
memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus
Interface Unit (BIU), and The Execution Unit (EU). These are explained as
following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the
System Bus. It performs various machine cycles such as memory read, I/O
read etc. to transfer data between memory and I/O devices.
BIU performs the following functions-
• It generates the 20-bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6-byte prefetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a
prefetch queue and an Address Generation Circuit.
Instruction Pointer (IP):
• It is a 16-bit register. It holds offset of the next instructions in the
Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20 bit physical address of the
Code Segment.
• Address of the next instruction is calculated as CS x 10H + IP.
Example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset = 44210H
This is the address of the instruction.
Code Segment register:
CS holds the base address for the Code Segment. All programs are stored in
the Code Segment and accessed via the IP.
Data Segment register:
DS holds the base address for the Data Segment.
Stack Segment register:
SS holds the base address for the Stack Segment.
Extra Segment register:
ES holds the base address for the Extra Segment.
Address Generation Circuit:
• The BIU has a Physical Address Generation Circuit.
 • It generates the 20-bit physical address using Segment and Offset
addresses using the formula:
• Physical Address
= Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue:
• It is a 6-byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the
current instruction is called pipelining.
• Gets flushed whenever a branch instruction occurs.

2. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU,
Special purpose registers, Instruction Register and Instruction Decoder and the
Flag/Status Register.

1. Fetches instructions from the Queue in BIU, decodes and executes

arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the
microprocessor.
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine
cycles.
8086 has four 16-bit general purpose registers AX, BX, CX and DX. Store
intermediate values during execution. Each of these have two 8-bit parts
(higher and lower).
• AX register:
It holds operands and results during multiplication and division
operations. Also, an accumulator during String operations.
• BX register:
It holds the memory address (offset address) in indirect addressing
modes.
• CX register:
It holds count for instructions like loop, rotate, shift and string
operations.
• DX register:
It is used with AX to hold 32-bit values during multiplication and
division.
Arithmetic Logic Unit (16 bit):
Performs 8 and 16 bit arithmetic and logic operations.
Special purpose registers (16-bit):
 • Stack Pointer:
Points to Stack top. Stack is in Stack Segment, used during
instructions like PUSH, POP, CALL, RET etc.
• Base Pointer:
BP can hold offset address of any location in the stack segment. It is
used to access random locations of the stack.
• Source Index:
It holds offset address in Data Segment during string operations.
• Destination Index:
It holds offset address in Extra Segment during string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The
instruction decoder decodes it and sends the information to the control circuit
for execution.
Flag/Status register (16 bits):
It has 9 flags that help change or recognize the state of the microprocessor.
6 Status flags:
1. carry flag (CF)
2. parity flag (PF)
3. auxiliary carry flag (AF)
4. zero flag(Z)
5. sign flag(S)
6. overflow flag (O)
Status flags are updated after every arithmetic and logic operation.
3 Control flags:
1. trap flag (TF)
2. interrupt flag (IF)
3. direction flag (DF)
These flags can be set or reset using control instructions like CLC, STC, CLD,
STD, CLI, STI, etc.
The Control flags are used to control certain operations.

Q2. Explain various addressing modes of 8086 with examples.

The way of specifying data to be operated by an instruction is known
as addressing modes. This specifies that the given data is an immediate data or
an address. It also specifies whether the given operand is register or register
pair.
Types of addressing modes:
1. Register mode – In this type of addressing mode both the operands
are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
2. Immediate mode – In this type of addressing mode the source
operand is a 8 bit or 16 bit data. Destination operand can never be
immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
MOV AX, 2000
MOV CS, AX
3. Displacement or direct mode – In this type of addressing mode the
effective address is directly given in the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
4. Register indirect mode – In this addressing mode the effective
address is in SI, DI or BX.
Example:
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
5. Based indexed mode – In this the effective address is sum of base
register and index register.
6. Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base
register.
Example:
MOV AL, [BP+SI]
 MOV AX, [BX+DI]
7. Indexed mode – In this type of addressing mode the effective address
is sum of index register and displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
8. Based mode – In this the effective address is the sum of base register
and displacement.
Example:
MOV AL, [BP+ 0100]
9. Based indexed displacement mode – In this type of addressing mode
the effective address is the sum of index register, base register and
displacement.
Example:
MOV AL, [SI+BP+2000]
10.String mode – This addressing mode is related to string instructions.
In this the value of SI and DI are auto incremented and decremented
depending upon the value of directional flag.
Example:
MOVS B
MOVS W
11.Input/Output mode – This addressing mode is related with input
output operations.
Example:
IN A, 45
OUT A, 50
12.Relative mode –
In this the effective address is calculated with reference to instruction
pointer.
Example:
JNZ 8-bit address
IP=IP+8-bit address

Q3. What are the steps followed by 8086 when an interrupt comes? How
much memory is required to store the interrupt vector table?
In 8086 microprocessor following tasks are performed when microprocessor
encounters an interrupt:
 1. The value of flag register is pushed into the stack. It means that first
the value of SP (Stack Pointer) is decremented by 2 then the value of
flag register is pushed to the memory address of stack segment.
2. The value of starting memory address of CS (Code Segment) is
pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the next word location.
6. Interrupt and Trap flag are reset to 0.

Q4. What is Interrupt Sub-routine (ISR) and where is it stored? What

contents are stored in the interrupt vector table?

Interrupt Service Routine

For every interrupt, there must be an interrupt service routine (ISR), or interrupt
handler. When an interrupt occurs, the microcontroller runs the interrupt service
routine. For every interrupt, there is a fixed location in memory that holds the
address of its interrupt service routine, ISR. The table of memory locations set
aside to hold the addresses of ISRs is called as the Interrupt Vector Table.
Interrupt Vector Table

There are six interrupts including RESET in 8051.

Interrupts ROM Location (Hex) Pin

Interrupts ROM Location (HEX)

Serial COM (RI and TI) 0023

Timer 1 interrupts (TF1) 001B

External HW interrupt 1 (INT1) 0013 P3.3 (13)

External HW interrupt 0 (INT0) 0003 P3.2 (12)

Timer 0 (TF0) 000B

Reset 0000 9

• When the reset pin is activated, the 8051 jumps to the address location
0000. This is power-up reset.
• Two interrupts are set aside for the timers: one for timer 0 and one for
timer 1. Memory locations are 000BH and 001BH respectively in the
interrupt vector table.
• Two interrupts are set aside for hardware external interrupts. Pin no. 12
and Pin no. 13 in Port 3 are for the external hardware interrupts INT0 and
INT1, respectively. Memory locations are 0003H and 0013H respectively
in the interrupt vector table.
• Serial communication has a single interrupt that belongs to both receive
and transmit. Memory location 0023H belongs to this interrupt.

Q5. What is the difference between physical address and effective address?
Obtain the physical address for the offset address 07EA:0103.
Effective address:

• It is also known as an offset address.

• It is the concern of the program.

• It is that virtual address that is generated by the program.

Physical address:

• It is also known as the actual address.

• It is the concern of the operating system.

• It is that address that is generated by the hardware.

Effective Address: 07EA

Offset Address: 0103

Physical Address: 07EA*10+0103

Physical Address: 07FA3H