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Low Power CMOS VLSI Design: Aditya Japa Assistant Professor (ECE) KL Hyderabad 12/07/2021

This document provides information about a course on low power CMOS VLSI design. [1] The course objectives are the exploration of low power techniques at the transistor, circuit, and architectural levels for CMOS VLSI sub-systems. [2] It will also cover the design and analysis of low voltage, low power adders, multipliers and memories. [3] The instructor's qualifications include a Ph.D. in tunnel FET based energy efficient circuit design with a focus on hardware security.

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karthik
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51 views14 pages

Low Power CMOS VLSI Design: Aditya Japa Assistant Professor (ECE) KL Hyderabad 12/07/2021

This document provides information about a course on low power CMOS VLSI design. [1] The course objectives are the exploration of low power techniques at the transistor, circuit, and architectural levels for CMOS VLSI sub-systems. [2] It will also cover the design and analysis of low voltage, low power adders, multipliers and memories. [3] The instructor's qualifications include a Ph.D. in tunnel FET based energy efficient circuit design with a focus on hardware security.

Uploaded by

karthik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Low Power CMOS VLSI Design

Aditya Japa
Assistant professor (ECE)
KL Hyderabad
12/07/2021
Course Objective
Exploration of low power techniques with transistor, circuit, and architectural
level for CMOS VLSI sub-systems. Design and analysis of low voltage, low
power adders, multipliers and low power memories (SRAM and DRAM).
Course Contents
• Sources of power dissipation

• Low power circuit techniques for leakage power reduction

• Low voltage low power adders and multipliers

• Low power memories(ROM and RAM)

• Low power SRAM technologies

• Basics of DRAM and future trends


Course instructor
Name: Japa Aditya

Qualification: (Ph.D. -Thesis submitted-June 2021) From IIIT Naya Raipur.

Research work: Tunnel FET based Energy Efficient Circuit Design with Enhanced
Hardware security.

Teaching interests: Circuits and Systems for VLSI, Cryptography and hardware security.

Research interests: Emerging semiconductor device technologies (Tunnel FETs, FinFETs,


and NCFETs) based energy efficient circuit design, hardware security modules or
subsystems design.
Evaluation scheme
Metal Oxide Semiconductor FET(MOSFET)
Device structure
MOSFET consists of three terminal source, drain and gate

N-channel MOSFET
Symbols of MOSFET:

PMOS NMOS

Input voltage : Gate-to-source voltage(VGS)


Output voltage: Darin-to-source voltage(VDS)
Output current: Drain current (ID)
Input current: Gate current (IG)
NMOS Device characteristics

(a) Transfer characteristics (b) Output characteristics

• Transfer characteristics are drawn between VGS and ID, it shows that NMOS produces the drain
current when VGS greater than threshold voltage(Vt).
• The output characteristics are drawn between VDS and ID. At small vale of VDS MOSFET
operates in the triode region, and when VDS increases it enters into saturation region.
Regions of operation
• Cut-off region: VGS  0, VDS  0
With this biasing transistor will be in cut-off region and zero current flows

• Triode or linear region: VGS  Vt ,VDS  VGS  Vt


W  2
 VGS  Vt VDS  VDS 
1
iD   nCox 
L  2 
• Saturation region:
VGS  Vt ,VDS  VGS  Vt
1 W
iD   nCox 


 VGS  Vt 
2

2 L 
Complementary metal-oxide-semiconductor (CMOS)
technology
• CMOS technology is a predominant technology for manufacturing integrated
circuits. This technology uses both NMOS and PMOS to realize various logic
functions.

Cross section of two transistors in a CMOS gate, in an N-well CMOS process


CMOS Inverter
• The CMOS inverter basically covers the flavors
of both PMOS and NMOS.
• In CMOS inverter, PMOS transistor is placed
between supply voltage and output, the NMOS
transistor is place between output and ground
terminal.
CMOS inverter
• Inverter always drives a load capacitor (CL).
Functionality of CMOS Inverter
• When Vin is high and equal to VDD the NMOS transistor is ON and the PMOS is OFF.

• Hence direct current flows from Vout to the ground which shows that Vout = 0 V.

• On the other hand, when Vin is low then NMOS transistor is OFF and PMOS transistor is ON.

• Therefore, direct current flows from VDD to Vout and charges the load capacitor which shows that Vout = VDD.
Voltage transfer characteristics (VTC)
• VTC is drawn between input and output of the
inverter.
• PMOS and NMOS devices operate in different
regions at different parts of VTC.
• The VTC of the inverter hence exhibits a very
narrow transition zone.
Benefits of CMOS technology over MOS
• Very low static power consumption

• Reduce the complexity of the circuit

• The high density of logic functions on a chip

• High noise immunity

• Layout of CMOS is more regular

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