8086 Microprocessor

Definition: 8086 is a 16-bit microprocessor and was designed in 1978 by

Intel. Unlike, 8085, an 8086 microprocessor has 20-bit address bus.
Thus, is able to access 220 i.e., 1 MB address in the memory.

As we know that a microprocessor performs arithmetic and logic

operations. And an 8086 microprocessor is able to perform these
operations with 16-bit data in one cycle. Hence is a 16-bit
microprocessor. Thus the size of the data bus is 16-bit as it can carry
16-bit data at a time. The architecture of 8086 microprocessor, is very
much different from that of 8085 microprocessor.
We have already discussed the introduction to the microprocessor
and 8085 microprocessor. So, lets now proceed further and understand
the architecture and working of 8086 microprocessor.
Block Diagram of 8086 Microprocessor

The architecture of 8086 microprocessor is composed of 2 major units,

the BIU i.e., Bus Interface Unit and EU i.e., Execution Unit. The figure
below shows the block diagram of the architectural representation of the
8086 microprocessor:
Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) manages the data, address and control
buses.

The BIU functions in such a way that it:

 Fetches the sequenced instruction from the memory,

 Finds the physical address of that location in the memory where the
instruction is stored and
 Manages the 6-byte pre-fetch queue where the pipelined instructions
are stored.
An 8086 microprocessor exhibits the property of pipelining the instructions
in a queue while performing decoding and execution of the previous
instruction. This saves the processor time of operation by a large amount.
This pipelining is done in a 6-byte queue. Also, the BIU contains 4
segment registers. Each segment register is 16-bit. The segments are
present in the memory and these registers hold the address of all the
segments. These registers are as follows:
1.Code segment register: It is a 16-bit register and holds the address of
the instruction or program stored in the code segment of the memory.
Also, the IP in the block diagram is the instruction pointer which is a default
register that is used by the processor in order to get the desired
instruction. The IP contains the offset address of the next byte that is to
be taken from the code segment.
2. Stack segment register: The stack segment register provides the
starting address of the stack segment in the memory. Like in stack pointer,
PUSH and POP operations are used in this segment to give and take the
data to/from it.
3. Data segment register: It holds the address of the data segment. The
data segment stores the data in the memory whose address is present in
this 16-bit register.
4. Extra segment register: Here the starting address of the extra
segment is present. This register basically contains the address of the
string data.
It is to be noteworthy that the physical address of the instruction is
achieved by combining the segment address with that of the offset
address.

6-byte pre-fetch queue: This queue is used in 8086 in order to perform

pipelining. As at the time of decoding and execution of the instruction in
EU, the BIU fetches the sequential upcoming instructions and stores it in
this queue.

The control unit decodes the opcode and generates control signals that
inform the BL and CL register to release the value stored in it. Also, it
signals the ALU to perform the ADD operation on that particular data.

It is noteworthy that in any instruction, like ADD BL, CL. BL denotes the
destination of the result of the add operation. This clearly shows that
whatever, the operation is performed its result must be stored in the first
register i.e., BL for this particular example.

Let us take another example: Consider an instruction, ADD CL, 05H.

This means that the operand which is 05H is to be added with the data
present in the CL register and is stored in that particular register i.e., CL.
In such conditions, the operand is not provided to the control unit as only
the opcode is required to be decoded by the CU. Hence the operand is
directly provided to the ALU. Also, the status of this result is stored in the
flag register. So, whenever, ALU carries out an operation, it
simultaneously generates the result as well as its status.

It is to be noteworthy that in BIU, pipelining fails whenever there is

branching in the instruction. This is because generally instructions are
present in a sequential manner. But, sometimes the instructions are
required to be executed unsequentially. However, in the queue, the
instructions are stored sequentially. So, in case there exist a need for any
random instruction to be decoded. The opcode stored in the queue will
become invalid and must be cleared at that particular time.

Memory Segmentation in 8086

Microprocessor
Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address. It is
basically used to enhance the speed of execution of the computer system, so that the
processor is able to fetch and execute the data from the memory easily and fast.

Need for Segmentation –

The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.
 Code segment register (CS): is used for addressing memory location in
the code segment of the memory, where the executable program is
stored.
 Data segment register (DS): points to the data segment of the memory
where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory
which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of
the memory. The stack segment is that segment of memory which is used
to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address,
so as to access one of the 1MB memory locations. The four segment
registers actually contain the upper 16 bits of the starting addresses of the
four memory segments of 64 KB each with which the 8086 is working at that
instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It
is an independent, separately addressable unit. Starting address will always
be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time.
However, it works only with four 64KB segments within the whole 1MB
memory.
Below is the one way of positioning four 64 kilobyte segments within the 1M
byte memory space of an 8086.

Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts
along with this 64kilobytes location of the first segment, then the two are
said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address
and its maximum size can go up to 64kilobytes. But if another segment
starts before this 64kilobytes location of the first segment, then the two
segments are said to be Non-Overlapped Segment.
Rules of Segmentation Segmentation process follows some rules as
follows:
 The starting address of a segment should be such that it can be evenly
divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64
kB.