5

CONTENT
4

SHEET
Trung Tâm Máy Tính AV
3 2 1

Cover Sheet 1
Block Diagram
Clock Distribution
2
3
Arrowhead
D
Power Delivery Map 4
BTX (Version: A03) D

Platform Sequence 5
SM BUS MAPPING 6
CPU: Intel Conroe, Wolfdale processors in LGA775 Package.
CK505 ClockGen 7
Notice that Apart from PRD Requirement CPU will support Yorkfield as well.
VRD11.1-ADP3290 8
System Chipset:
LGA775 -1~3 9~11
North Bridge ... Eaglelake-Q45
Eaglelake -GMCH-1~4 12~15
South Bridge ... ICH10DO
DDRIII-CHA/DIMM 1 & 3 16
Main Memory:
DDRIII-CHB/DIMM 2 & 4 17
Dual Channel / DDR-III * 4 (Maximum to 8GB)
DDRIII-Termination 18
C
On Board Device: C

1D1V/FSB_VTT/1D5V 19
Clock Generator ... IDTCV184-2BPAG
STR1D5V/3D3_DUAL/5V_DUAL 20 Super I/O ... SMSC5524/5514E
VGA Connector 21 LAN ... Boazman 82567-B0
HDA Codec ... AD1984A-04
PCI-E 16X / 1X Slot 22
BIOS ... SPI Flash ROM-64Mbit
ICH10DO-1~4 23~26
Expansion Slots:
LAN BOAZMAN 27
PCI EXPRESS 16X SLOT *1
HDA Codec AD1984 28 PCI EXPRESS 1X SLOT * 1
Super I/O--SMSC5524/5514E 29 PCI SLOT * 2 Board Stack-up
(1080 Prepreg Considerations)
DP / Gen II 30 PWM Controller:
B

PCI Slot 31 Controller ... ADP3293 (3Phase) Solder Mask

1.9mils Cu plus plating B

Driver ... ADP3120AJRZ PREPREG 2.7mils

BTX, PRT, MISC Connector 32 1 oz. (1.2mils)
Cu Power
Plane
CPU / System Fan 33
CORE 47mils

TPM, XDP,LPC CONN. 34

1 oz. (1.2mils)
POP1 XDP, LPC HDR, SPI Debug Cu GND
USB Header / COM Port 35 Proto Build Plane
PREPREG 2.7mils
Solder Mask

LAN / Rear USB Connector 36 POP3 SIO SMSC 5524C

1.9mils Cu plus plating

POP4 SIO SMSC 5514E

FP / SPI / Floppy 37
Single End 50ohm Top/Bottom : 4mils
POP5 TPM STMicro(4.4mm) USB2.0 - 90ohm : 15/4.5/7.5/4.5/15
Reserved-1~2 38~39 SATA - 95ohm : 15/4/8/4/15
PCIE - 85ohm : 15/4/8/4/15
POP6 DMI - 95ohm : 15/4/8/4/15
KB/MS/COM2 40 TPM Z(6.1mm) LAN - 95ohm : 15/4/8/4/15

A IRQ Map 41 POP7 TPM J(6.1mm) A

RESET Map 42 POP8 TPM Winbond(4.4mm)

AMT TIMMING 43 POP9 QFN

Title

Strap Pin & ID POP Table 44 Cover Sheet

DWG NO Rev
A01
History 45 Arrowhead

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Date: Thursday, November 25, 2010
1
Sheet 1 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

VRD 11.1
3 Phase PWM
PAGE 8
LGA775 Processor
Socket T
D
XDP Header PAGE 9,10,11 D
PAGE 34

VGA IDTCV184 Clock Generator

FSB PAGE 7
Connector
PAGE 21 800/1066/1333

PCI-E X16
Channel A DDRIII
GFX Connector 12 Lanes DDRIII 800/1066
PAGE 22 DIMM1 PAGE 16

DIMM3
GMCH PAGE 16

4 Lanes
PCI-E Gen2 Eaglelake
Switch Q45 DDRIII 800/1066 Channel B DDRIII
Display Port Connector PAGE 30
C PAGE 12,13,14,15 C
PAGE 30 DIMM2 PAGE 17

DIMM4 PAGE 17
DMI I/F
4 Lanes Contorl Link

Front Panel
USB2.0 Port x2
PAGE 35
Intel BOAZMAN
PAGE 27

Internal USB
USB2.0 Port x2 USB 2.0
PAGE 35

PCI Slot 1
PAGE 31
PCI I/F ICH10DO SATA I/F Serial ATA
Back Panel SATA x3
USB2.0 Port x6 PCI Slot 2 PAGE 31
ESATA x1PAGE 24
B B
PAGE 36 PAGE 23,24,25,26

PCI-E X1
PCI-E X1 Slot 1
PAGE 22

PAGE 34
TPM
HD Link Intel HD Audio
ADI AD1984 PAGE 28
PAGE 34
TCM
LPC I/F
TPM HEADER
PAGE 34

SPI I/F
Super I/O BIOS
SMSC 5524/5514E SPI Flash 64Mb
PAGE 29
PAGE 37
A A

PS2/COM2 Floppy
Drive Connector COM1 Printer Port Title
PAGE 40 Header PAGE 37 PAGE 35 PAGE 32
Block Diagram
DWG NO Rev
A01
Arrowhead

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1
Sheet 2 of 45
 5

14.318MHz
4

Trung Tâm Máy Tính AV 3 2 1

CPU

D
CPU 200/266/333 MHz Diff Pair D

MCH 200/266/333 MHz Diff Pair

DDRIII 4 Slots 12 Diff CLKs

PCI Express 100 MHz Diff Pair Channel A DDRIII DDRIII 800/1066
PCI Express x16 Gfx
DIMM1
GMCH DIMM2
DOT 96 MHz Diff Pair Eaglelake
Channel B DDRIII DDRIII 800/1066
DIMM3
PCI Express/DMI 100 MHz Diff Pair DIMM4
C C
IDTCV184 ClockGen

PCI Express/DMI 100 MHz Diff Pair

USB/SIO 48 MHz

ICH 33 MHz

REF 14 MHz

CK_PCI_STOP
ICH10
CK_CPU_STOP
Azalia Bit Clock

B
PCI 33 MHz PCI Slot 1 B

PCI 33 MHz PCI Slot 2

32.768KHz
TPM 33 MHz
TPM 1.2
HD Audio

Boazman LAN
Super I/O
SIO 33 MHz
SATA 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair

A A

PCI Express 100 Mhz Diff Pair PCI Express x1 Slot

XDP 100MHz Diff Pair XDP Title

Clock Distribution
DWG NO Rev
A01
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1
Sheet 3 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

BTX P/S 3.3V Super I/O SMSC

3.3V
CPU Icc(Max)=50mA
VRD 11.1 Conroe Wolfdale Yorkfiled
5V 5VSB Switching 3.3SBV
12V Core 95W Icc(Max)=50mA(S0) 5V
D
3 Phase 100A 1.15~1.5V D

5VDUAL 85A VR_TDC 3.3SBV

DDR3 Channel A Icc(Max)= Icc(Max)=38mA(S3)
1.1V FSB 5VSB
10A Vtt=4.6A
Vdd (Core)=1.5V
Ivdd(Max)=3.6A(per channel)
5VUSB
USB2.0 12 Ports Icc(Max)=
+5V DUAL=5A(S0, S1)
Vtt (Core)
0.75V
Eaglelake GMCH Q45 +5V DUAL=20mA(S3) 4.345A(S0,S1)
22mA(S3)
Ivterm(Max)=415mA Single Phase Switch
(per channel) 5V to 1.5V DDRIII Linaer FSB_VTT
Ivdd(Max)=18A 5.8A 1.1V 1.1V PS2
4A VRTDC +5V DUAL=345mA(S0, S1)
+5V DUAL=2mA(S3)
DDR3 Channel B
1.5V VCCSM
Vdd (Core)=1.5V VTT_DDR 1.5V VCC_SMCLK
Ivdd(Max)=3.6A(per channel) 0.83A-0.75V LDO

GMCH 1.1V PCI Express X16

Vtt (Core) 5V 22A Vcore (Core Logic)
0.75V Switching 1.1V
slot (1)
Ivterm(Max)=415mA 12V
(per channel)
+12V=5.5A
C C

3.3VSB
Linear 1.5V Icc(Max)=0.375A(wake)
to 1.1V VCC_CL Icc(Max)=0.02A(no wake)
VCC_CL 3A 1.1V
3A
+3.3V=3A
3.3V VCCA_DAC 66mA
3.3V 3.3V VCC3_3 15.8mA PCI Express X1
HDA Codec ADI1984A Per slot (2)
Vcc LDO
5V +12V=0.5A
12V
Icc(Max)=200mA to 5V 3.3VSB
ICH10DO Icc(Max)=0.375A(wake)
Vcc Icc(Max)=0.02A(no wake)
3.3V 1.1V VCCDMI 41mA
Icc(Max)=40mA
+3.3V=3A
Linaer 1.1V VCC_CPU_IO 14mA
1.5V to 1.5V
V_1P5V_ICH 1.1V (Core) VCC1_1
2A 1.16A PCI Slot
B B
-12V
1.5V (USB &SATA) VCC1_5A Icc(Max)=0.1A -12V
1.652A
Linear 2.4V 1.5V (PCIe)VCC1_5B
Linear 3.3V to 1.5V
to 2.4V 0.646A 5V
V_1P5V_ICH 1.5V VCCGLAN1_5 5V Icc(Max)=5A
2A 80mA
3.3V
RTC Icc(Max)=7.6A
5VSB RTC=5uA
Battery
12V
3.3V VccCL3_3 19mA Icc(Max)=0.5A
5V_STBY to 3.3SB 3.3V VccSUS3_3 212mA
1.5A 3.3V VccLAN (10/100) 19mA 3.3VSB
3.3V VccSUSHDA 32mA Icc(Max)=0.375A(wake)
3.3V VCC3_3 308mA Icc(Max)=0.02A(no wake)

3.3V
3.3V VccGLAN3_3 1mA
3.3V VccHDA 32mA

Boazman GbE Lan

A A
3.3V STBY
IO LED 15.5mA

BJT
1.5V ANALOG 418.2mA
CK505
Title
1.0V Internal 1.8
Vdd (Core) Power Delivery Map
to 1.0 VR core 3.3V
277.2mA Ivdd(Max)=250mA DWG NO Rev
A01
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1
Sheet 4 of 45
 5 4

Trung Tâm Máy Tính AV

3 2 1

>=99ms

D
PWROK D

>=0ms
FSB_VTT

1D5V_ICH

1D05V_ICH&
Other Power

3D3V_SYS
C
>=0ms C

>=0ms
5V_SYS

LAN_RSET,
ICH_RSMRSTJ
>=0ms
1D1V_MCH_CL >=10ms

>=0ms
3D3V_SB
B B

5V_SB_SYS >=0ms

RTCRSTJ

VCCRTC >=18ms

A A

Title

Platform Sequence
DWG NO Rev
A01
Arrowhead

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Sheet 5 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

ICH10
D D

SIO SCH5524
SMBus Host
Controller Bus Switch

SMBus Slave
Controller

C
SMBus RESUME C

SMBus MAIN

XDP
Clock Gen.

B B
SLOT 1 (PCI-E *16)

SLOT 2 (PCI-E *1)

SLOT 3 (PCI SLOT)

SLOT 4 (PCI SLOT)

DIMM 1

DIMM 3

DIMM 2

DIMM 4

A A

Title

SM BUS
DWG NO Rev
A01
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Sheet 6 of 45
 5

3D3V_SB
4

Trung Tâm Máy Tính AV 3 2

CK_33M_PCI1
CK_48M_ICH
CK_33M_PCI0
CK_33M_PCI2
1

3D3V_CLK CK_33M_SIO
Stuff for AMT CK_33M_ICH
CK_33M_TPM
CK_14M_SIO
CK_14M_ICH
CK_14M_TPM

CLKVDD1 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy

S
C285 C22 C30 C23 C24 C25 C26 C27 C143 C517
* * * * * * * * * *

*
R631 10K G FDN340P 10pF 10pF 10pF 10pF 10pF 10pF 10pF 10pF 10pF 10pF
19,20,23,38 SLP_M

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

50V, NPO, +/-5%

C583 Q62 FB11 C582 C11 C13 C15
D * 4.7uF * 4.7uF * 0.1uF * 0.1uF * 0.1uF
D

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

c0805h14
*

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

FB 100 Ohm

Reserved for EMI Caps

close to pin 9 close to pin 16,39

U1

** ** **
46 CK_P_CPU_R 33 R31
16 CPUT0 45 CK_P_CPU 10
CLKVDD1 CK_N_CPU_R 33 R29
9 VDD_PLL3 CPUC0 CK_N_CPU 10
FB13 2 VDD_48MHZ 43 CK_P_GMCH_R 33 R27
53 VDD_PCI CPUT1 42 CK_P_GMCH 12
CLKVDD2 CK_N_GMCH_R 33 R25
31 VDD_REF CPUC1 CK_N_GMCH 12
CLKVDD2
* 3D3V_CLK_IO 47 VDD_SRC
VDD_CPU SRCT8/CPU_ITPT
39 CK_XDP_P_SRC8_R 33 R26
CK_XDP_P 10
38 CK_XDP_N_SRC8_R 33 R28
12 SRCC8/CPU_ITPC CK_XDP_N 10
EC9 FB 100 Ohm
VDD_IO
* 470uF
+/-20% C94 C584 C16 C17 C14
20
26 VDD_PLL3_IO
* * * * *

**
0.1uF 4.7uF 0.1uF 0.1uF 0.1uF 37 VDD_SRC_IO_1 13 CK_96M_P_GMCH_R R41 33
VDD_SRC_IO_2 DOT96T/SRCT0 CK_96M_P_GMCH 12
16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

c0805h14 14 CK_96M_N_GMCH_R R40 33
6.3V, X5R, +/-10% DOT96C/SRCC0 CK_96M_N_GMCH 12
41 17
VDD_CPU_IO SRCT1/SE1 18

IDTCV184-2APAG8
SRCC1/SE2

** ** **
V_OUT 40 21 CK_SATA_100M_P_ICH_R R37 33
IO_VOUT SATAT/SRCT2 22 CK_SATA_100M_N_ICH_R CK_SATA_100M_P_ICH 24
R36 33
SATAC/SRCC2 CK_SATA_100M_N_ICH 24
close to pin 55 close to pin 61 close to pin 2 24 CK_DMI_P_ICH_R R19 33
SRCT3/CR#_C 25 CK_DMI_N_ICH_R CK_DMI_P_ICH 23
R18 33
C OSC_CK14M_XTAL_OUT 52 SRCC3/CR#_D CK_DMI_N_ICH 23 C
3D3V_CLK XTAL_IN
27 CK_DMI_P_GMCH_R R23 33
X1 SRCT4 28 CK_DMI_N_GMCH_R R24 33 CK_DMI_P_GMCH 12
XTAL-14.318MHz SRCC4 CK_DMI_N_GMCH 12

*
R630 1 2 R629 0 OSC_CK14M_XTAL_IN 51
XTAL_OUT
15

** ** **
R692 30 CK_PCI_STOP_R R30 1K
+/-5% PCI_STOP#/SRCT5 CK_PCI_STOP 23
C19 C20 29 CK_CPU_STOP_R R32 1K
* 0 * 27pF * 27pF CPU_STOP#/SRCC5 CK_CPU_STOP 23
C

**
Q1 +/-5% 50V, NPO, +/-5% 50V, NPO, +/-5% R7 1K 48 33 CK_PE_100M_P_16PORT_R R38 33
23 CK_PWRGD
*

V_OUT B MMBT3904 49 CKPWRGD/PD# SRCT6 32 CK_PE_100M_N_16PORT_R CK_PE_100M_P_16PORT 22

R20 33 Dummy 3D3V_CLK_R 10,12 FSBSEL1
R8 1K
FSB/TEST_MODE SRCC6
R39 33
CK_PE_100M_N_16PORT 22
sot23_bech11

**
R663 0 56 36 CK_REFSSCLK_P_GMCH_R R21 33
E

29,34 SMB_CLK_MAIN 55 SCL SRCT7/CR#_F 35 CK_REFSSCLK_P_GMCH 12

C581 3D3V_CLK_R R668 0 CK_REFSSCLK_N_GMCH_R R22 33
100pF * 29,34 SMB_DATA_MAIN SDA SRCC7/CR#_E CK_REFSSCLK_N_GMCH 12
50V, NPO, +/-5% EC1

*** **** *****

* 100uF dummy 6 CK_PIN6 R9 33Dummy

**
16V, +/-20% R644 0 PCI4/SRC5_EN 5 CK_PIN5 R60 33 CK_33M_PCI2 31
16,17,22,23,29,31 SMB_CLK_RESUME PCI3/CFGP 4 CK_33M_PCI1 31
dummy R646 0 CK_PIN4 R6 33Dummy CK_33M_PCI0
16,17,22,23,29,31 SMB_DATA_RESUME PCI2/TME 3 CK_33M_PCI0
dummy CK_PIN3 R543 22
15 PCI1/CR#_B 1 CK_PIN1 R44 33 CK_33M_TPM 34
19 VSS_IO PCI0/CR#_A CK_33M_SIO 29
11 VSS_PLL3 R13 1K CK_FSBSEL0
44 VSS_48MHZ 7 CK_PIN7 R5 33
8 VSS_CPU PCIF5/ITP_EN 10 R12 33 CK_33M_ICH 25
50 VSS_PCI USB_48/FSA 54 CK_FSBSEL2 CK_48M_ICH 23
3D3V_CLK_R VSS_REF REF/FSC/TEST_SEL
R3 1K
23
FB1 34 VSS_SRC1
VSS_SRC2 dummy CK_14M_SIOR R14 15 +/-5%
3D3V_CLK_IO C509 CK_14M_TPMR R33 15 +/-5% Dummy POP7 CK_14M_SIO 29
* IDTCV184-2APAG8 * 10pF CK_14M_ICHR R4 15 +/-5% CK_14M_TPM
CK_14M_ICH
34
23

50V, NPO, +/-5%

FB 100 Ohm 3D3V_SYS 3D3V_CLK 3D3V_CLK
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
* 10uF * 10uF * 10uF * 10uF * 0.1uF * 0.1uF * 0.1uF * 0.1uF * 0.1uF * 0.1uF
16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

6.3V, X5R, +/-20%

6.3V, X5R, +/-20%

6.3V, X5R, +/-20%

6.3V, X5R, +/-20%

B B

*R48 *R45 *R47 *R46

10K 10K 10K 10K
dummy
CK_PIN7 CK_PIN5

CK_PIN6 CK_PIN4

*R58 *R53 *R57 *R54

10K
dummy 10K 10K 10K
dummy

PIN NAME NET Strapping description

3D3V_CLK 1 Overclocking DISABLED DEFAULT
PCI2/TME CK_PIN4
(PIN4) 0 Overclocking ENABLED
*

R560 0 CK_FSBSEL0 R178 0 CK_FSBSEL2

10,12 FSBSEL0 10,12 FSBSEL2
dummy dummy 1 CGF TABLE ENABLED
PCI3/CFGP CK_PIN5
R557
R558 * 2.2K (PIN5) 0 CGF TABLE DISABLED
2.2K
* +/-5% +/-5% *R49 *R50 1 SRC5
47K 47K PCI4/SRC5_EN CK_PIN6
CK_14M_ICHR (PIN6) 0 CPU_STOP# and PCI_STOP# DEFAULT
3D3V_CLK
3D3V_CLK 1 CPU_ITP DEFAULT
PCI_F5/ITP_EN CK_PIN7
1

MMDT5551 MMDT5551
CK_48M_ICH
(PIN7) 0 SRC8
A A
*R559 R55 R56
1K Q3039 *R177 Q3038 33K 33K
1K 3D3V_CLK 3D3V_CLK
6

Host Clock FSA FSB FSC

Frequency *R535 *R606
10K 10K Title
Dummy Dummy
266 MHz 0 0 0 CK_PCI_STOP_R CK505 ClockGen
CK_CPU_STOP_R
DWG NO Rev
200 MHz 0 1 0 A01
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1
Sheet 7 of 45
 5

RN91
VTT_OUT_RIGHT

680 +/-5%
4

TTSNS
Trung Tâm Máy Tính AV 3

12V_VRM_IN

12V_VRM
2 1

10
10
P_VID7
P_VID1
P_VID7
P_VID1
*1 2 5V_SYS
D1
C470 C347
P_VID6 3 4 * C344 10uF 10uF
10
10
P_VID6
P_VID2
P_VID2 5
7
6
8 * R645 0.1uF
+/-5%
A C R485 2.2 * +/-10% * +/-10%
0 16V, X7R +/-5%
+/-5% Dummy 2.7K C435
*

D
RN92 680 +/-5% R681 PROCHOTJ 10,24,29 1N4148W 6.8nF C12
P_VID3
*1 AGND Dummy 25V, X7R
* 0.1uF Q4

C
10 P_VID3 2
P_VID0 Dummy 25V, X7R, +/-10%
10 P_VID0 3 4
P_VID5 VRHOT R116 130 B Q73 G VCCP
10 P_VID5 5 6

*
P_VID4 +/-1% MMBT3904 PU1 R320 IPD090N03L G L1
10 P_VID4 7 8 12V_VRM 1 8
sot23_bech11 R662 2.2 10K Choke 410nH
*R556 Dummy

S
**
VTT_OUT_RIGHT PSI R523 1K +/-1% Dummy PWM1 2 BST DRVH 7 +/-5% 2 1
10 PSI 3 IN SW 6

*
P_VR_EN R586 200 47K 100K OD#
10 P_VR_EN *T

*
D OD# PGND D
+/-1% RT1 4 5
*R584

D
VCC DRVL 1
X02 update

D
R532 Dummy R659 1 +/-1% ADP3120AJRZ-RL Q41 +/-1%
* 1K
G
Q40
1
CP2
2 * R522
+/-1% C349 10
C381 IPD060N03LGG 1nF +/-1%
10 P_VR_EN * 1uF *
IPD060N03L G 50V, X7R, +/-10%
COPPER

S
*
P_VRM_GD R597 680 16V, X7R, +/-10%

S
+/-1%
C405
D3012
0.1uF
*

*
16V, X7R, +/-10% R651 680 C A 12V_VRM PHASE1
*

P_VID0
P_VID1
P_VID2
P_VID3
P_VID4
P_VID5
P_VID6
P_VID7
C485 +/-1% Stuff for 95W CPU ( modified 1117) CSREF
C445 C2223

PSI
0.1uF 10,23 P_VRM_GD 1N4148W
1uF R502 10uF
16V, X7R
R582
* 10 * 16V, X7R, *0 * +/-10%
+/-5% C402 +/-5% 12V_VRM_IN

*
1nF
* 50V, X7R, +/-10% R603 10K
Dummy AGND AGND +/-1% Dummy AGND 12V_VRM

D13
AGND

41
40
39
38
37
36
35
34
33
32
31
AGND AGND A C R526 2.2 C471 C192
10 P_VSS_SENSE
+/-5% 10uF 10uF
Reserved For Fairchild
* *

VCC
GND2
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

D
C337 680pF C444 C370 +/-10% +/-10%
*
*

1 30 PWM1 1N4148W 6.8nF 0.1uF Q9

50V, X7R, +/-10% C442 22pF 2 EN PWM1 29 PWM2 25V, X7R * 25V, X7R, +/-10%
*

50V, NPO, +/-5% FBRTN 3 PWRGD PWM2 28 PWM3 Dummy G VCCP

4 FBRTN PWM3 27

*
FB U16 Reserved For ADP3192A PU2 R325 IPD090N03L G L2

***
R605 COMP 5 FB NC2 26 R677 0 +/-5% ODN# 12V_VRM 1 8 R491 2.2 10K Choke 410nH

S
*

R525 1.21KOhm C288 220pF 35.7K 6 COMP ADP3293JCPZ-RL ODN# 25 R658 0 +/-5% PHASE1 PWM2 2 BST DRVH 7 +/-5% 2 1
10 P_VCC_SENSE
*

7 SS SW1 24 3 IN SW 6

*
+/-1% 50V, NPO, +/-5%
+/-1% R554 0 +/-5% PHASE2 ODN#

*
8 DELAY SW2 23 R520 1K+/-1% PHASE3 4 OD# PGND 5
*R52

D
VRHOT 9 TRDET SW3 22 PHASE4 VCC DRVL 1

CSCOMP
TTSNS 10 VRHOT NC1 21 VRM_IMON

CSSUM
R550 C191 C443 R553 1 +/-1% Q5 Q57 +/-1%

CSREF
TTSNS IMON ADP3120AJRZ-RL CP3

RAMP
LLINE
*

GND1
VCCP 4.7nF 22nF R604
* * *R529

IREF
10
*

OD#
ILIM
3

G G 1 2

RT
+/-5% 50V, X7R 50V, X7R 0 C162 10
C VCCP R599 Q49 +/-5% C408 IPD060N03L G IPD060N03L G 1nF +/-1% C
* 0 R647 BAT54C
X02 update
modified on 1117 from R661 R493 R524 Dummy
* 1uF * 50V, X7R, +/-10%
COPPER
* * * *

S
11
12
13
14
15
16
17
18
19
20
+/-5% 45.3K 90.9K 90.9K 90.9K 16V, X7R, +/-10%
Dummy +/-1%
5.49k to 7.5k for 95W CPU +/-1% +/-1% +/-1%
Dummy AGND
2

AGND AGND C590

*
100pF R531 PHASE2
Reserved For Fairchild
Reserved For ADP3192A * 50V, NPO 7.5K *R601
0
R527
+/-1%
100KOhm Reserved For Fairchild Stuff for 95W CPU ( modified 1117)
CSREF
Dummy +/-1% +/-5% AGND
*

R495 1.8KOhm
+/-1% OD#

Reserved For ADP3192A

R678 AGND *R6020 *R486
RT
AGND
12V_VRM
12V_VRM_IN

0 Dummy +/-5%
*

+/-5%R726 Reserved Dummy 180K

C190 D2 71.5KDummy
For +/-1% * C364 C372
D4
*

120pF C A RT R521 4.7nF 820pF C472 C439

CP1 * 50V,NPO,+/-5% Fairchild AGND 604KOhm * 50V, X7R * A C R59 2.2
* 10uF
* 10uF
1 2 +/-1% R583 61.9K +/-5% C406 +/-10% +/-10%

D
*

*
1N4148W AGND R537 71.5K C438 0.1uF
COPPER AGND
Dummy +/-1% 12V_VRM 50V,NPO,+/-5%
+/-1% +/-1% 1N4148W * 6.8nF * 25V, X7R, +/-10% Q7
AGND C334 RT2 25V, X7R

*
G
*R721 * 10nF 100K +/-1% Dummy VCCP

*
6.04K 25V, X7R C195 PU3 R341 IPD090N03L G L25
+/-1% * R614
* 2.2nF 12V_VRM 1 8 R643 2.2 10K Choke 410nH

S
Dummy R518
* 50V, X7R, +/-10% PWM3 2 BST DRVH 7 +/-5% 2 1
0 IN SW
3 6

*
1K dummy ODN#
+/-5%

D
*

*
VRM_IMON AGND +/-1% 4 OD# PGND 5
0 R717 0 R718 VCC DRVL Q8 Q21 *R534
1
+/-5% +/-5%
*R722 R660 1 +/-1% ADP3120AJRZ-RL +/-1%
C

G G CP4
R528 C371 100 12V_VRM_IN
D3 * 6.04K * 0.1uF +/-5% IPD060N03L G IPD060N03L G C369 1 2 *R533
10
+/-1% 16V, X7R Dummy 1nF +/-1%
MMSZ2V4T1
*

S
C437 50V, X7R, +/-10%
COPPER
Q71
1uF
*
A

FBRTN 6 1 CSREF 16V, X7R, +/-10%

B Reserved For ADP3192A B
Dummy 2 P_PSI_A C343
5 PHASE3
R670 * 1nF
50V, X7R 5V_SYS
Stuff for 95W CPU ( modified 1117)
CSREF
C98 C591 4 3 ODN# OD#
1

10nF 150pF VCCP

25V, X7R, +/-10% * Reserved For 50V, NPO, +/-5% * MMDT5551
5.1KOhm Dummy
R3905
Dummy ADP3192A Dummy +/-1% AGND 5.1KOhm R78
2

AGND Dummy 9,10,12,29,34 HCPURSTJ +/-1%

* 1K

1
C468
Reserved For ADP3192A RC delay to turn the
switch on only after
* 10uF
Voltage translation
required for the switch

3
2
12V_VRM 50msec after RESET# is
Input LC circuit 12V_VRM_IN
* C346
22uF * C363
22uF * C338
22uF high.
Q3036

MMDT5551
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 5V_SYS
L24 2 1 Choke 500nH R74 *
*

12VPOWER 1K

4
C440 EC43 EC44 EC42 EC40 VTT_OUT_RIGHT
4 3
* 0.1uF
16V, X7R, +/-10%
* 470uF
+/-20%
* 470uF
+/-20%
* 470uF
+/-20%
* 470uF
+/-20%
* R71
1K
2 1 Dummy Dummy C193 C441 C198
* 22uF * 22uF * 22uF R331
*
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 1K
Header_2x2 5V_SYS
Dummy U3520

3
PSI R730 0 1 IO

**
+/-5% VCC 5
Output Ecap * C367
22uF * C434
22uF * C340
22uF
P_PSI_A R731
+/-5%
0
*
R675
0 * C459 Q3035
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% Dummy +/-5% 0.1uF MMDT5551

4
VCCP dummy 16V, X7R
VCCP 2 OI

*
10 P_PSI_N C 4 R61 1K
HCPURSTJ 9,10,12,29,34

EC55 EC41 EC10 EC45 EC48 TC1 C335 C403 C194 3

* 820uF * 820uF * 820uF * 820uF * 820uF * 100uF * 22uF * 22uF * 22uF
Stuffing option to
connect PSI# directly
GND
A +/-20% +/-20% +/-20% +/-20% +/-20% 2V,+30/-20% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 74V1G66CTR A
Dummy Dummy Dummy Dummy from processor to VR;
Leave EMPTY as default R675
12V_VRM_IN

VCCP
C197 C373 C342
Stuff for 95W CPU ( modified 1117) * 22uF * 22uF * 22uF
Information From Intel MOW42
C196 C436 C341 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10%
0.1uF 0.1uF 0.1uF
* 16V, X7R, +/-10% * 16V, X7R, +/-10% * 16V, X7R, +/-10% Title
EC12 EC11 EC54 EC13 EC14
* 820uF * 820uF * 820uF * 820uF * 820uF VRD11.1 ADP3290
+/-20% +/-20% +/-20% +/-20% +/-20%
Dummy
* C345
22uF * C287
22uF * C423
22uF
DWG NO Rev
A01
6.3V, X5R, +/-10% 6.3V, X5R, +/-10% 6.3V, X5R, +/-10% Arrowhead

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Sheet 8 of 45
 5 4

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HDJ[63..0] HAJ[35..3]
HDJ[63..0] 12 12 HAJ[35..3]
CPUA 1 OF 7
HAJ3 L5 D2
HAJ4 P6 A03# ADS# C2 HADSJ 12
HAJ5 M5 A04# BNR# D4 HBNRJ 12
CPUB 2 OF 7 HAJ6 L4 A05# HIT# H4 TP_CPU_H4 HITJ 12
M4 A06# FC35 G8 TP1
HAJ7
D A07# BPRI# HBPRIJ 12 D
HDJ0 B4 G16 HDJ32 HAJ8 R4 B2
HDJ1 C5 D00# D32# E15 HDJ33 HAJ9 T5 A08# DBSY# C1 HDBSYJ 12
HDJ2 A4 D01# D33# E16 HDJ34 HAJ10 U6 A09# DRDY# E4 HDRDYJ 12
HDJ3 C6 D02# D34# G18 HDJ35 HAJ11 T4 A10# HITM# AB2 HITMJ 12
HDJ4 A5 D03# D35# G17 HDJ36 HAJ12 U5 A11# IERR# P3 HIERRJ 10
HDJ5 B6 D04# D36# F17 HDJ37 HAJ13 U4 A12# INIT# C3 INITJ 24
HDJ6 B7 D05# D37# F18 HDJ38 HAJ14 V5 A13# LOCK# E3 HLOCKJ 12
HDJ7 A7 D06# D38# E18 HDJ39 HAJ15 V4 A14# TRDY# AD3 TP_CPU_AD3 HTRDYJ 12
A10 D07# D39# E19 W5 A15# FC36 G7 TP2
HDJ8 HDJ40 HAJ16
HDJ9 A11 D08# D40# F20 HDJ41 TP_CPU_N4 N4 A16# DEFER# AB3 TP_CPU_AB3 HDEFERJ 12
B10 D09# D41# E21 TP58 P5 RSVD1 FC37 U2 TP3
HDJ10 HDJ42 TP_CPU_P5 TP_CPU_U2
C11 D10# D42# F21 12 HREQJ[4..0] TP59 K4 RSVD2 FC29 U3 TP4
HDJ11 HDJ43 HREQJ0 TP_CPU_U3
D8 D11# D43# G21 J5 REQ0# FC30 TP5
HDJ12 HDJ44 HREQJ1
HDJ13 B12 D12# D44# E22 HDJ45 HREQJ2 M6 REQ1# F3 HBR0J
HDJ14 C12 D13# D45# D22 HDJ46 HREQJ3 K6 REQ2# BR0# G1 BPMB0J HBR0J 10,12
HDJ15 D11 D14# D46# G22 HDJ47 HREQJ4 J6 REQ3# BPMB0# C9 BPMB1J BPMB0J 10
A8 D15# D47# D19 HAJ[35..3] R6 REQ4# BPMB1# G4 BPMB2J BPMB1J 10
12 HDBIJ0 C8 DBI0# DBI2# G20 HDBIJ2 12 12 HAJ[35..3] 12 HADSTBJ0 ADSTB0# BPMB2# G3 BPMB2J 10
BPMB3J
12 HDSTBNJ0 B9 DSTBN0# DSTBN2# G19 HDSTBNJ2 12 BPMB3# H5 BPMB3J 10
TESTHI_10
12 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 12 AB6 TESTHI_10 TESTHI_10 10
HAJ17
HDJ16 G9 D20 HDJ48 HAJ18 W6 A17# J16 TP_CPU_J16
F8 D16# D48# D17 Y6 A18# FC31 H15 TP6
HDJ17 HDJ49 HAJ19 TP_CPU_H15
F9 D17# D49# A14 Y4 A19# FC32 H16 TP7
HDJ18 HDJ50 HAJ20 TP_CPU_H16
E9 D18# D50# C15 AA4 A20# FC33 J17 TP8
HDJ19 HDJ51 HAJ21 TP_CPU_J17
D7 D19# D51# C14 AD6 A21# FC34 TP9
HDJ20 HDJ52 HAJ22
HDJ21 E10 D20# D52# B15 HDJ53 HAJ23 AA5 A22# H1 CPU_GTLREF0
HDJ22 D10 D21# D53# C18 HDJ54 HAJ24 AB5 A23# GTLREF0 H2 CPU_GTLREF1
HDJ23 F11 D22# D54# B16 HDJ55 HAJ25 AC5 A24# GTLREF1 F2 CPU_GTLREF2
HDJ24 F12 D23# D55# A17 HDJ56 HAJ26 AB4 A25# GTLREF2 G10 CPU_GTLREF3
HDJ25 D13 D24# D56# B18 HDJ57 HAJ27 AF5 A26# GTLREF3
HDJ26 E13 D25# D57# C21 HDJ58 HAJ28 AF4 A27# E24 TP_CPU_E24
G13 D26# D58# B21 AG6 A28# FC10 H29 TP47
HDJ27 HDJ59 HAJ29 TP_CPU_H29
F14 D27# D59# B19 AG4 A29# FC15 TP62
HDJ28 HDJ60 HAJ30
HDJ29 G14 D28# D60# A19 HDJ61 HAJ31 AG5 A30#
HDJ30 F15 D29# D61# A22 HDJ62 HAJ32 AH4 A31# G23
HDJ31 G15 D30# D62# B22 HDJ63 HAJ33 AH5 A32# RESET# HCPURSTJ 8,10,12,29,34
G11 D31# D63# C20 HAJ34 AJ5 A33# B3
12 HDBIJ1 G12 DBI1# DBI3# A16 HDBIJ3 12 AJ6 A34# RS0# F5 HRSJ0 12
C HAJ35 C
12 HDSTBNJ1 E12 DSTBN1# DSTBN3# C17 HDSTBNJ3 12 A35# RS1# HRSJ1 12
TP_CPU_AC4 AC4 A3
12 HDSTBPJ1 DSTBP1# DSTBP3# HDSTBPJ3 12 TP60 RSVD3 RS2# HRSJ2 12
TP_CPU_AE4 AE4
TP61 AD5 RSVD4
12 HADSTBJ1 ADSTB1#
CPU Socket_PGA775
cpu_lga775h67-1 CPU Socket_PGA775
cpu_lga775h67-1

VTT_OUT_RIGHT VTT_OUT_RIGHT

GTLREF voltage should be 0.67*VTT

R114
* 57.6
+/-1%
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin *R123
49.9
+/-1%
Intel CRB used 50 Ohm Reserved for CPU_GTLREF Adjusting
0.22nF caps should be placed near CPU pin
place series resistor as close to divider
12V_SYS
*

*
CPU_GTLREF0_DIVIDER R115 10 CPU_GTLREF0 R122 10 CPU_GTLREF1

*
CPU_GTLREF1_DIVIDER R333 0 CPU_GTLREF1_DIVIDER

C34 *R136
4.7K

D
1uF
* 10V, X5R, +/-10% *R120
100
+/-1%
* C38
220pF
50V, NPO, +/-5% *
C39
1uF
10V, X5R, +/-10%
*R121
100
+/-1%
* C40
220pF
50V, NPO, +/-5%
+/-5%
Q32

dummy dummy G
2N7002-7-F

S
B
R680 B
R232 R233 576
* 0 * 0 +/-1%
dummy

FSB_VTT VTT_OUT_LEFT
Q72

* *
R118 1K 6 1
R359 23 CPU_GTLREF_CTRL1
* 57.6 *R362
57.6
5
2
+/-1% +/-1% R199 1K
dummy 23 CPU_GTLREF_CTRL2
4 3
12V_SYS
*

CPU_GTLREF3_DIVIDER R358 10 CPU_GTLREF3 CPU_GTLREF2_DIVIDER R361 10 CPU_GTLREF2

MMDT5551
dummy
*R206

D
C41 C43 4.7K
1uF
* 10V, X5R, +/-10% *R124
100 * C42
220pF * 1uF
10V, X5R, +/-10% * R360 * C44
220pF
+/-5%

G
Q35

+/-1% 50V, NPO, +/-5% dummy 100 50V, NPO, +/-5%

dummy dummy dummy 2N7002-7-F

S
R682
1.3KOhm
+/-1%

CPU_GTLREF_CTRL1 CPU_GTLREF_CTRL2
GP60 GP18 / 20 GTLREF
A A

0 0 0.615 x Vtt
0 1 0.63 x Vtt Default Value

1 0 0.65 x Vtt
Title
1 1 0.67 x Vtt LGA775 -1
DWG NO Rev
A01
Arrowhead

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Sheet 9 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

CPUC 3 OF 7
P2 F26 TESTHI_0
24 SMIJ K3 SMI# TESTHI_0 W3 TESTHI_1 If not used, pull up through 51 to 1k ohm
24 A20MJ R3 A20M# TESTHI_1 F25 to vtt_out_right or ground respectively,i.e
24 FERRJ K1 FERR#/PBE# TESTHI_2 G25 reserved the termination circuit
24 INTR L1 LINT0 TESTHI_3 G27 FSB_VTT
24 NMI N2 LINT1 TESTHI_4 G26 CPUD 4 OF 7
24 IGNNEJ M3 IGNNE# TESTHI_5 G24 AE1 A29
HTCK
24 STPCLKJ STPCLK# TESTHI_6 F24 34 HTCK AD1 TCK VTT1 B25
TESTHI_2_7 HTDI
HVCCA A23 TESTHI_7 AK6 FORCEPHJ 34 HTDI HTDO AF1 TDI VTT2 B29
HVSSA B23 VCCA FC8 P1 34 HTDO HTMS AC1 TDO VTT3 B30
C23 VSSA DPSLP# L2 DPSLP# 23,29 34 HTMS AG1 TMS VTT4 C29
HVCCIOPLL HTRSTJ
D
D23 VCCIOPLL SLP# W2 PM_SLP 12,29 34 HTRSTJ TRST# VTT5 A26
D
HVCCPLL
VCC_PLL TDI_M
TDO_M
U1 TESTHI_M
HBPM0J AJ2
VTT6
VTT7
B27
C28
* R640
34 HBPM0J 0
AM2 N1 HBPM1J AJ1 BPM0# VTT8 A25
8 P_VID0 AL5 VID0 PWRGOOD AL2 CPU_PWRG 23 34 HBPM1J AD2 BPM1# VTT9 A28
PROCHOTJ HBPM2J
8 P_VID1

*
AM3 VID1 PROCHOT# M2 H_THERMTRIPJ R639 0 PROCHOTJ 8,24,29 34 HBPM2J HBPM3J AG2 BPM2# VTT10 A27
8 P_VID2 AL6 VID2 THERMTRIP# THERMTRIPJ 24 34 HBPM3J AF2 BPM3# VTT11 C30
HBPM4J TPEC_VCC
8 P_VID3 AK4 VID3 A13 34 HBPM4J AG3 BPM4# VTT12 A30
HCOMP0 HBPM5J
8 P_VID4 AL4 VID4 COMP0 T1 34 HBPM5J BPM5# VTT13 C25
HCOMP1 Dummy
8 P_VID5 AM5 VID5 COMP1 G2 AC2 VTT14 C26
HCOMP2 stuff for proto FP_RSTJ
8 P_VID6 AM7 VID6 COMP2 R1 23,34,37 FP_RSTJ DBR# VTT15 C27
HCOMP3
8 P_VID7

**
VID_SELECT AN7 VID7 COMP3 J2 HCOMP4 R231 0 AK3 VTT16 B26
VID_SELECT FC3 T2 34 CPU_CK_XDP_P AJ3 ITPCLK0 VTT17 D27
PM_DPRSTP# R299 0
F28 DPRSTP# Y3 PM_DPRSTP# 12,23 34 CPU_CK_XDP_N ITPCLK1 VTT18 D28
P_PSI_N Dummy
7 CK_P_CPU G28 BCLK0 FC17 AE3 P_PSI_N 8 G29 VTT19 D25
HCOMP7 Place as colse to cpu
7 CK_N_CPU BCLK1 FC18 B13 7,12 FSBSEL0 H30 BSEL0 VTT20 D26
HCOMP8
AE8 COMP8 socket as possible 7,12 FSBSEL1 G30 BSEL1 VTT21 B28
23,29 CPU_SKTOCC# SKTOCC# 7,12 FSBSEL2 BSEL2 VTT22 D29
G5 CK_XDP_N VTT23 D30 VTT_OUT_RIGHT VTT_OUT_LEFT
24,29 PECI PECI F29 7 CK_XDP_N VTT24 AM6
TP_CPU_F29 CK_XDP_P
RSVD5 G6 TP64 7 CK_XDP_P FC40 P_VRM_GD 8,23
TP_CPU_G6
AL1 RSVD6 AH2 TP65 AA1
THERMDA_NC TP_CPU_AH2 VTT_OUT_RIGHT
TP103 AK1 THERMDA RSVD7 N5 TP66 VTT_OUT_RIGHT J1
THERMDC_NC TP_CPU_N5 VTT_OUT_LEFT
TP104 THERMDC RSVD8 AE6 TP67 VTT_OUT_LEFT F27
TP_CPU_AE6 VTT_SEL
RSVD9 D16 TP68 FSB_VTT VTT_SEL VTT_SEL 19
TP_CPU_D16
TP69
**

R63 0 dummy AN3 RSVD10 A20 TP_CPU_A20 C18 C31 C33

8 P_VCC_SENSE
8 P_VSS_SENSE
R64 0 dummy AN4 VCC_SENSE RSVD11 E23 TP_CPU_E23
TP70
TP71
CPU Socket_PGA775 VTT_SEL VTT * 0.1uF * 0.1uF * 0.1uF

***
VSS_SENSE RSVD12

16V, X7R, +/-10%

16V, X7R, +/-10%

AN5 F23 TP_CPU_F23 R683 470 FSBSEL0 cpu_lga775h67-1 No Connect 1.2V 16V, X7R, +/-10%
AN6 VCC_MB_REG RSVD13 V2 TP72
TP_CPU_V2 1.2V 1.2V dummy
AL8 VSS_MB_REG RSVD14 E7 TP10
TP_CPU_AL8 TP_CPU_E7 R684 470 FSBSEL2 Vss 1.1V
TP77 AL7 VCCP4 RSVD15 D14 TP73
TP_CPU_AL7 TP_CPU_D14
TP78 VSS186 RSVD16 E6 TP74
TP_CPU_E6 R685 470 FSBSEL1
RSVD17 D1 TP75
TP_CPU_D1
AL3 RSVD18 TP76
TP_CPU_AL3
TP79 VRDSEL
AA2 TP_CPU_AA2
V1 FC39 E29 TP11
MS_ID1 TP_CPU_E29
W1 MSID1 FC26 TP63
C MS_ID0 C

****
MSID0 A24 TP_CPU_A24 R66 1K dummy
FC23 J3 TP_CPU_J3 R130 1K dummy
CPU_BOOT Y1 FC22 F6 TP_CPU_F6 R357 51
BOOTSELECT FC21 E5 TP_CPU_E5 R119 1K dummy
FC20
*R65
51
VTT_OUT_RIGHT
CPU Socket_PGA775
cpu_lga775h67-1

X02 update
FSB_VTT

3D3V_SYS R106
*R107
100
+/-1%
*

* *
R90 51 TESTHI_0 1K dummy

*
MS_ID0 R108 0 dummy dummy
P_VR_EN 8

C
R92 51 TESTHI_2_7
1D5V_ICH R2348 B Q6
Dummy
* 220 MMBT3904 *R195
1.5KOhm

*
POP1 MS_ID1 R109 0 sot23_bech11 +/-1%

E
*

R67 0 +/-5% HVCCPLL dummy

dummy X02 update
A

IERR_LED1 VTT_OUT_RIGHT
*R110 *R111
1

C28 C29
10uF * * 10nF Dummy LED_Yellow 3D3V_SYS 51 51

* *
c0805h14 25V, X7R, +/-10% POP1 Q74 R68 62 HIERRJ dummy dummy
2

6 1 HIERRJ 9
10V, Y5V
C

2 *R593 R72 62 HCPURSTJ BOM Note:

*

HIERRJ R588 1K 5 1K HCPURSTJ 8,9,12,29,34

placed near pin D23, within 500 mils POP1 POP1 1.Stuff R108 for 95W YORKFIELD support
4 3 Dummy R82 130 FORCEPHJ 2.Stuff R109 for 65W CONROE/WOLFDALE support
Dummy
+/-1%
3.Empty Q6 for VTT tool test
MMDT5551 R85 130 dummy PROCHOTJ 4.Reserve R110 and R111 for CPU support before CONROE
B B
+/-1%
Dummy
* * *

R179 680 P_PSI_N

R355 49.9 dummy HCOMP7

+/-1%
VTT_OUT_RIGHT
PLL Supply Filter R374 680 VID_SELECT

VTT_OUT_LEFT

******
R88 51 HBPM5J
VTT_OUT_LEFT
R91 51 HBPM4J
FSB_VTT
***********

****
R73 62 R93 51 HBPM3J R94 0 dummy BPMB3J

R75 100 dummy

HBR0J
CPU_PWRG
9,12
R96 51 HBPM2J R97 0 dummy BPMB2J
*R98
51
*R95
51

R76 51 BPMB3J R99 51 HBPM1J R100 0 dummy BPMB1J

BPMB3J 9 BPMB1J 9
* L44
* L43 R77 51 BPMB2J R102 51 HBPM0J R103 0 dummy BPMB0J
BPMB2J 9 BPMB0J 9
10uH@2.52MHz 10uH@2.52MHz
dummy dummy R79 51 TESTHI_10
TESTHI_10 9 Reserve for Kentsfield CPU support
R80 51 dummy DPSLP#

R81 51 TESTHI_M
HVCCIOPLL
R83 51 dummy PM_SLP

HVCCA R101 51 TESTHI_1

R84 49.9 dummy HCOMP4

+/-1%

*
C333 R86 49.9 dummy PM_DPRSTP# VID_SELECT R62 0 dummy
* 22uF +/-1% PSI 8
A 6.3V, X5R, +/-10% A

HVSSA dummy
****

R87 49.9 HCOMP0

+/-1%
R89 49.9 HCOMP1
+/-1%
R104 49.9 HCOMP2
+/-1%
R105 49.9 HCOMP3 Title
+/-1%
R356 24.9 HCOMP8 LGA775 -2
+/-1%
DWG NO Rev
A01
Arrowhead

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1
Sheet 10 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

VCCP VCCP VCCP

CPUE 5 OF 7 CPUF 6 OF 7 CPUG 7 OF 7
AG22 AK12 AF9 AL23
K29 VCCP1 VCCP93 AH22 AF22 VCCP185 VSS41 A12 H22 AE10
AM26 VCCP2 VCCP94 T29 AH11 VCCP186 VSS42 L25 H21 VSS126 VSS201 AF13
AE12 VCCP3 VCCP95 AM14 AJ14 VCCP187 VSS43 J7 H20 VSS127 VSS202 H6
AE11 VCCP5 VCCP96 AM25 AH19 VCCP188 VSS44 AE28 H19 VSS128 VSS203 A18
D VCCP6 VCCP97 VCCP189 VSS45 VSS129 VSS204 D
W23 AE9 AH29 AE29 H18 A2
W24 VCCP7 VCCP98 Y29 AH27 VCCP190 VSS46 K5 AB7 VSS130 VSS205 E2
W25 VCCP8 VCCP99 AK25 AG28 VCCP191 VSS47 J4 H17 VSS131 VSS206 D9
T25 VCCP9 VCCP100 AK19 AL26 VCCP192 VSS48 AE30 AJ24 VSS132 VSS207 C4
Y28 VCCP10 VCCP101 AG15 AM12 VCCP193 VSS49 AN20 AM17 VSS133 VSS208 A6
AL18 VCCP11 VCCP102 J22 J24 VCCP194 VSS50 AF10 AC3 VSS134 VSS209 D6
AC25 VCCP12 VCCP103 T24 J13 VCCP195 VSS51 AE24 H14 VSS135 VSS210 D5
W30 VCCP13 VCCP104 AG21 T28 VCCP196 VSS52 AM24 P28 VSS136 VSS211 A9
Y30 VCCP14 VCCP105 AM21 W28 VCCP197 VSS53 AN23 V6 VSS137 VSS212 D3
AN14 VCCP15 VCCP106 J25 J12 VCCP198 VSS54 H9 AK2 VSS138 VSS213 B1
AD28 VCCP16 VCCP107 U30 J27 VCCP199 VSS55 H8 P27 VSS139 VSS214 B5
Y26 VCCP17 VCCP108 AL21 AG19 VCCP200 VSS56 H13 P26 VSS140 VSS215 B8
AC29 VCCP18 VCCP109 AG25 AL9 VCCP201 VSS57 AC6 AM28 VSS141 VSS216 AJ4
M29 VCCP19 VCCP110 AJ18 AD30 VCCP202 VSS58 AC7 AJ13 VSS142 VSS217 AE26
U24 VCCP20 VCCP111 J19 AF21 VCCP203 VSS59 AH6 W4 VSS143 VSS218 AH1
J23 VCCP21 VCCP112 AH30 Y24 VCCP204 VSS60 C16 P25 VSS144 VSS219 V7
AC27 VCCP22 VCCP113 J15 AK14 VCCP205 VSS61 AM16 AJ20 VSS145 VSS221 C13
AM18 VCCP23 VCCP114 AG12 J9 VCCP206 VSS62 AE25 W7 VSS146 VSS222 AK24
AM19 VCCP24 VCCP115 AJ22 M27 VCCP207 VSS63 AE27 P23 VSS147 VSS223 AB30
AB8 VCCP25 VCCP116 J20 AF14 VCCP208 VSS64 AJ28 AG13 VSS148 VSS224 L6
AC26 VCCP26 VCCP117 AH18 J30 VCCP209 VSS65 AJ7 AG16 VSS149 VSS225 L7
J8 VCCP27 VCCP118 AH26 AG18 VCCP210 VSS66 F19 AG17 VSS150 VSS226 AB29
J28 VCCP28 VCCP119 W27 AA8 VCCP211 VSS67 AH13 C7 VSS151 VSS227 M1
T30 VCCP29 VCCP120 AL25 AG8 VCCP212 VSS68 AD7 Y2 VSS152 VSS228 AB28
AM9 VCCP30 VCCP121 AN8 AL29 VCCP213 VSS69 AH16 L30 VSS153 VSS229 E8
AF15 VCCP31 VCCP122 AH14 AD29 VCCP214 VSS70 AK17 L29 VSS154 VSS230 AG20
AC8 VCCP32 VCCP123 U27 W8 VCCP215 VSS71 E17 D15 VSS155 VSS231 AN17
AE14 VCCP33 VCCP124 T23 AH8 VCCP216 VSS72 AH17 AL27 VSS156 VSS232 AB27
N23 VCCP34 VCCP125 R8 N24 VCCP217 VSS73 AH20 Y7 VSS157 VSS233 AB26
W29 VCCP35 VCCP126 AK22 AN22 VCCP218 VSS74 AE5 L27 VSS158 VSS234 AN16
U29 VCCP36 VCCP127 AN29 J14 VCCP219 VSS75 AH23 AA29 VSS159 VSS235 M7
AC24 VCCP37 VCCP128 AG11 K26 VCCP220 VSS76 AE7 N6 VSS160 VSS236 AB25
AC23 VCCP38 VCCP129 AK26 AF19 VCCP221 VSS77 AM13 N7 VSS161 VSS237 AB24
Y23 VCCP39 VCCP130 J10 N8 VCCP222 VSS78 AH24 AA28 VSS162 VSS238 AB23
AN26 VCCP40 VCCP131 AJ15 AF12 VCCP223 VSS79 AJ30 AN13 VSS163 VSS239 N3
AN25 VCCP41 VCCP132 AG26 M28 VCCP224 VSS80 AJ10 AA27 VSS164 VSS240 AA30
AN11 VCCP42 VCCP133 AN9 AK9 VCCP225 VSS81 AF3 AA26 VSS165 VSS241 F4
C AN18 VCCP43 VCCP134 AH15 VCCP226 VSS82 AK5 P4 VSS166 VSS242 AG10 C
Y27 VCCP44 VCCP135 AF18 VSS83 AJ16 AA25 VSS167 VSS243 AE13
Y25 VCCP45 VCCP136 AL15 VSS84 AF6 AA24 VSS168 VSS244 AF30
AD24 VCCP46 VCCP137 J26 C10 VSS85 AK29 P7 VSS169 VSS245 H28
AE23 VCCP47 VCCP138 J18 D12 VSS1 VSS86 AJ17 E26 VSS170 VSS246 F7
AE22 VCCP48 VCCP139 J21 C24 VSS2 VSS87 F22 V30 VSS171 VSS247 AF29
AN19 VCCP49 VCCP140 AG27 K2 VSS4 VSS88 AH3 R2 VSS172 VSS248 AF28
V8 VCCP50 VCCP141 AK15 C22 VSS5 VSS89 AK10 V29 VSS173 VSS249 AF27
K8 VCCP51 VCCP142 AF11 AN1 VSS6 VSS90 AM10 V28 VSS174 VSS251 AF26
AE21 VCCP52 VCCP143 AD23 B14 VSS7 VSS91 F16 R5 VSS175 VSS252 AF25
AM30 VCCP53 VCCP144 AM15 K7 VSS8 VSS92 AJ23 V27 VSS176 VSS253 AN28
AE19 VCCP54 VCCP145 AF8 AE16 VSS9 VSS93 F13 R7 VSS177 VSS254 AN27
AC30 VCCP55 VCCP146 AK21 B11 VSS10 VSS94 AG7 E20 VSS178 VSS255 AF24
AE15 VCCP56 VCCP147 AG30 AL10 VSS11 VSS95 F10 AN10 VSS179 VSS256 AF23
M30 VCCP57 VCCP148 AJ21 AK23 VSS12 VSS96 L26 V25 VSS180 VSS257 AG24
K27 VCCP58 VCCP149 AM11 H12 VSS13 VSS97 AD4 T3 VSS181 VSS258 AF17
M24 VCCP59 VCCP150 AL11 AF7 VSS14 VSS98 H11 V24 VSS182 VSS259 AN24
AN21 VCCP60 VCCP151 AJ11 AK7 VSS15 VSS99 L24 V23 VSS183 VSS260 H3
T8 VCCP61 VCCP152 K30 H7 VSS16 VSS100 L23 T6 VSS184 VSS261 P24
AC28 VCCP62 VCCP153 AL14 E14 VSS17 VSS101 AM23 E25 VSS185 VSS263 AE20
N25 VCCP63 VCCP154 AN30 L28 VSS18 VSS102 A15 R29 VSS187 VSS264 AE17
AE18 VCCP64 VCCP155 AH25 Y5 VSS19 VSS103 AH10 R28 VSS189 VSS265 E27
W26 VCCP65 VCCP156 AL12 E11 VSS20 VSS104 B24 R27 VSS190 VSS266 T7
AD25 VCCP66 VCCP157 AJ9 AL16 VSS21 VSS106 L3 R26 VSS191 VSS267 R30
M8 VCCP67 VCCP158 AK11 AL24 VSS22 VSS107 H27 R25 VSS192 VSS268 AJ27
N30 VCCP68 VCCP159 AG14 AK13 VSS23 VSS108 A21 U7 VSS193 VSS269 AB1
AD26 VCCP69 VCCP160 N29 D21 VSS24 VSS109 AE2 R24 VSS194 VSS270 AM4
AJ26 VCCP70 VCCP161 AL30 AL20 VSS26 VSS110 AJ29 R23 VSS195 VSS271 V26
AM29 VCCP71 VCCP162 AJ25 D18 VSS27 VSS111 AK27 P30 VSS196 VSS272 AA23
M25 VCCP72 VCCP163 AH9 AN2 VSS28 VSS113 AK28 V3 VSS197 VSS273 AL28
M26 VCCP73 VCCP164 J29 AK16 VSS29 VSS114 B20 P29 VSS198 VSS274 AF20
L8 VCCP74 VCCP165 J11 AK20 VSS30 VSS115 AM20 AF16 VSS199 VSS275 AG23
U25 VCCP75 VCCP166 K25 AM27 VSS31 VSS116 H26 VSS200 VSS276
Y8 VCCP76 VCCP167 P8 AM1 VSS32 VSS117 B17
AJ12 VCCP77 VCCP168 K23 AL13 VSS33 VSS118 H25
AD27 VCCP78 VCCP169 AL19 AL17 VSS34 VSS119 H24
U23 VCCP79 VCCP170 AM8 C19 VSS35 VSS120 AA3
M23 VCCP80 VCCP171 T26 E28 VSS36 VSS121 AA7 CPU Socket_PGA775
B VCCP81 VCCP172 VSS37 VSS122 B
AG29 N28 AH7 H23 cpu_lga775h67-1
N27 VCCP82 VCCP173 AH12 AK30 VSS38 VSS123 AA6
AM22 VCCP83 VCCP174 AL22 D24 VSS39 VSS124 H10
U28 VCCP84 VCCP175 AN15 VSS40 VSS125
K28 VCCP85 VCCP176 AJ8
U8 VCCP86 VCCP177 U26
AK18 VCCP87 VCCP178 AJ19
AD8 VCCP88 VCCP179 T27 CPU Socket_PGA775
K24 VCCP89 VCCP180 AK8 cpu_lga775h67-1
AH28 VCCP90 VCCP181 AN12
AH21 VCCP91 VCCP182 AG9
VCCP92 VCCP183 N26
VCCP184

CPU Socket_PGA775
cpu_lga775h67-1

A A

Title

LGA775 -3
DWG NO Rev
A01
Arrowhead

PDF 文件使用 "pdfFactory Pro" 试用版本创建 www.fineprint.cn

5

www.advancerepairlaptop.blogspot.com
4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 11 of 45
 5

HDJ[63..0]
4

Trung Tâm Máy Tính AV 3 2 1

9 HAJ[35..3] HDJ[63..0] 9
GMCHB 2 OF 10
HAJ3 L36 F44 HDJ0
HAJ4 L37 FSB_AB_3 FSB_DB_0 C44 HDJ1 GMCHE 5 OF 10
HAJ5 J38 FSB_AB_4 FSB_DB_1 D44 HDJ2

**
HAJ6 F40 FSB_AB_5 FSB_DB_2 C41 HDJ3 H_FSBSEL0 F17 D14 HSYNC R125 30
H39 FSB_AB_6 FSB_DB_3 E43 G16 BSEL0 CRT_HSYNC C14 3V_HSYNC 21
HAJ7 HDJ4 H_FSBSEL1 VSYNC R126 30
L38 FSB_AB_7 FSB_DB_4 B43 P15 BSEL1 CRT_VSYNC 3V_VSYNC 21
HAJ8 HDJ5 H_FSBSEL2
HAJ9 L43 FSB_AB_8 FSB_DB_5 D40 HDJ6 TP12 TP_ALLZTEST M20 BSEL2
HAJ10 N39 FSB_AB_9 FSB_DB_6 B42 HDJ7 TP13 TP_XORTEST N17 ALLZTEST B18
N35 FSB_AB_10 FSB_DB_7 B38 K16 XORTEST CRT_RED D18 RED 21
HAJ11 HDJ8 TP_MCH_K16
N37 FSB_AB_11 FSB_DB_8 F38 F15 RSVD_29 CRT_GREEN C18 GREEN 21
HAJ12 HDJ9 EXP_SLR
J41 FSB_AB_12 FSB_DB_9 A38 G15 EXP_SLR CRT_BLUE F13 BLUE 21
HAJ13 HDJ10 GMCHA 1 OF 10 TP48 TP_MCH_G15
HAJ14 N40 FSB_AB_13 FSB_DB_10 B37 HDJ11 EXP_RXP0 F6 C11 EXP_TXP0 EXP_SM H17 RSVD_7 CRT_IRTN R127 R128 R129
D
HAJ15 M45
R35
FSB_AB_14
FSB_AB_15
FSB_DB_11
FSB_DB_12
D38
C37
HDJ12 22
22
EXP_RXP0
EXP_RXN0
EXP_RXN0 G7
H6
PEG_RXP_0
PEG_RXN_0
PEG_TXP_0
PEG_TXN_0
B11
A10
EXP_TXN0
EXP_TXP0
EXP_TXN0
22
22
ITPM_EN L17 EXP_SM
ITPM_ENABLE L15
*150 * 150 *150
D

HAJ16 HDJ13 EXP_RXP1 EXP_TXP1 +/ -1% +/ -1% +/ -1%

VGA
T36 FSB_AB_16 FSB_DB_13 D37 22 EXP_RXP1 G4 PEG_RXP_1 PEG_TXP_1 B9 EXP_TXP1 22 CRT_DDC_DATA M15 DDCA_DATA 21
HAJ17 HDJ14 EXP_RXN1 EXP_TXN1
R36 FSB_AB_17 FSB_DB_14 B36 22 EXP_RXN1 J6 PEG_RXN_1 PEG_TXN_1 C9 EXP_TXN1 22 M17 CRT_DDC_CLK DDCA_CLK 21
HAJ18 HDJ15 EXP_RXP2 EXP_TXP2 TP_MCH_M17
R34 FSB_AB_18 FSB_DB_15 E37 22 EXP_RXP2 J7 PEG_RXP_2 PEG_TXP_2 D8 EXP_TXP2 22 TP54 J17 RSVD_8 B15
HAJ19 HDJ16 EXP_RXN2 EXP_TXN2 TLS DAC_REFSET
R37 FSB_AB_19 FSB_DB_16 J35 22 EXP_RXN2 L6 PEG_RXN_2 PEG_TXN_2 B8 EXP_TXN2 22 G20 CEN DAC_IREF
HAJ20 HDJ17 EXP_RXP3 EXP_TXP3 TP_MCH_G20
R39 FSB_AB_20 FSB_DB_17 H35 22 EXP_RXP3 L7 PEG_RXP_3 PEG_TXP_3 C7 EXP_TXP3 22 TP27 J16 BSCANTEST E15
HAJ21 HDJ18 EXP_RXN3 EXP_TXN3 TP_MCH_J16 CK_96M_P_GMCH
U38 FSB_AB_21 FSB_DB_18 F37 22 EXP_RXN3 N9 PEG_RXN_3 PEG_TXN_3 B7 EXP_TXN3 22 TP26 M16 RSVD_10 DPL_REFCLKINP D15 CK_96M_P_GMCH 7
HAJ22 HDJ19 EXP_RXP4 EXP_TXP4 TP_MCH_M16 CK_96M_N_GMCH
T37 FSB_AB_22 FSB_DB_19 G37 22 EXP_RXP4 N10 PEG_RXP_4 PEG_TXP_4 B6 EXP_TXP4 22 TP51 J15 RSVD_11 DPL_REFCLKINN CK_96M_N_GMCH 7
HAJ23 HDJ20 EXP_RXN4 EXP_TXN4 TP_MCH_J15
U34 FSB_AB_23 FSB_DB_20 J33 22 EXP_RXN4 N7 PEG_RXN_4 PEG_TXN_4 B3 EXP_TXN4 22 J20 RSVD_12 G8
HAJ24 HDJ21 EXP_RXP5 EXP_TXP5 TP_MCH_J20 CK_REFSSCLK_P_GMCH
U40 FSB_AB_24 FSB_DB_21 L33 22 EXP_RXP5 N6 PEG_RXP_5 PEG_TXP_5 B4 EXP_TXP5 22 F20 RSVD_13 DPL_REFSSCLKINP G9 CK_REFSSCLK_P_GMCH 7
HAJ25 HDJ22 EXP_RXN5 EXP_TXN5 TP_MCH_F20 CK_REFSSCLK_N_GMCH
T34 FSB_AB_25 FSB_DB_22 G33 22 EXP_RXN5 R7 PEG_RXN_5 PEG_TXN_5 D2 EXP_TXN5 22 DUALX8_ENABLE DPL_REFSSCLKINN CK_REFSSCLK_N_GMCH 7
HAJ26 HDJ23 EXP_RXP6 EXP_TXP6
Y36 FSB_AB_26 FSB_DB_23 L31 22 EXP_RXP6 R6 PEG_RXP_6 PEG_TXP_6 C2 EXP_TXP6 22
HAJ27 HDJ24 EXP_RXN6 EXP_TXN6
U35 FSB_AB_27 FSB_DB_24 M31 22 EXP_RXN6 R9 PEG_RXN_6 PEG_TXN_6 H2 EXP_TXN6 22
HAJ28 HDJ25 EXP_RXP7 EXP_TXP7
AA35 FSB_AB_28 FSB_DB_25 M30 22 EXP_RXP7 R10 PEG_RXP_7 PEG_TXP_7 G2 EXP_TXP7 22
HAJ29 HDJ26 EXP_RXN7 EXP_TXN7
U37 FSB_AB_29 FSB_DB_26 J30 22 EXP_RXN7 U10 PEG_RXN_7 PEG_TXN_7 J2 EXP_TXN7 22 AY4 AN6
HAJ30 HDJ27 EXP_RXP8 EXP_TXP8 CL_DATA MCH_PLTRSTJ
EXP_TXP8 30 24 CL_DATA MCH_PLTRSTJ 26
FSB

PCIE
HAJ31 Y37 FSB_AB_30 FSB_DB_27 G31 HDJ28 30 EXP_RXP8 EXP_RXN8 U9 PEG_RXP_8 PEG_TXP_8 K2 EXP_TXN8 CL_CLK AY2 CL_DATA RSTINB AR4 PWRGD_3V
Y34 FSB_AB_31 FSB_DB_28 K30 30 EXP_RXN8 U6 PEG_RXN_8 PEG_TXN_8 K1 EXP_TXN8 30 24 CL_CLK CL_CLK PWROK PWRGD_3V 23,29,30
HAJ32 HDJ29 EXP_RXP9 EXP_TXP9 CL_VREF_MCH AN13 K15 ICH_SYNCJ
Y38 FSB_AB_32 FSB_DB_29 M29 30 EXP_RXP9 U7 PEG_RXP_9 PEG_TXP_9 L2 EXP_TXP9 30 AW2 CL_VREF ICH_SYNCB ICH_SYNCJ 23
HAJ33 HDJ30 EXP_RXN9 EXP_TXN9 CL_RST
FSB_AB_33 FSB_DB_30 30 EXP_RXN9 PEG_RXN_9 PEG_TXN_9 EXP_TXN9 30 24 CL_RST CL_RSTB
HAJ34 AA37 G30 HDJ31 EXP_RXP10 AA9 P2 EXP_TXP10 MCH_CLPWROK_R AN8
EXP_TXP10 30

*****
HAJ35 AA36 FSB_AB_34 FSB_DB_31 J29 HDJ32 22 EXP_RXP10 EXP_RXN10 AA10 PEG_RXP_10 PEG_TXP_10 M2 EXP_TXN10 CL_PWROK AU4 HDA_BCLK R349 0
FSB_AB_35 FSB_DB_32 F29 22 EXP_RXN10 R4 PEG_RXN_10 PEG_TXN_10 T2 EXP_TXN10 30 HDA_BCLK AV4
HDJ33 EXP_RXP11 EXP_TXP11 HDA_RSTB R350 0

MISC
FSB_DB_33 H29 22 EXP_RXP11 P4 PEG_RXP_11 PEG_TXP_11 R1 EXP_TXP11 30 HDA_RSTB AU2
HDJ34 EXP_RXN11 EXP_TXN11 HDA_SDI R351 0
9 HREQJ[4..0] G38 FSB_DB_34 L25 22 EXP_RXN11 AA7 PEG_RXN_11 PEG_TXN_11 U2 EXP_TXN11 30 AR7 HDA_SDI AV1
HREQJ0 HDJ35 EXP_RXP12 EXP_TXP12 TP_MCH_AR7 HDA_SDO R352 0
K35 FSB_REQB_0 FSB_DB_35 K26 22 EXP_RXP12 AA6 PEG_RXP_12 PEG_TXP_12 V2 EXP_TXP12 22 TP19 AN10 JTAG_TDI HDA_SDO AU3
HREQJ1 HDJ36 EXP_RXN12 EXP_TXN12 TP_MCH_AN10 HDA_SYNC R353 0
J39 FSB_REQB_1 FSB_DB_36 L29 22 EXP_RXN12 AB10 PEG_RXN_12 PEG_TXN_12 W4 EXP_TXN12 22 TP20 AN11 JTAG_TDO HDA_SYNC
HREQJ2 HDJ37 EXP_RXP13 EXP_TXP13 TP_MCH_AN11
C43 FSB_REQB_2 FSB_DB_37 J26 22 EXP_RXP13 AB9 PEG_RXP_13 PEG_TXP_13 V3 EXP_TXP13 22 TP33 AN9 JTAG_TCK
HREQJ3 HDJ38 EXP_RXN13 EXP_TXN13 TP_MCH_AN9
G39 FSB_REQB_3 FSB_DB_38 M26 22 EXP_RXN13 AB3 PEG_RXN_13 PEG_TXN_13 AA4 EXP_TXN13 22 TP34 JTAG_TMS J11
HREQJ4 HDJ39 EXP_RXP14 EXP_TXP14 DDPC_CTRLCLK
FSB_REQB_4 FSB_DB_39 H26 22 EXP_RXP14 AA2 PEG_RXP_14 PEG_TXP_14 Y4 EXP_TXP14 22 DDPC_CTRLCLK F11 DDPC_CTRLCLK 30
HDJ40 EXP_RXN14 EXP_TXN14 DDPC_CTRLDATA
J40 FSB_DB_40 F25 22 EXP_RXN14 AD10 PEG_RXN_14 PEG_TXN_14 AC1 EXP_TXN14 22 DDPC_CTRLDATA DDPC_CTRLDATA 30
HDJ41 EXP_RXP15 EXP_TXP15
9 HADSTBJ0 T39 FSB_ADSTBB_0 FSB_DB_41 F24 22 EXP_RXP15 AD11 PEG_RXP_15 PEG_TXP_15 AB2 EXP_TXP15 22
HDJ42 EXP_RXN15 EXP_TXN15
9 HADSTBJ1 FSB_ADSTBB_1 FSB_DB_42 G25 22 EXP_RXN15 PEG_RXN_15 PEG_TXN_15 EXP_TXN15 22 R31
HDJ43 TP_MCH_R31
TP37

**
C39 FSB_DB_43 H24 HDJ44 DMI_RXP0 AD7 AC2 DMI_TXP0 TP_MCH_R32 R32 RSVD_14 P42 R346 0
9 HDSTBPJ0 B39 FSB_DSTBPB_0 FSB_DB_44 L24 23 DMI_RXP0 AD8 DMI_RXP_0 DMI_TXP_0 AD2 DMI_TXP0 23 TP36 U30 RSVD_15 SLPB P43 PM_SLP 10,29
HDJ45 DMI_RXN0 DMI_TXN0 TP_MCH_U30 R342 0
9 HDSTBNJ0 B40 FSB_DSTBNB_0 FSB_DB_45 J24 23 DMI_RXN0 AE9 DMI_RXN_0 DMI_TXN_0 AD4 DMI_TXN0 23 TP38 U31 RSVD_16 DPRSTPB PM_DPRSTP# 10,23
HDBIJ0 HDJ46 DMI_RXP1 DMI_TXP1 TP_MCH_U31
9 HDBIJ0 K31 FSB_DINVB_0 FSB_DB_46 N24 23 DMI_RXP1 AE10 DMI_RXP_1 DMI_TXP_1 AE4 DMI_TXP1 23 TP35 R15 RSVD_17
HDJ47 DMI_RXN1 DMI_TXN1 TP_MCH_R15
9 HDSTBPJ1 J31 FSB_DSTBPB_1 FSB_DB_47 C28 23 DMI_RXN1 AE6 DMI_RXN_1 DMI_TXN_1 AE2 DMI_TXN1 23 TP41 R14 RSVD_18
HDJ48 DMI_RXP2 DMI_TXP2 TP_MCH_R14
DMI_TXP2 23 TP40

DMI
C 9 HDSTBNJ1 HDBIJ1 F33 FSB_DSTBNB_1 FSB_DB_48 B31 HDJ49 23 DMI_RXP2 DMI_RXN2 AE7 DMI_RXP_2 DMI_TXP_2 AF2 DMI_TXN2 TP_MCH_T15 T15 RSVD_19 AN17 C
9 HDBIJ1 J25 FSB_DINVB_1 FSB_DB_49 F35 23 DMI_RXN2 AF9 DMI_RXN_2 DMI_TXN_2 AF4 DMI_TXN2 23 TP42 T14 RSVD_20 NC1 A44
HDJ50 DMI_RXP3 DMI_TXP3 TP_MCH_T14
9 HDSTBPJ2 K25 FSB_DSTBPB_2 FSB_DB_50 C35 23 DMI_RXP3 AF8 DMI_RXP_3 DMI_TXP_3 AG4 DMI_TXP3 23 TP39 AB15 RSVD_21 NC2 BD1
HDJ51 DMI_RXN3 DMI_TXN3 TP_MCH_AB15
9 HDSTBNJ2 F26 FSB_DSTBNB_2 FSB_DB_51 B35 23 DMI_RXN3 DMI_RXN_3 DMI_TXN_3 DMI_TXN3 23 TP45 A45 RSVD_22 NC3 BD45
HDBIJ2 HDJ52 TP_MCH_A45
9 HDBIJ2 C32 FSB_DINVB_2 FSB_DB_52 D35 1D1V_MCH TP44 B2 RSVD_23 NC4 BE2
HDJ53 TP_MCH_B2
9 HDSTBPJ3 D32 FSB_DSTBPB_3 FSB_DB_53 D31 TP46 BE1 RSVD_24 NC5 BE44
HDJ54 TP_MCH_BE1
TP43

*
9 HDSTBNJ3 HDBIJ3 D30 FSB_DSTBNB_3 FSB_DB_54 A34 HDJ55 D9 Y7 GMCH_EXP_COMP TP_MCH_BE45 BE45 RSVD_25 NC6 B14
R174 49.9
9 HDBIJ3 FSB_DINVB_3 FSB_DB_55 B32 7 CK_DMI_P_GMCH E9 EXP_CLKP EXP_RCOMPO Y8 TP49 L13 RSVD_26 NC7 B45
HDJ56 +/-1% TP_MCH_L13
J42 FSB_DB_56 F31 7 CK_DMI_N_GMCH EXP_CLKN EXP_COMPI Y6 L11 RSVD_27 NC8 AK15
HDJ57 TP_MCH_L11
9 HADSJ L40 FSB_ADSB FSB_DB_57 D28 J13 EXP_ICOMPO TP50 RSVD_28 NC9 AD42
HDJ58
9 HTRDYJ J43 FSB_TRDYB FSB_DB_58 A29 HDJ59 22 SDVO_CTRLDATA G13 SDVO_CTRLDATA NC10 AN16

*
9 HDRDYJ G44 FSB_DRDYB FSB_DB_59 C30 HDJ60 22 SDVO_CTRLCLK SDVO_CTRLCLK AG1 GMCH_EXP_RBIAS R171 750 NC11 W30
9 HDEFERJ K44 FSB_DEFERB FSB_DB_60 B30 HDJ61 TP_MCH_AB13 AB13 EXP_RBIAS +/-1% NC12 AW44
9 HITMJ H45 FSB_HITMB FSB_DB_61 E27 TP22 RSVD_1 NC13
HDJ62 TP_MCH_AD13 AD13 R42
9 HITJ H40 FSB_HITB FSB_DB_62 B28 TP23 RSVD_2 NC14 U32
HDJ63
9 HLOCKJ L42 FSB_LOCKB FSB_DB_63 NC15
9,10 HBR0J J44 FSB_BREQ0B
9 HBNRJ FSB_BNRB Q45
H37 B24 HSWING VSYNC
9 HBPRIJ H42 FSB_BPRIB FSB_SWING A23 HRCOMP HSYNC
9 HDBSYJ G43 FSB_DBSYB FSB_RCOMP dummy
9 HRSJ0 L44 FSB_RSB_0 C22 MCH_GTLREF C484 dummy
9
9
HRSJ1
HRSJ2
G42 FSB_RSB_1
FSB_RSB_2
FSB_DVREF
FSB_ACCVREF
B23 * 10pF
* C483
D27 10pF Q45
8,9,10,29,34 HCPURSTJ FSB_CPURSTB P29
CK_P_GMCH 7

*
TP_MCH_N25 N25 HPL_CLKINP P30 R1732 1K EXP_SM
TP21 RSVD_3 HPL_CLKINN CK_N_GMCH 7

Q45

R137 1.02K DAC_REFSET

+/-1%

* * *
FSB_VTT R140 10K H_FSBSEL0
FSB_VTT 7,10 FSBSEL0

R143 10K H_FSBSEL1

B

*R139 *R152 7,10 FSBSEL1 ATX: dummy

B

57.6 BTX: pop

301 +/-1% R145 10K H_FSBSEL2

*
+/-1% 7,10 FSBSEL2 R147 1K EXP_SLR
*

R172 49.9 MCH_GTLREF

*

R142 49.9 HSWING +/-1% Stuff for AMT

+/-1%

*
C61 R132 0 3D3V_SYS

* 1uF *R150 * C62

38 MCH_CLPWROK MCH_CLPWROK_R 24
*R144 *

*
C59 10V, X5R, +/-10% 100 220pF TP_MCH_L13 R379 10K
100 0.1uF +/-1% 50V, NPO, +/-5% dummy
+/-1% 16V, Y5V, +80%/-20% dummy

*
R151 0 dummy TP_MCH_K16
3D3V_SYS 22 PEG_PINB7
HSWING voltage should be 0.25*FSB_VTT
10 mils width, 10 mils spacing GTLREF voltage should be 0.67*VTT = 0.75V

*
max. 3 inches long 12 mils width, 15 mils spacing R371 1K TP_MCH_K16
divider should be within 1.5" of the GTLREF pin dummy
220pF caps should be placed near MCH pin
place series resistor as close to divider * R337

* * *
Resistor and Capacitor next to each other 1K R388 1K TP_MCH_J15
Dummy dummy

TLS R390 1K TP_MCH_J20

dummy
*

HRCOMP R148 16.5 R391 1K TP_MCH_F20

+/-1%
R370 unstuff for enable TLS, * R370 dummy
1K

10 mils width, 7 mils spacing

1D1V_MCH_CL R370 stuff for disable TLS Dummy

* *
max. 500 mils R3782 0
X8_PCIE_DET# 23
5 on 5 mils in breakout, max 250 mils
*R146
1K
+/-1%
0.35V
3D3V_SYS R368 0 EXP_SM
22 EXP_PRSNT dummy
CL_VREF_MCH
A A

*R149
464
+/-1%
* C60
0.1uF
16V, Y5V * 10K
min. 4 mils width R551
10 mils spacing Dummy
5 mils min. for max. of 300 mils in breakout

ITPM_EN

Title

* 10K
R545
Eaglelake -GMCH -1
R545 stuff for enable iTPM, dummy DWG NO Rev
R545 unstuff for disable iTPM A01
Arrowhead

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5

www.advancerepairlaptop.blogspot.com 4 3 2
Date: Friday, July 30, 2010
1
Sheet 12 of 45
 16 M_MAA_A[14..0]
5

M_MAA_A1
BC41
BC35
GMCHC

DDR_A_MA_0
4

3 OF 10

DDR_A_DQS_0
BC5
BD4
Trung Tâm Máy Tính AV
M_DQS_A0
M_DQS_AJ0
M_DQS_A[7..0] 16
M_DQS_AJ[7..0] 16
3

17 M_MAA_B[14..0] M_MAA_B0
M_MAA_B1
BD24
BB23
GMCHD
2

DDR_B_MA_0
4 OF 10

DDR_B_DQS_0
AW8
AW9
M_DQS_B0
M_DQS_BJ0
1

M_DQS_B[7..0] 17
M_DQS_BJ[7..0] 17
BB32 DDR_A_MA_1 DDR_A_DQSB_0 BC3 M_DQM_A[7..0] 16 BB24 DDR_B_MA_1 DDR_B_DQSB_0 AY6 M_DQM_B[7..0] 17
M_MAA_A2 M_DQM_A0 M_MAA_B2 M_DQM_B0
BC32 DDR_A_MA_2 DDR_A_DM_0 M_DATA_A[63..0] 16 BD23 DDR_B_MA_2 DDR_B_DM_0 M_DATA_B[63..0] 17
M_MAA_A3 M_MAA_B3
M_MAA_A4 BD32 DDR_A_MA_3 BC2 M_DATA_A0 M_MAA_B4 BB22 DDR_B_MA_3 AV7 M_DATA_B0
M_MAA_A5 BB31 DDR_A_MA_4 DDR_A_DQ_0 BD3 M_DATA_A1 M_MAA_B5 BD22 DDR_B_MA_4 DDR_B_DQ_0 AW4 M_DATA_B1
M_MAA_A6 AY31 DDR_A_MA_5 DDR_A_DQ_1 BD7 M_DATA_A2 M_MAA_B6 BC22 DDR_B_MA_5 DDR_B_DQ_1 BA9 M_DATA_B2
M_MAA_A7 BA31 DDR_A_MA_6 DDR_A_DQ_2 BB7 M_DATA_A3 M_MAA_B7 BC20 DDR_B_MA_6 DDR_B_DQ_2 AU11 M_DATA_B3
M_MAA_A8 BD31 DDR_A_MA_7 DDR_A_DQ_3 BB2 M_DATA_A4 M_MAA_B8 BB20 DDR_B_MA_7 DDR_B_DQ_3 AU7 M_DATA_B4
M_MAA_A9 BD30 DDR_A_MA_8 DDR_A_DQ_4 BA3 M_DATA_A5 M_MAA_B9 BD20 DDR_B_MA_8 DDR_B_DQ_4 AU8 M_DATA_B5
M_MAA_A10 AW43 DDR_A_MA_9 DDR_A_DQ_5 BE6 M_DATA_A6 M_MAA_B10 BC26 DDR_B_MA_9 DDR_B_DQ_5 AW7 M_DATA_B6
M_MAA_A11 BC30 DDR_A_MA_10 DDR_A_DQ_6 BD6 M_DATA_A7 M_MAA_B11 BD19 DDR_B_MA_10 DDR_B_DQ_6 AY9 M_DATA_B7
M_MAA_A12 BB30 DDR_A_MA_11 DDR_A_DQ_7 M_MAA_B12 BB19 DDR_B_MA_11 DDR_B_DQ_7
AM42 DDR_A_MA_12 BB9 M_DQS_A[7..0] 16 BE38 DDR_B_MA_12 AT15 M_DQS_B[7..0] 17
M_MAA_A13 M_DQS_A1 M_MAA_B13 M_DQS_B1
BD28 DDR_A_MA_13 DDR_A_DQS_1 BC9 M_DQS_AJ[7..0] 16 BA19 DDR_B_MA_13 DDR_B_DQS_1 AU15 M_DQS_BJ[7..0] 17
M_MAA_A14 M_DQS_AJ1 M_MAA_B14 M_DQS_BJ1
D DDR_A_MA_14 DDR_A_DQSB_1 BD9 M_DQM_A[7..0] 16 DDR_B_MA_14 DDR_B_DQSB_1 AR15 M_DQM_B[7..0] 17 D
M_DQM_A1 M_DQM_B1
AW42 DDR_A_DM_1 M_DATA_A[63..0] 16 BD36 DDR_B_DM_1 M_DATA_B[63..0] 17
AU42 DDR_A_WEB BB8 M_DATA_A8 17 M_WE_BJ BC37 DDR_B_WEB AY13 M_DATA_B8
16 M_CAS_AJ AV42 DDR_A_CASB DDR_A_DQ_8 AY8 M_DATA_A9 17 M_CAS_BJ BD35 DDR_B_CASB DDR_B_DQ_8 AP15 M_DATA_B9
16 M_RAS_AJ DDR_A_RASB DDR_A_DQ_9 BD11 M_DATA_A10 17 M_RAS_BJ DDR_B_RASB DDR_B_DQ_9 AW15 M_DATA_B10
M_BS_A0 AV45 DDR_A_DQ_10 BB11 M_DATA_A11 17 M_BS_B[2..0] M_BS_B0 BD26 DDR_B_DQ_10 AT16 M_DATA_B11
M_BS_A1 AY44 DDR_A_BS_0 DDR_A_DQ_11 BC7 M_DATA_A12 M_BS_B1 BB26 DDR_B_BS_0 DDR_B_DQ_11 AU13 M_DATA_B12
M_BS_A2 BC28 DDR_A_BS_1 DDR_A_DQ_12 BE8 M_DATA_A13 M_BS_B2 BD18 DDR_B_BS_1 DDR_B_DQ_12 AW13 M_DATA_B13
DDR_A_BS_2 DDR_A_DQ_13 BD10 M_DATA_A14 DDR_B_BS_2 DDR_B_DQ_13 AP16 M_DATA_B14
16 M_BS_A[2..0] AU43 DDR_A_DQ_14 AY11 M_DATA_A15 BB35 DDR_B_DQ_14 AU16 M_DATA_B15
16 M_SCS_A0J AR40 DDR_A_CSB_0 DDR_A_DQ_15 17 M_SCS_B0J BD39 DDR_B_CSB_0 DDR_B_DQ_15
AU44 DDR_A_CSB_1 BD15 M_DQS_A[7..0] 16 17 M_SCS_B1J BB37 DDR_B_CSB_1 AR20 M_DQS_B[7..0] 17
M_DQS_A2 M_DQS_B2
16 M_SCS_A2J AM43 DDR_A_CSB_2 DDR_A_DQS_2 BB15 M_DQS_AJ[7..0] 16 17 M_SCS_B2J BD40 DDR_B_CSB_2 DDR_B_DQS_2 AR17 M_DQS_BJ[7..0] 17
M_DQS_AJ2 M_DQS_BJ2
16 M_SCS_A3J DDR_A_CSB_3 DDR_A_DQSB_2 BD14 M_DQM_A[7..0] 16 17 M_SCS_B3J DDR_B_CSB_3 DDR_B_DQSB_2 AU17 M_DQM_B[7..0] 17
M_DQM_A2 M_DQM_B2
16 M_SCKE_A[3..0] BB27 DDR_A_DM_2 M_DATA_A[63..0] 16 17 M_SCKE_B[3..0] BC18 DDR_B_DM_2 M_DATA_B[63..0] 17
M_SCKE_A0 M_SCKE_B0
M_SCKE_A1 BD27 DDR_A_CKE_0 BB14 M_DATA_A16 M_SCKE_B1 AY20 DDR_B_CKE_0 AY17 M_DATA_B16
M_SCKE_A2 BA27 DDR_A_CKE_1 DDR_A_DQ_16 BC14 M_DATA_A17 M_SCKE_B2 BE17 DDR_B_CKE_1 DDR_B_DQ_16 AV17 M_DATA_B17
M_SCKE_A3 AY26 DDR_A_CKE_2 DDR_A_DQ_17 BC16 M_DATA_A18 M_SCKE_B3 BB18 DDR_B_CKE_2 DDR_B_DQ_17 AR21 M_DATA_B18
DDR_A_CKE_3 DDR_A_DQ_18 BB16 M_DATA_A19 DDR_B_CKE_3 DDR_B_DQ_18 AV20 M_DATA_B19
16 M_ODT_A[3..0] M_ODT_A0 AR42 DDR_A_DQ_19 BC11 M_DATA_A20 17 M_ODT_B[3..0] M_ODT_B0 BD37 DDR_B_DQ_19 AP17 M_DATA_B20
M_ODT_A1 AM44 DDR_A_ODT_0 DDR_A_DQ_20 BE12 M_DATA_A21 M_ODT_B1 BC39 DDR_B_ODT_0 DDR_B_DQ_20 AW16 M_DATA_B21
M_ODT_A2 AR44 DDR_A_ODT_1 DDR_A_DQ_21 BA15 M_DATA_A22 M_ODT_B2 BB38 DDR_B_ODT_1 DDR_B_DQ_21 AT20 M_DATA_B22
M_ODT_A3 AL40 DDR_A_ODT_2 DDR_A_DQ_22 BD16 M_DATA_A23 BD42 DDR_B_ODT_2 DDR_B_DQ_22 AN20 M_DATA_B23
DDR_A_ODT_3 DDR_A_DQ_23 DDR_B_ODT_3 DDR_B_DQ_23
AY37 AR22 M_DQS_A[7..0] 16 AY33 AU26 M_DQS_B[7..0] 17
M_DQS_A3 M_DQS_B3
16 CK_M_200M_P_DDR0_A BA37 DDR_A_CK_0 DDR_A_DQS_3 AT22 M_DQS_AJ[7..0] 16 17 CK_M_200M_P_DDR0_B AW33 DDR_B_CK_0 DDR_B_DQS_3 AT26 M_DQS_BJ[7..0] 17
M_DQS_AJ3 M_DQS_BJ3
16 CK_M_200M_N_DDR0_A AW29 DDR_A_CKB_0 DDR_A_DQSB_3 AV22 M_DQM_A[7..0] 16 17 CK_M_200M_N_DDR0_B AV31 DDR_B_CKB_0 DDR_B_DQSB_3 AV25 M_DQM_B[7..0] 17
M_DQM_A3 M_DQM_B3
AY29 DDR_A_CK_1 DDR_A_DM_3 M_DATA_A[63..0] 16 AW31 DDR_B_CK_1 DDR_B_DM_3 M_DATA_B[63..0] 17
AU37 DDR_A_CKB_1 AW21 M_DATA_A24 AW35 DDR_B_CKB_1 AT25 M_DATA_B24
16 CK_M_200M_P_DDR2_A AV37 DDR_A_CK_2 DDR_A_DQ_24 AY22 M_DATA_A25 17 CK_M_200M_P_DDR2_B AY35 DDR_B_CK_2 DDR_B_DQ_24 AV26 M_DATA_B25
16 CK_M_200M_N_DDR2_A AU33 DDR_A_CKB_2 DDR_A_DQ_25 AV24 M_DATA_A26 17 CK_M_200M_N_DDR2_B AT31 DDR_B_CKB_2 DDR_B_DQ_25 AU29 M_DATA_B26
16 CK_M_200M_P_DDR3_A AT33 DDR_A_CK_3 DDR_A_DQ_26 AY24 M_DATA_A27 17 CK_M_200M_P_DDR3_B AU31 DDR_B_CK_3 DDR_B_DQ_26 AV29 M_DATA_B27
16 CK_M_200M_N_DDR3_A AT30 DDR_A_CKB_3 DDR_A_DQ_27 AU21 M_DATA_A28 17 CK_M_200M_N_DDR3_B AP31 DDR_B_CKB_3 DDR_B_DQ_27 AW25 M_DATA_B28
AR30 DDR_A_CK_4 DDR_A_DQ_28 AT21 M_DATA_A29 17 CK_M_200M_P_DDR4_B AP30 DDR_B_CK_4 DDR_B_DQ_28 AR25 M_DATA_B29
AW38 DDR_A_CKB_4 DDR_A_DQ_29 AR24 M_DATA_A30 17 CK_M_200M_N_DDR4_B AW37 DDR_B_CKB_4 DDR_B_DQ_29 AP26 M_DATA_B30
16 CK_M_200M_P_DDR5_A AY38 DDR_A_CK_5 DDR_A_DQ_30 AU24 M_DATA_A31 AV35 DDR_B_CK_5 DDR_B_DQ_30 AR29 M_DATA_B31
16 CK_M_200M_N_DDR5_A DDR_A_CKB_5 DDR_A_DQ_31 DDR_B_CKB_5 DDR_B_DQ_31
AH43 M_DQS_A[7..0] 16 AR38 M_DQS_B[7..0] 17
C M_DQS_A4 M_DQS_B4 C
DDR_A_DQS_4 AH42 M_DQS_AJ[7..0] 16 DDR_B_DQS_4 AR37 M_DQS_BJ[7..0] 17
M_DQS_AJ4 M_DQS_BJ4
DDR_A_DQSB_4 AK42 M_DQM_A[7..0] 16 AR43 DDR_B_DQSB_4 AU39 M_DQM_B[7..0] 17
M_DQM_A4 M_DQM_B4
DDR_A_DM_4 M_DATA_A[63..0] 16 16 M_SCS_A1J BB40 DDR3_A_CSB1 DDR_B_DM_4 M_DATA_B[63..0] 17
M_MAA_A0
AL41 M_DATA_A32 16 M_MAA_A0 AT44 DDR3_A_MA0 AR36 M_DATA_B32
DDR_A_DQ_32 AK43 M_DATA_A33 16 M_WE_AJ M_ODT_B3 AV40 DDR3_A_WEB DDR_B_DQ_32 AU38 M_DATA_B33
DDR_A_DQ_33 AG42 M_DATA_A34 17 M_ODT_B3 DDR3_DRAM_PWROK AR6 DDR3_A_ODT3 DDR_B_DQ_33 AN35 M_DATA_B34
DDR_A_DQ_34 AG44 M_DATA_A35 BC24 DDR3_A_DRAM_PWROK DDR_B_DQ_34 AN37 M_DATA_B35
DDR_A_DQ_35 AL42 16,17 DRAMRSTJ DDR3_DRAMRSTB DDR_B_DQ_35 AV39
M_DATA_A36 M_DATA_B36
DDR_A_DQ_36 AK44 M_DATA_A37 DDR_B_DQ_36 AW39 M_DATA_B37
DDR_A_DQ_37 AH44 M_DATA_A38 DDR_B_DQ_37 AU40 M_DATA_B38
DDR_A_DQ_38 AG41 M_DATA_A39 DDR_B_DQ_38 AU41 M_DATA_B39
DDR_A_DQ_39 TP_DDR_AN29 AN29 DDR_B_DQ_39
AD43 M_DQS_A[7..0] 16 TP15 AN30 RSVD_4 AK34 M_DQS_B[7..0] 17
M_DQS_A5 TP_DDR_AN30 M_DQS_B5
DDR_A_DQS_5 AE42 M_DQS_AJ[7..0] 16 TP16 AJ33 RSVD_5 DDR_B_DQS_5 AL34 M_DQS_BJ[7..0] 17
M_DQS_AJ5 TP_DDR_AJ33 M_DQS_BJ5
DDR_A_DQSB_5 AE45 M_DQM_A[7..0] 16 TP17 AK33 RSVD_6 DDR_B_DQSB_5 AL37 M_DQM_B[7..0] 17
M_DQM_A5 TP_DDR_AK33 M_DQM_B5
DDR_A_DM_5 M_DATA_A[63..0] 16 TP18 RSVD_7 DDR_B_DM_5 M_DATA_B[63..0] 17
AF43 M_DATA_A40 AL35 M_DATA_B40
DDR_A_DQ_40 AF42 M_DATA_A41 DDR_B_DQ_40 AL36 M_DATA_B41
DDR_A_DQ_41 AC44 M_DATA_A42 DDR_B_DQ_41 AK36 M_DATA_B42
DDR_A_DQ_42 AC42 M_DATA_A43 DDR_B_DQ_42 AJ34 M_DATA_B43
DDR_A_DQ_43 AF40 M_DATA_A44 DDR_B_DQ_43 AN39 M_DATA_B44
DDR_A_DQ_44 AF44 M_DATA_A45 DDR_B_DQ_44 AN40 M_DATA_B45
DDR_A_DQ_45 AD44 M_DATA_A46 DDR_B_DQ_45 AK37 M_DATA_B46
DDR_A_DQ_46 AC41 M_DATA_A47 MCH_DDR_VREF BB44 DDR_B_DQ_46 AL39 M_DATA_B47
DDR_A_DQ_47 DDR_VREF DDR_B_DQ_47
Y43 M_DQS_A[7..0] 16 AF37 M_DQS_B[7..0] 17
M_DQS_A6 M_DQS_B6
DDR_A_DQS_6 Y42 M_DQS_AJ[7..0] 16 DDR_B_DQS_6 AF36 M_DQS_BJ[7..0] 17
M_DQS_AJ6 M_DQS_BJ6
DDR_A_DQSB_6 AA45 M_DQM_A[7..0] 16 AY42 DDR_B_DQSB_6 AJ35 M_DQM_B[7..0] 17
M_DQM_A6 MCH_DDR_RPD M_DQM_B6
DDR_A_DM_6 M_DATA_A[63..0] 16 BA43 DDR_RPD DDR_B_DM_6 M_DATA_B[63..0] 17
MCH_DDR_RPU
AB43 M_DATA_A48 MCH_DDR_SPD BC43 DDR_RPU AJ38 M_DATA_B48
DDR_A_DQ_48 AA42 M_DATA_A49 MCH_DDR_SPU BC44 DDR_SPD DDR_B_DQ_48 AJ37 M_DATA_B49
DDR_A_DQ_49 W42 M_DATA_A50 DDR_SPU DDR_B_DQ_49 AF38 M_DATA_B50
DDR_A_DQ_50 W41 M_DATA_A51 DDR_B_DQ_50 AE37 M_DATA_B51
DDR_A_DQ_51 AB42 M_DATA_A52 DDR_B_DQ_51 AK40 M_DATA_B52
DDR_A_DQ_52 AB44 M_DATA_A53 DDR_B_DQ_52 AJ40 M_DATA_B53
DDR_A_DQ_53 Y44 M_DATA_A54 DDR_B_DQ_53 AF34 M_DATA_B54
DDR_A_DQ_54 Y40 M_DATA_A55 DDR_B_DQ_54 AE35 M_DATA_B55
B DDR_A_DQ_55 DDR_B_DQ_55 B

T44 M_DQS_A[7..0] 16 AB35 M_DQS_B[7..0] 17

M_DQS_A7 M_DQS_B7
DDR_A DDR_A_DQS_7
DDR_A_DQSB_7
T43
T42
M_DQS_AJ7
M_DQM_A7
M_DQS_AJ[7..0] 16
M_DQM_A[7..0] 16
DDR_B_DQS_7
DDR_B_DQSB_7
AD35
AD37
M_DQS_BJ7
M_DQM_B7
M_DQS_BJ[7..0] 17
M_DQM_B[7..0] 17
DDR_A_DM_7
V42
M_DATA_A[63..0] 16 DDR_B DDR_B_DM_7
AD40
M_DATA_B[63..0] 17
M_DATA_A56 M_DATA_B56
DDR_A_DQ_56 U45 M_DATA_A57 DDR_B_DQ_56 AD38 M_DATA_B57
DDR_A_DQ_57 R40 M_DATA_A58 DDR_B_DQ_57 AB40 M_DATA_B58
DDR_A_DQ_58 P44 M_DATA_A59 DDR_B_DQ_58 AA39 M_DATA_B59
DDR_A_DQ_59 V44 M_DATA_A60 DDR_B_DQ_59 AE36 M_DATA_B60
DDR_A_DQ_60 V43 M_DATA_A61 DDR_B_DQ_60 AE39 M_DATA_B61
DDR_A_DQ_61 R41 M_DATA_A62 DDR_B_DQ_61 AB37 M_DATA_B62
DDR_A_DQ_62 R44 M_DATA_A63 DDR_B_DQ_62 AB38 M_DATA_B63
DDR_A_DQ_63 DDR_B_DQ_63

Q45
Q45

1D5V_STR
1D5V_STR DDRII Compensation Group Signals

*R5281
499
*R157
+/-1%
5V_SB_SYS
1K
+/-1%
R153 * 80.6
+/-1%
MCH_DDR_RPD

23 DDR3_DRAM_PWROK
MCH_DDR_VREF
R5291 1D5V_STR
C4351 R1341 1K
* *R160 * C67
*

1uF 0 +-5% 1K 0.1uF R154 80.6 MCH_DDR_RPU

10V, X5R, +/-10% +/-5% Dummy +/-1% 16V, Y5V +/-1%
Q341
Dummy C63
6 1 * 0.1uF
16V, Y5V
R5311Dummy 2
A 5 width 10 mils, spacing 10 mils A
20,23 SLP_S4J
*

5 mils width/spacing minimum for max. of 300 mils R155 249 MCH_DDR_SPD
1K +-5% 4 3 in GMCH break-out area +/-1%
Dummy Placed close to GMCH pin
MMDT5551 1D5V_STR
Dummy
*

R158 80.6 MCH_DDR_SPU

+/-1%
For DDR3 dram_power sequencing C66
* 0.1uF Title
16V, Y5V

If use ICH10R / ICH10 Eaglelake -GMCH -2

DWG NO Rev
POP this circuit A01
Change R5281 to 10KOhm and dummy R4101 Arrowhead

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5

www.advancerepairlaptop.blogspot.com
4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 13 of 45
 1D5V_ICH
FB3
5

FB 600 Ohm
4

Trung Tâm Máy Tính AV 3 2 1

*
R162 1 VCCDQ_CRT

C69 C457
1uF 1uF
* 10V, X5R, +/-10% * 10V, X5R, +/-10% GMCHG 7 OF 10 GMCHF 6 OF 10 1D1V_MCH 1D1V_PCIEXPRESS

1D1V_MCH_CL 1D1V_MCH_CL 1D1V_MCH 1D1V_PCIEXPRESS R695 0

r0805h6

AA32 AK21 AA19 AA14 R696 0

AA33 VCC_CL_1 VCC_CL_42 AK22 AA21 VCC_1 VCC_EXP_1 AA15 r0805h6
AB32 VCC_CL_2 VCC_CL_43 AK23 AA23 VCC_2 VCC_EXP_2 AB14
AB33 VCC_CL_3 VCC_CL_44 AK24 AA25 VCC_3 VCC_EXP_3 AC15
3D3V_SYS Modify according to Intel MOW50 AD32 VCC_CL_4 VCC_CL_45 AK25 AA27 VCC_4 VCC_EXP_4 AD14
AD33 VCC_CL_5 VCC_CL_46 AK26 AA29 VCC_5 VCC_EXP_5 AD15
D FB5 AE32 VCC_CL_6 VCC_CL_47 AK27 AA30 VCC_6 VCC_EXP_6 AE14
D
FB 600 Ohm C114 C339 C396
*

*
R163 R253 1 VCCA_EXP AE33 VCC_CL_7 VCC_CL_48 AK29 AB20 VCC_7 VCC_EXP_7 AE15
+/-1% 40.2 r0603h6 AF32 VCC_CL_8
VCC_CL_9
VCC_CL_49
VCC_CL_50
AK30 AB22 VCC_8
VCC_9
VCC_EXP_8
VCC_EXP_9
AF14 * 2.2uF
10V, X5R, +/-10%
* 2.2uF
10V, X5R, +/-10%
* 2.2uF
10V, X5R, +/-10%
C456 R703 AJ32 AL1 AB24 AF15
* 1uF * 39.2 AK31
AL30
VCC_CL_10
VCC_CL_11
VCC_CL_51
VCC_CL_52
AL10
AL11
AB26
AB29
VCC_10
VCC_11
VCC_EXP_10
VCC_EXP_11
AG15
AJ10
10V, X5R, +/-10% +/-1%
AM15 VCC_CL_12 VCC_CL_53 AL12 AB30 VCC_12 VCC_EXP_12 AJ11
AM16 VCC_CL_13 VCC_CL_54 AL14 AC16 VCC_13 VCC_EXP_13 AJ12
AM17 VCC_CL_14 VCC_CL_55 AL15 AC17 VCC_14 VCC_EXP_14 AJ13
3D3V_SYS AM20 VCC_CL_15 VCC_CL_56 AL16 AC19 VCC_15 VCC_EXP_15 AJ14
VCCA_DAC AM21 VCC_CL_16 VCC_CL_57 AL17 AC21 VCC_16 VCC_EXP_16 AJ6
FB4 AM22 VCC_CL_17 VCC_CL_58 AL19 AC23 VCC_17 VCC_EXP_17 AJ7
FB 600 Ohm
*

R164 1 VCCA_DAC AM24 VCC_CL_18 VCC_CL_59 AL2 1D5V_STR AC25 VCC_18 VCC_EXP_18 AJ8
r0603h6 AM25 VCC_CL_19 VCC_CL_60 AL20 AC27 VCC_19 VCC_EXP_19 AJ9
C107 C458 AM26 VCC_CL_20 VCC_CL_61 AL21 AC29 VCC_20 VCC_EXP_20 AK10
*R380 VCC_CL_21 VCC_CL_62 VCC_21 VCC_EXP_21

1
* 1uF
10V, X5R, +/-10% * 1uF
10V, X5R, +/-10% 0
AM29
Y32 VCC_CL_22 VCC_CL_63
AL22
AL23
* L26
AD16
AD17 VCC_22 VCC_EXP_22
AK11
AK12
dummy Y33 VCC_CL_23 VCC_CL_64 AL24 180nH AD20 VCC_23 VCC_EXP_23 AK13 1D1V_MCH_CL
AP1 VCC_CL_24 VCC_CL_65 AL25 AD22 VCC_24 VCC_EXP_24 AK6
AP2 VCC_CL_25 VCC_CL_66 AL26 AD24 VCC_25 VCC_EXP_25 AK7
Y31 VCC_CL_26 VCC_CL_67 AL27 AD26 VCC_26 VCC_EXP_26 AK8

2
Stuff for Non-Graphic sku AA31 VCC_CL_27 VCC_CL_68 AL29 AD29 VCC_27 VCC_EXP_27 AK9

POWER
AB31 VCC_CL_28 VCC_CL_69 AL4 VCC_CKDDR AE16 VCC_28 VCC_EXP_28 U14

1
AC31 VCC_CL_29 VCC_CL_70 AL5 AE17 VCC_29 VCC_EXP_29 U15 C153 C154

5V_SYS
AD31 VCC_CL_30
VCC_CL_31
VCC_CL_71
VCC_CL_72
AL6
C432
AE19 VCC_30
VCC_31
VCC_EXP_30
VCC_EXP_31
W15 * 10uF * 10uF
AE31 AL7 C431 AE21 Y14 c0805h14 c0805h14
* *

2
VCCA_DAC AF31 VCC_CL_32 VCC_CL_73 AL8 0.1uF 22uF AE23 VCC_32 VCC_EXP_32 Y15 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
AG30 VCC_CL_33 VCC_CL_74 AL9 16V, Y5V 6.3V, X5R, +/-10% AE25 VCC_33 VCC_EXP_33 AJ1
AG31 VCC_CL_34 VCC_CL_75 AM2 AE27 VCC_34 VCC_EXP_34 AJ2
U14 AJ30 VCC_CL_35 VCC_CL_76 AM3 AE29 VCC_35 VCC_EXP_35 AK2
1 5 AJ31 VCC_CL_36 VCC_CL_77 AM4 AF16 VCC_36 VCC_EXP_36 AK3 Place in 1D1V_MCH_CL plane
IN OUT AK16 VCC_CL_37 VCC_CL_78 AJ15 AF17 VCC_37 VCC_EXP_37 AK4 (less than 100 mils from the package)
3 4 AK17 VCC_CL_38 VCC_CL_79 AK14 AF19 VCC_38 VCC_EXP_38
EN ADJ AK19 VCC_CL_39 VCC_CL_80 AJ27 AF20 VCC_39
*R201 C160
GND

1.82KOhm 1uF AK20 VCC_CL_40 VCC_CL_81 AJ29 AF21 VCC_40

+/-1%
* EC34 * 10V, X5R, +/-10% VCC_CL_41 VCC_CL_82
VCC_CL_83
Y29 AF22 VCC_41
VCC_42
Dummy 220uF Y30 Place these parts close to AF23
2

C RT9179PB 6.3V, +/-20% Dummy VCC_CL_84 W31 AF24 VCC_43 C

VCC_CKDDR ballout in MCH backside

POWER
Dummy VCC_CL_85 1D5V_STR AF25 VCC_44
C161 Dummy 1D1V_MCH_CL AF26 VCC_45
1uF R202 AP44 1D5V_STR AF27 VCC_46 FSB_VTT
* 10V, X5R, +/-10% *1K VCCA_GPLLD B12 VCC_DDR_1 AT45 AF29 VCC_47
*

Dummy +/-1% R159 0 +/-5%VCCD_HPLL U33 VCCDPLL_EXP VCC_DDR_2 AV44 AG16 VCC_48
VCCD_HPLL VCC_DDR_3 VCC_49
Dummy VCCA_GPLL B16
VCCAPLL_EXP VCC_DDR_4
AY40
BA41 * L8
AG17
AG20 VCC_50
FSB_VTT
VCC_DDR_5 BB39 180nH AG22 VCC_51 A25

1
VCCA_HPLL B22 VCC_DDR_6 BD21 AG24 VCC_52 VTT_FSB_1 B25
VCCA_MPLL A21 VCCA_HPLL
VCCA_MPLL
VCC_DDR_7
VCC_DDR_8
BD25
Dummy
AG26 VCC_53
VCC_54
VTT_FSB_2
VTT_FSB_3
B26 * C116
2.2uF * C117
2.2uF * C118
2.2uF
VCCA_DPLLA D20 BD29 AG29 C24 c0603h9 c0603h9 c0603h9

2
3D3V_SYS VCCA_DPLLB C20 VCCA_DPLLA VCC_DDR_9 BD34 AJ16 VCC_55 VTT_FSB_4 C26
VCCA_DPLLB VCC_DDR_10 VCC_56 VTT_FSB_5

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

BD38 VCC_CKDDR BACK AJ17 D22
VCC_DDR_11 BE23 AJ19 VCC_57 VTT_FSB_6 D23
E19 VCC_DDR_12 BE27 AJ21 VCC_58 VTT_FSB_7 D24
VCC3_3 VCC_DDR_13 BE31 C80 AJ23 VCC_59 VTT_FSB_8 E23
VCC_HDA AR2 VCC_DDR_14 BE36 * 0.1uF AJ25 VCC_60 VTT_FSB_9 F21
* C78 VCC_HDA VCC_DDR_15 16V, Y5V *R169 *R170 R25
R26
VCC_61
VCC_62
VTT_FSB_10
VTT_FSB_11
F22
G21
0.1uF dummy 0 0
16V, Y5V VCCA_DAC B19 Dummy R27 VCC_63 VTT_FSB_12 G22
D19 VCCA_DAC_1 R29 VCC_64 VTT_FSB_13 H21
VCCA_DAC_2 AK32 BACK T21 VCC_65 VTT_FSB_14 H22
VCCA_EXP A17 VCC_CKDDR_1 AL31 BACK C81 T24 VCC_66 VTT_FSB_15 J21 Place in FSB_VTT plane as close to the GMCH as possible
1D1V_MCH_CL
L3
VCC_EXP VCC_CKDDR_2
VCC_CKDDR_3
AL32 * 22uF T25 VCC_67
VCC_68
VTT_FSB_16
VTT_FSB_17
J22 (less than 100 mils from the package)
AM31 Dummy 6.3V, X5R, +/-10% T26 K21
*

VCCA_HPLL VCCDQ_CRT B20 VCC_CKDDR_4 T27 VCC_69 VTT_FSB_18 K22

B17 VCCDQ_CRT AM30 T29 VCC_70 VTT_FSB_19 L21
VSS VCCCML_DDR Dummy U21 VCC_71 VTT_FSB_20 L22
1

270nH U22 VCC_72 VTT_FSB_21 M21

* C73
2.2uF
VCCAVRAM_EXP
AG2 U23 VCC_73
VCC_74
VTT_FSB_22
VTT_FSB_23
M22
6.3V, Y5V, +80%/-20% U24 N20
2

c0603h9 U25 VCC_75 VTT_FSB_24 N21

1D1V_MCH_CL U26 VCC_76 VTT_FSB_25 N22 1D5V_STR
L46 U27 VCC_77 VTT_FSB_26 P20
Q45 100nH

*
VCCCML_DDR U29 VCC_78 VTT_FSB_27 P21
W19 VCC_79 VTT_FSB_28 P22
W21 VCC_80 VTT_FSB_29 P24
B VCC_81 VTT_FSB_30 B
1D1V_MCH W23 R20

1
W25 VCC_82 VTT_FSB_31 R21
* C390
* C391
* C392
* C393
* C394
* C395

*
VCCAVRAM_EXP R382 0 W27 VCC_83 VTT_FSB_32 R22 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
1D5V_ICH W29 VCC_84 VTT_FSB_33 R23

2
1D1V_MCH_CL C586 Y20 VCC_85 VTT_FSB_34 R24
L4 VCC_86 VTT_FSB_35

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

4.7uF 1D5V_ICH Y22
*
*

VCC_87

C0603H9

C0603H9

C0603H9

C0603H9
1 2 VCCA_MPLL Y24
*R386

*
VCC_88

c0603h9

c0603h9
6.3V, X5R, +/-10% R332 0 Y26
R165 1 0 dummy dummy T22 VCC_89
2.2uH r0603h6 dummy c0805h14 T23 VCC_90
VCC_HDA AC4 VCC_91
dummy VCC_92
AF3
1

R166 1 C74 F9 VCC_93

r0603h6 * 10uF *R387 H4 VCC_94
VCC_95
10V, Y5V, +80%/-20% 0 L3
dummy
2

c0805h14 P3 VCC_96 Connect ground sides of caps with traces to GND balls
Dummy V4 VCC_97 (less than 100 mils from the package)
1D1V_MCH VCC_98
1D1V_MCH
L45
Q45
*

R372 1 VCCA_GPLLD
r0603h6
1

C83 C82
1uH R367 1 * 10uF * 0.1uF C123 C124 C397

1
r0603h6 10V, Y5V, +80%/-20% 16V, Y5V 22uF 22uF 22uF C115
* * * *
2

dummy c0805h14 10uF

1D1V_MCH_CL 1D1V_MCH 1D1V_MCH c0805h14

2
L5

10V, Y5V, +80%/-20%

*

6.3V,X5R,+/-20%

6.3V,X5R,+/-20%

6.3V,X5R,+/-20%
R167 1 VCCA_GPLL
r0603h6
1

* C75
* C76
1

1
1uH R168 1 10uF 0.1uF C128 C127 C119 C120 C121 C122 C125 C157 C155 C389 C126 C336 C156 C398
r0603h6 10V, Y5V, +80%/-20% 16V, Y5V * 10uF * 10uF * 10uF * 10uF * 10uF * 10uF * 1uF * 1uF * 1uF * 1uF * 1uF * 1uF * 1uF * 1uF
2

c0805h14 c0805h14 c0805h14 c0805h14 c0805h14 c0805h14 c0805h14 c0603h9 c0603h9 c0603h9 c0603h9 c0603h9 c0603h9 c0603h9 c0603h9
2
2

2
BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK BACK
10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

dummy
A A
L6
*

VCCA_DPLLA
EC3
10uH@2.52MHz * 470uF
+/-20% * C77
0.1uF
16V, Y5V

L7
*

VCCA_DPLLB dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy Title
EC4 Place these caps close to 1D1V_MCH plane in MCH backside
10uH@2.52MHz * 470uF
* C79 Eaglelake -GMCH -3
+/-20% 0.1uF
16V, Y5V DWG NO Rev
A01
Arrowhead

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5

www.advancerepairlaptop.blogspot.com
4 3 2
Date: Friday, July 30, 2010
1
Sheet 14 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

GMCHH 8 OF 10 GMCHI 9 OF 10
GMCHJ 10 OF 10

BD12 W17
A12 AJ36 BD17 VSS_186 VSS_271 L26
A15 VSS_1 VSS_94 AJ39 BD43 VSS_187 VSS_272 L30
A19 VSS_2 VSS_95 AJ44 BD8 VSS_188 VSS_273 L35 A3
A27 VSS_3 VSS_96 AJ45 BE10 VSS_189 VSS_274 L39 VSS_355 A43
A31 VSS_4 VSS_97 AK35 BE15 VSS_190 VSS_275 L4 VSS_356 A6
A36 VSS_5 VSS_98 AK38 BE19 VSS_191 VSS_276 L8 VSS_357 B44
A40 VSS_6 VSS_99 AK39 BE21 VSS_192 VSS_277 L9 VSS_358 BC1
A8 VSS_7 VSS_100 AL38 BE25 VSS_193 VSS_278 M1 VSS_359 BC45
D VSS_8 VSS_101 VSS_194 VSS_279 VSS_360 D
AA1 AL44 BE29 M24 BD2
AA11 VSS_9 VSS_102 AL45 BE34 VSS_195 VSS_280 M25 VSS_361 BD44
AA12 VSS_10 VSS_103 AN21 BE40 VSS_196 VSS_281 M44 VSS_362 BE3
AA13 VSS_11 VSS_104 AN22 C16 VSS_197 VSS_282 N11 VSS_363 BE43
AA16 VSS_12 VSS_105 AN24 C3 VSS_198 VSS_283 N13 VSS_364 C1

GND
AA17 VSS_13 VSS_106 AN25 C5 VSS_199 VSS_284 N16 VSS_365 C45
AA20 VSS_14 VSS_107 AN26 D11 VSS_200 VSS_285 N26 VSS_366 F1
AA22 VSS_15 VSS_108 AN33 D16 VSS_201 VSS_286 N29 VSS_367 BA5
AA24 VSS_16 VSS_109 AN36 D21 VSS_202 VSS_287 N30 VSS_368 AD30
AA26 VSS_17 VSS_110 AN38 D25 VSS_203 VSS_288 N33 VSS_369 AC30
AA34 VSS_18 VSS_111 AN7 D26 VSS_204 VSS_289 N36 VSS_370 AF30
AA38 VSS_19 VSS_112 AP20 D39 VSS_205 VSS_290 N38 VSS_371 AE30
AA40 VSS_20 VSS_113 AP21 D6 VSS_206 VSS_291 N8 VSS_372
AA44 VSS_21 VSS_114 AP22 D7 VSS_207 VSS_292 P16
AA8 VSS_22 VSS_115 AP24 E3 VSS_208 VSS_293 P17
AB11 VSS_23 VSS_116 AP25 E31 VSS_209 VSS_294 P25
AB12 VSS_24 VSS_117 AP29 E41 VSS_210 VSS_295 P26
AB16 VSS_25 VSS_118 AP45 E5 VSS_211 VSS_296 P31
AB17 VSS_26 VSS_119 AR10 F16 VSS_212 VSS_297 R11
AB19 VSS_27 VSS_120 AR11 F2 VSS_213 VSS_298 R12
AB21 VSS_28 VSS_121 AR13 F30 VSS_214 VSS_299 R16 Q45
AB23 VSS_29 VSS_122 AR16 F4 VSS_215 VSS_300 R17
AB25 VSS_30 VSS_123 AR26 F42 VSS_216 VSS_301 R19
AB27 VSS_31 VSS_124 AR3 F45 VSS_217 VSS_302 R2
AB34 VSS_32 VSS_125 AR31 G11 VSS_218 VSS_303 R30
AB36 VSS_33 VSS_126 AR33 G17 VSS_219 VSS_304 R38
AB39 VSS_34 VSS_127 AR35 G24 VSS_220 VSS_305 R45
AB4 VSS_35 VSS_128 AR39 G26 VSS_221 VSS_306 R5
AB6 VSS_36 VSS_129 AR8 G29 VSS_222 VSS_307 R8

GND
AB7 VSS_37 VSS_130 AR9 G3 VSS_223 VSS_308 T10
GND
AB8 VSS_38 VSS_131 AT1 G35 VSS_224 VSS_309 T11
AC20 VSS_39 VSS_132 AT11 H1 VSS_225 VSS_310 T12
AC22 VSS_40 VSS_133 AT13 H11 VSS_226 VSS_311 T13
AC24 VSS_41 VSS_134 AT17 H13 VSS_227 VSS_312 T16
AC26 VSS_42 VSS_135 AT2 H15 VSS_228 VSS_313 T17
AC45 VSS_43 VSS_136 AT24 H16 VSS_229 VSS_314 T19
AC5 VSS_44 VSS_137 AT29 H20 VSS_230 VSS_315 T20
C AD12 VSS_45 VSS_138 AT35 H25 VSS_231 VSS_316 T3 C
AD19 VSS_46 VSS_139 AU20 H30 VSS_232 VSS_317 T30
AD21 VSS_47 VSS_140 AU22 H31 VSS_233 VSS_318 T31
AD23 VSS_48 VSS_141 AU25 H33 VSS_234 VSS_319 T32
AD25 VSS_49 VSS_142 AU30 H38 VSS_235 VSS_320 T33
AD27 VSS_50 VSS_143 AU35 H44 VSS_236 VSS_321 T35
AD3 VSS_51 VSS_144 AU5 H7 VSS_237 VSS_322 T38
AD34 VSS_52 VSS_145 AU6 H8 VSS_238 VSS_323 T4
AD36 VSS_53 VSS_146 AU9 H9 VSS_239 VSS_324 T40
AD39 VSS_54 VSS_147 AV11 J3 VSS_240 VSS_325 T6
AD6 VSS_55 VSS_148 AV13 J37 VSS_241 VSS_326 T7
AD9 VSS_56 VSS_149 AV15 J4 VSS_242 VSS_327 T8
AE1 VSS_57 VSS_150 AV16 J5 VSS_243 VSS_328 T9
AE11 VSS_58 VSS_151 AV2 J8 VSS_244 VSS_329 U1
AE12 VSS_59 VSS_152 AV21 J9 VSS_245 VSS_330 W2
AE13 VSS_60 VSS_153 AV30 K11 VSS_246 VSS_331 W20
AE20 VSS_61 VSS_154 AV33 K13 VSS_247 VSS_332 W22
AE22 VSS_62 VSS_155 AV38 K17 VSS_248 VSS_333 W24
AE24 VSS_63 VSS_156 AV6 K20 VSS_249 VSS_334 W26
AE26 VSS_64 VSS_157 AV8 K24 VSS_250 VSS_335 W44
AE34 VSS_65 VSS_158 AV9 K29 VSS_251 VSS_336 W45
AE38 VSS_66 VSS_159 AW11 K33 VSS_252 VSS_337 W5
AE40 VSS_67 VSS_160 AW17 K45 VSS_253 VSS_338 Y10
AE44 VSS_68 VSS_161 AW20 L10 VSS_254 VSS_339 Y11
AE8 VSS_69 VSS_162 AW22 L16 VSS_255 VSS_340 Y12
AF10 VSS_70 VSS_163 AW24 L20 VSS_256 VSS_341 Y13
AF11 VSS_71 VSS_164 AW26 U11 VSS_257 VSS_342 Y16
AF12 VSS_72 VSS_165 AW3 U12 VSS_258 VSS_343 Y17
AF13 VSS_73 VSS_166 AW30 U13 VSS_259 VSS_344 Y19
AF33 VSS_74 VSS_167 AY1 U16 VSS_260 VSS_345 Y2
AF35 VSS_75 VSS_168 AY15 U17 VSS_261 VSS_346 Y21
AF39 VSS_76 VSS_169 AY16 U19 VSS_262 VSS_347 Y23
AF6 VSS_77 VSS_170 AY21 U20 VSS_263 VSS_348 Y25
AF7 VSS_78 VSS_171 AY25 U36 VSS_264 VSS_349 Y27
AG19 VSS_79 VSS_172 AY30 U39 VSS_265 VSS_350 Y3
AG21 VSS_80 VSS_173 AY45 U44 VSS_266 VSS_351 Y35
AG23 VSS_81 VSS_174 B10 U8 VSS_267 VSS_352 Y39
AG25 VSS_82 VSS_175 B21 W1 VSS_268 VSS_353 Y9
B VSS_83 VSS_176 VSS_269 VSS_354 B
AG27 B27 W16
AG45 VSS_84 VSS_177 B29 VSS_270
AG5 VSS_85 VSS_178 B34 MCH-HS
AH2 VSS_86 VSS_179 BA23 3
AH3 VSS_87 VSS_180 F8 4 A3 D
AH4 VSS_88 VSS_181 BB21 4
AJ20 VSS_89 VSS_182 BB25
AJ22 VSS_90 VSS_183 BB28 FOXCONN

AJ24 VSS_91 VSS_184 BB6 7

AJ26 VSS_92 VSS_185 B 7C 8
VSS_93 8
Heatsink

HS2 HS1
1 1
1 1 GPI_NB_HS_DETJ 23
2 2
2 2
Clip_2P Clip_2P

For GMCH heatsink hook

A A

Title

Eaglelake -GMCH -4
DWG NO Rev
A01
Arrowhead

www.advancerepairlaptop.blogspot.com
PDF 文件使用 "pdfFactory Pro" 试用版本创建 www.fineprint.cn
5 4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 15 of 45
 5

198
187
49
48
DIMM_1
FREE1
FREE2
FREE3
4

RSVD
ODT1
ODT0
79
77
195
Trung Tâm Máy Tính AV
M_ODT_A1
M_ODT_A0
M_ODT_A[3..0] 13
3

198
187
49
48
DIMM_3
FREE1
FREE2
FREE3
2

RSVD
ODT1
ODT0
79
77
195
M_ODT_A3
M_ODT_A2
M_ODT_A[3..0] 13
1

FREE4 FREE4
240 240
120 VTT 68 120 VTT 68
VTT_DDR VTT NC/PAR_IN VTT_DDR VTT NC/PAR_IN
53 53
NC/ERR_OUT 167 NC/ERR_OUT 167
239 NC/TEST4 239 NC/TEST4
235 VSS 235 VSS
232 VSS 232 VSS
229 VSS 229 VSS
226 VSS 226 VSS
223 VSS 39 223 VSS 39
220 VSS CB<0> 40 220 VSS CB<0> 40
217 VSS CB<1> 45 217 VSS CB<1> 45
D VSS CB<2> VSS CB<2> D
214 46 214 46
211 VSS CB<3> 158 211 VSS CB<3> 158
208 VSS CB<4> 159 208 VSS CB<4> 159
205 VSS CB<5> 164 205 VSS CB<5> 164
202 VSS CB<6> 165 202 VSS CB<6> 165
199 VSS CB<7> 199 VSS CB<7>
166 VSS M_DQS_AJ[7..0] 13 166 VSS M_DQS_AJ[7..0] 13
163 VSS 7 M_DQS_A0 163 VSS 7 M_DQS_A0
160 VSS DQS<0> 6 160 VSS DQS<0> 6
157 VSS DQS*<0> M_DQS_AJ0 157 VSS DQS*<0> M_DQS_AJ0
154 VSS 16 M_DQS_A1 154 VSS 16 M_DQS_A1
151 VSS DQS<1> 15 151 VSS DQS<1> 15
148 VSS DQS*<1> M_DQS_AJ1 148 VSS DQS*<1> M_DQS_AJ1
145 VSS 25 M_DQS_A2 145 VSS 25 M_DQS_A2
142 VSS DQS<2> 24 142 VSS DQS<2> 24
139 VSS DQS*<2> M_DQS_AJ2 139 VSS DQS*<2> M_DQS_AJ2
136 VSS 34 M_DQS_A3 136 VSS 34 M_DQS_A3
133 VSS DQS<3> 33 133 VSS DQS<3> 33
130 VSS DQS*<3> M_DQS_AJ3 130 VSS DQS*<3> M_DQS_AJ3
127 VSS 85 M_DQS_A4 127 VSS 85 M_DQS_A4
124 VSS DQS<4> 84 124 VSS DQS<4> 84
121 VSS DQS*<4> M_DQS_AJ4 121 VSS DQS*<4> M_DQS_AJ4
119 VSS 94 M_DQS_A5 119 VSS 94 M_DQS_A5
116 VSS DQS<5> 93 116 VSS DQS<5> 93
113 VSS DQS*<5> M_DQS_AJ5 113 VSS DQS*<5> M_DQS_AJ5
110 VSS 103 M_DQS_A6 110 VSS 103 M_DQS_A6
107 VSS DQS<6> 102 107 VSS DQS<6> 102
104 VSS DQS*<6> M_DQS_AJ6 104 VSS DQS*<6> M_DQS_AJ6
101 VSS 112 M_DQS_A7 101 VSS 112 M_DQS_A7
98 VSS DQS<7> 111 98 VSS DQS<7> 111
95 VSS DQS*<7> M_DQS_AJ7 95 VSS DQS*<7> M_DQS_AJ7
92 VSS 43 M_DQS_A[7..0] 13 92 VSS 43 M_DQS_A[7..0] 13
89 VSS DQS<8> 42 89 VSS DQS<8> 42
86 VSS DQS*<8> 86 VSS DQS*<8>
83 VSS 125 M_DQM_A0 83 VSS 125 M_DQM_A0
80 VSS DM0/DQS9 126 80 VSS DM0/DQS9 126
47 VSS DQS9* 47 VSS DQS9*
C 44 VSS 134 M_DQM_A1 44 VSS 134 M_DQM_A1 C
41 VSS DM1/DQS10 135 41 VSS DM1/DQS10 135
38 VSS DQS10* 38 VSS DQS10*
35 VSS 143 M_DQM_A2 35 VSS 143 M_DQM_A2
32 VSS DM2/DQS11 144 32 VSS DM2/DQS11 144
29 VSS DQS11* 29 VSS DQS11*
26 VSS 152 M_DQM_A3 26 VSS 152 M_DQM_A3
23 VSS DM3/DQS12 153 23 VSS DM3/DQS12 153
20 VSS DQS12* 20 VSS DQS12*
17 VSS 203 M_DQM_A4 17 VSS 203 M_DQM_A4
14 VSS DM4/DQS13 204 14 VSS DM4/DQS13 204
11 VSS DQS13* 11 VSS DQS13*
8 VSS 212 M_DQM_A5 8 VSS 212 M_DQM_A5
5 VSS DM5/DQS14 213 5 VSS DM5/DQS14 213
VSS DQS14* VSS DQS14*
DDRIII

DDRIII
2 2
VSS 221 M_DQM_A6 VSS 221 M_DQM_A6
1D5V_STR 197 DM6/DQS15 222 1D5V_STR 197 DM6/DQS15 222
194 VDDQ DQS15* 194 VDDQ DQS15*
191 VDDQ 230 M_DQM_A7 191 VDDQ 230 M_DQM_A7
189 VDDQ DM7/DQS16 231 189 VDDQ DM7/DQS16 231
186 VDDQ NC/DQS16* R941 186 VDDQ NC/DQS16* R942
183 VDDQ 161 M_DQM_A[7..0] 13 183 VDDQ 161 M_DQM_A[7..0] 13
+/-5% 0 dummy +/-5% 0 dummy
182 VDDQ DM8/DQS17 162 182 VDDQ DM8/DQS17 162
179 VDDQ DQS17* 179 VDDQ DQS17*
176 VDDQ 3 M_DATA_A[63..0] 13 176 VDDQ 3 M_DATA_A[63..0] 13
M_DATA_A0 M_DATA_A0
173 VDDQ DQ<0> 4 M_DATA_A1 173 VDDQ DQ<0> 4 M_DATA_A1
170 VDDQ DQ<1> 9 M_DATA_A2 170 VDDQ DQ<1> 9 M_DATA_A2
78 VDDQ DQ<2> 10 M_DATA_A3 78 VDDQ DQ<2> 10 M_DATA_A3
75 VDD DQ<3> 122 M_DATA_A4 75 VDD DQ<3> 122 M_DATA_A4
72 VDD DQ<4> 123 M_DATA_A5 72 VDD DQ<4> 123 M_DATA_A5
69 VDD DQ<5> 128 M_DATA_A6 69 VDD DQ<5> 128 M_DATA_A6
66 VDD DQ<6> 129 M_DATA_A7 66 VDD DQ<6> 129 M_DATA_A7
VDDSPD 65 VDD DQ<7> 12 M_DATA_A8 65 VDD DQ<7> 12 M_DATA_A8
62 VDD DQ<8> 13 M_DATA_A9 62 VDD DQ<8> 13 M_DATA_A9
C429 60 VDD DQ<9> 18 M_DATA_A10 60 VDD DQ<9> 18 M_DATA_A10
57 VDD DQ<10> 19 57 VDD DQ<10> 19
*4.7uF VDD DQ<11>
M_DATA_A11
VDD DQ<11>
M_DATA_A11
6.3V, X5R

54 131 M_DATA_A12 54 131 M_DATA_A12

51 VDD DQ<12> 132 M_DATA_A13 VDDSPD 51 VDD DQ<12> 132 M_DATA_A13
B VDD DQ<13> VDD DQ<13> B
236 137 M_DATA_A14 236 137 M_DATA_A14
VDDSPD DQ<14> 138 M_DATA_A15 VDDSPD DQ<14> 138 M_DATA_A15
DQ<15> 21 M_DATA_A16 DQ<15> 21 M_DATA_A16
SMVREF_A_DDR3 67 DQ<16> 22 M_DATA_A17 SMVREF_A_DDR3 67 DQ<16> 22 M_DATA_A17
18 SMVREF_A_DDR3 1 VREFCA DQ<17> 27 18 SMVREF_A_DDR3 1 VREFCA DQ<17> 27
SMVREFDQ_A M_DATA_A18 SMVREFDQ_A M_DATA_A18
18 SMVREFDQ_A 118 VREFDQ DQ<18> 28 18 SMVREFDQ_A 118 VREFDQ DQ<18> 28
M_DATA_A19 M_DATA_A19
7,17,22,23,29,31 SMB_CLK_RESUME 238 SCL DQ<19> 140 M_DATA_A20 7,17,22,23,29,31 SMB_CLK_RESUME 238 SCL DQ<19> 140 M_DATA_A20
7,17,22,23,29,31 SMB_DATA_RESUME 237 SDA DQ<20> 141 M_DATA_A21 7,17,22,23,29,31 SMB_DATA_RESUME 237 SDA DQ<20> 141 M_DATA_A21
SA1 SA0 SA1 DQ<21> SA1 DQ<21>
117 146 M_DATA_A22 SA1 SA0 117 146 M_DATA_A22
0 0 SA0 DQ<22> 147 M_DATA_A23 SA0 DQ<22> 147 M_DATA_A23
DQ<23> 30 M_DATA_A24 0 1 DQ<23> 30 M_DATA_A24
DQ<24> 31 M_DATA_A25 DQ<24> 31 M_DATA_A25
13 M_BS_A[2..0] M_BS_A2 52 DQ<25> 36 M_DATA_A26 13 M_BS_A[2..0] M_BS_A2 52 DQ<25> 36 M_DATA_A26
M_BS_A1 190 BA2 DQ<26> 37 M_DATA_A27 M_BS_A1 190 BA2 DQ<26> 37 M_DATA_A27
M_BS_A0 71 BA1 DQ<27> 149 M_DATA_A28 M_BS_A0 71 BA1 DQ<27> 149 M_DATA_A28
BA0 DQ<28> 150 M_DATA_A29 BA0 DQ<28> 150 M_DATA_A29
DQ<29> 155 M_DATA_A30 DQ<29> 155 M_DATA_A30
13 M_SCKE_A[3..0] M_SCKE_A1 169 DQ<30> 156 M_DATA_A31 13 M_SCKE_A[3..0] M_SCKE_A3 169 DQ<30> 156 M_DATA_A31
M_SCKE_A0 50 CKE1 DQ<31> 81 M_DATA_A32 M_SCKE_A2 50 CKE1 DQ<31> 81 M_DATA_A32
CKE0 DQ<32> 82 M_DATA_A33 CKE0 DQ<32> 82 M_DATA_A33
76 DQ<33> 87 M_DATA_A34 76 DQ<33> 87 M_DATA_A34
13 M_SCS_A1J S1* DQ<34> 13 M_SCS_A3J S1* DQ<34>
193 88 M_DATA_A35 193 88 M_DATA_A35
13 M_SCS_A0J S0* DQ<35> 13 M_SCS_A2J S0* DQ<35>
200 M_DATA_A36 200 M_DATA_A36
DQ<36> 201 M_DATA_A37 DQ<36> 201 M_DATA_A37
64 DQ<37> 206 M_DATA_A38 64 DQ<37> 206 M_DATA_A38
13 CK_M_200M_N_DDR0_A CK1/NU* DQ<38> 13 CK_M_200M_N_DDR3_A CK1/NU* DQ<38>
63 207 M_DATA_A39 63 207 M_DATA_A39
13 CK_M_200M_P_DDR0_A CK1/NU DQ<39> 13 CK_M_200M_P_DDR3_A CK1/NU DQ<39>
185 90 M_DATA_A40 185 90 M_DATA_A40
13 CK_M_200M_N_DDR2_A 184 CK0* DQ<40> 91 13 CK_M_200M_N_DDR5_A 184 CK0* DQ<40> 91
13 CK_M_200M_P_DDR2_A M_DATA_A41 13 CK_M_200M_P_DDR5_A M_DATA_A41
CK0 DQ<41> 96 M_DATA_A42 CK0 DQ<41> 96 M_DATA_A42
13 M_MAA_A[14..0] M_MAA_A0 188 DQ<42> 97 M_DATA_A43 13 M_MAA_A[14..0] M_MAA_A0 188 DQ<42> 97 M_DATA_A43
M_MAA_A1 181 A0 DQ<43> 209 M_DATA_A44 M_MAA_A1 181 A0 DQ<43> 209 M_DATA_A44
M_MAA_A2 61 A1 DQ<44> 210 M_DATA_A45 M_MAA_A2 61 A1 DQ<44> 210 M_DATA_A45
M_MAA_A3 180 A2 DQ<45> 215 M_DATA_A46 M_MAA_A3 180 A2 DQ<45> 215 M_DATA_A46
M_MAA_A4 59 A3 DQ<46> 216 M_DATA_A47 M_MAA_A4 59 A3 DQ<46> 216 M_DATA_A47
M_MAA_A5 58 A4 DQ<47> 99 M_DATA_A48 M_MAA_A5 58 A4 DQ<47> 99 M_DATA_A48
M_MAA_A6 178 A5 DQ<48> 100 M_DATA_A49 M_MAA_A6 178 A5 DQ<48> 100 M_DATA_A49
M_MAA_A7 56 A6 DQ<49> 105 M_DATA_A50 M_MAA_A7 56 A6 DQ<49> 105 M_DATA_A50
A M_MAA_A8 177 A7 DQ<50> 106 M_DATA_A51 M_MAA_A8 177 A7 DQ<50> 106 M_DATA_A51 A
M_MAA_A9 175 A8 DQ<51> 218 M_DATA_A52 M_MAA_A9 175 A8 DQ<51> 218 M_DATA_A52
M_MAA_A10 70 A9 DQ<52> 219 M_DATA_A53 M_MAA_A10 70 A9 DQ<52> 219 M_DATA_A53
M_MAA_A11 55 A10/AP DQ<53> 224 M_DATA_A54 M_MAA_A11 55 A10/AP DQ<53> 224 M_DATA_A54
M_MAA_A12 174 A11 DQ<54> 225 M_DATA_A55 M_MAA_A12 174 A11 DQ<54> 225 M_DATA_A55
M_MAA_A13 196 A12 DQ<55> 108 M_DATA_A56 M_MAA_A13 196 A12 DQ<55> 108 M_DATA_A56
M_MAA_A14 172 A13 DQ<56> 109 M_DATA_A57 M_MAA_A14 172 A13 DQ<56> 109 M_DATA_A57
171 A14 DQ<57> 114 M_DATA_A58 171 A14 DQ<57> 114 M_DATA_A58
A15 DQ<58> 115 M_DATA_A59 A15 DQ<58> 115 M_DATA_A59
168 DQ<59> 227 M_DATA_A60 168 DQ<59> 227 M_DATA_A60
13,17 DRAMRSTJ 74 RESET* DQ<60> 228 13,17 DRAMRSTJ 74 RESET* DQ<60> 228
M_DATA_A61 M_DATA_A61 Title
13 M_CAS_AJ 192 CAS* DQ<61> 233 M_DATA_A62 13 M_CAS_AJ 192 CAS* DQ<61> 233 M_DATA_A62
13 M_RAS_AJ
13 M_WE_AJ
73 RAS*
WE*
DQ<62>
DQ<63>
234 M_DATA_A63 13 M_RAS_AJ
13 M_WE_AJ
73 RAS*
WE*
DQ<62>
DQ<63>
234 M_DATA_A63 DDRIII Channel A DIMM 1, 3
DDR III ddr240_ddr3h260 DDR III ddr240_ddr3h260 DWG NO Rev
A01
Arrowhead

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4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 16 of 45
 5

198
187
49
48
DIMM_2
FREE1
FREE2
FREE3
4

RSVD
ODT1
ODT0
79
77
195
Trung Tâm Máy Tính AV
M_ODT_B1
M_ODT_B0
M_ODT_B[3..0] 13
3

198
187
49
48
DIMM_4
FREE1
FREE2
FREE3
2

RSVD
ODT1
ODT0
79
77
195
M_ODT_B3
M_ODT_B2
M_ODT_B[3..0] 13
1

FREE4 FREE4
240 240
120 VTT 68 120 VTT 68
VTT_DDR VTT NC/PAR_IN VTT_DDR VTT NC/PAR_IN
53 53
NC/ERR_OUT 167 NC/ERR_OUT 167
239 NC/TEST4 239 NC/TEST4
235 VSS 235 VSS
232 VSS 232 VSS
229 VSS 229 VSS
226 VSS 226 VSS
223 VSS 39 223 VSS 39
220 VSS CB<0> 40 220 VSS CB<0> 40
217 VSS CB<1> 45 217 VSS CB<1> 45
D VSS CB<2> VSS CB<2> D
214 46 214 46
211 VSS CB<3> 158 211 VSS CB<3> 158
208 VSS CB<4> 159 208 VSS CB<4> 159
205 VSS CB<5> 164 205 VSS CB<5> 164
202 VSS CB<6> 165 202 VSS CB<6> 165
199 VSS CB<7> 199 VSS CB<7>
166 VSS M_DQS_BJ[7..0] 13 166 VSS M_DQS_BJ[7..0] 13
163 VSS 7 M_DQS_B0 163 VSS 7 M_DQS_B0
160 VSS DQS<0> 6 160 VSS DQS<0> 6
157 VSS DQS*<0> M_DQS_BJ0 157 VSS DQS*<0> M_DQS_BJ0
154 VSS 16 M_DQS_B1 154 VSS 16 M_DQS_B1
151 VSS DQS<1> 15 151 VSS DQS<1> 15
148 VSS DQS*<1> M_DQS_BJ1 148 VSS DQS*<1> M_DQS_BJ1
145 VSS 25 M_DQS_B2 145 VSS 25 M_DQS_B2
142 VSS DQS<2> 24 142 VSS DQS<2> 24
139 VSS DQS*<2> M_DQS_BJ2 139 VSS DQS*<2> M_DQS_BJ2
136 VSS 34 M_DQS_B3 136 VSS 34 M_DQS_B3
133 VSS DQS<3> 33 133 VSS DQS<3> 33
130 VSS DQS*<3> M_DQS_BJ3 130 VSS DQS*<3> M_DQS_BJ3
127 VSS 85 M_DQS_B4 127 VSS 85 M_DQS_B4
124 VSS DQS<4> 84 124 VSS DQS<4> 84
121 VSS DQS*<4> M_DQS_BJ4 121 VSS DQS*<4> M_DQS_BJ4
119 VSS 94 M_DQS_B5 119 VSS 94 M_DQS_B5
116 VSS DQS<5> 93 116 VSS DQS<5> 93
113 VSS DQS*<5> M_DQS_BJ5 113 VSS DQS*<5> M_DQS_BJ5
110 VSS 103 M_DQS_B6 110 VSS 103 M_DQS_B6
107 VSS DQS<6> 102 107 VSS DQS<6> 102
104 VSS DQS*<6> M_DQS_BJ6 104 VSS DQS*<6> M_DQS_BJ6
101 VSS 112 M_DQS_B7 101 VSS 112 M_DQS_B7
98 VSS DQS<7> 111 98 VSS DQS<7> 111
95 VSS DQS*<7> M_DQS_BJ7 95 VSS DQS*<7> M_DQS_BJ7
92 VSS 43 M_DQS_B[7..0] 13 92 VSS 43 M_DQS_B[7..0] 13
89 VSS DQS<8> 42 89 VSS DQS<8> 42
86 VSS DQS*<8> 86 VSS DQS*<8>
83 VSS 125 M_DQM_B0 83 VSS 125 M_DQM_B0
80 VSS DM0/DQS9 126 80 VSS DM0/DQS9 126
47 VSS DQS9* 47 VSS DQS9*
C 44 VSS 134 M_DQM_B1 44 VSS 134 M_DQM_B1 C
41 VSS DM1/DQS10 135 41 VSS DM1/DQS10 135
38 VSS DQS10* 38 VSS DQS10*
35 VSS 143 M_DQM_B2 35 VSS 143 M_DQM_B2
32 VSS DM2/DQS11 144 32 VSS DM2/DQS11 144
29 VSS DQS11* 29 VSS DQS11*
26 VSS 152 M_DQM_B3 26 VSS 152 M_DQM_B3
23 VSS DM3/DQS12 153 23 VSS DM3/DQS12 153
20 VSS DQS12* 20 VSS DQS12*
17 VSS 203 M_DQM_B4 17 VSS 203 M_DQM_B4
14 VSS DM4/DQS13 204 14 VSS DM4/DQS13 204
11 VSS DQS13* 11 VSS DQS13*
8 VSS 212 M_DQM_B5 8 VSS 212 M_DQM_B5
5 VSS DM5/DQS14 213 5 VSS DM5/DQS14 213
VSS DQS14* VSS DQS14*
DDRIII

DDRIII
2 2
VSS 221 M_DQM_B6 VSS 221 M_DQM_B6
1D5V_STR 197 DM6/DQS15 222 1D5V_STR 197 DM6/DQS15 222
194 VDDQ DQS15* 194 VDDQ DQS15*
191 VDDQ 230 M_DQM_B7 191 VDDQ 230 M_DQM_B7
189 VDDQ DM7/DQS16 231 189 VDDQ DM7/DQS16 231
186 VDDQ NC/DQS16* R944 186 VDDQ NC/DQS16* R945
183 VDDQ 161 M_DQM_B[7..0] 13 183 VDDQ 161 M_DQM_B[7..0] 13
+/-5% 0 dummy +/-5% 0 dummy
182 VDDQ DM8/DQS17 162 182 VDDQ DM8/DQS17 162
179 VDDQ DQS17* 179 VDDQ DQS17*
176 VDDQ 3 M_DATA_B[63..0] 13 176 VDDQ 3 M_DATA_B[63..0] 13
M_DATA_B0 M_DATA_B0
173 VDDQ DQ<0> 4 M_DATA_B1 173 VDDQ DQ<0> 4 M_DATA_B1
170 VDDQ DQ<1> 9 M_DATA_B2 170 VDDQ DQ<1> 9 M_DATA_B2
78 VDDQ DQ<2> 10 M_DATA_B3 78 VDDQ DQ<2> 10 M_DATA_B3
75 VDD DQ<3> 122 M_DATA_B4 75 VDD DQ<3> 122 M_DATA_B4
72 VDD DQ<4> 123 M_DATA_B5 72 VDD DQ<4> 123 M_DATA_B5
69 VDD DQ<5> 128 M_DATA_B6 69 VDD DQ<5> 128 M_DATA_B6
66 VDD DQ<6> 129 M_DATA_B7 66 VDD DQ<6> 129 M_DATA_B7
65 VDD DQ<7> 12 M_DATA_B8 65 VDD DQ<7> 12 M_DATA_B8
62 VDD DQ<8> 13 M_DATA_B9 62 VDD DQ<8> 13 M_DATA_B9
60 VDD DQ<9> 18 M_DATA_B10 60 VDD DQ<9> 18 M_DATA_B10
57 VDD DQ<10> 19 M_DATA_B11 57 VDD DQ<10> 19 M_DATA_B11
54 VDD DQ<11> 131 M_DATA_B12 54 VDD DQ<11> 131 M_DATA_B12
51 VDD DQ<12> 132 M_DATA_B13 VDDSPD 51 VDD DQ<12> 132 M_DATA_B13
B VDD DQ<13> VDD DQ<13> B
236 137 M_DATA_B14 236 137 M_DATA_B14
VDDSPD VDDSPD DQ<14> VDDSPD DQ<14>
138 M_DATA_B15 138 M_DATA_B15
DQ<15> 21 M_DATA_B16 DQ<15> 21 M_DATA_B16
SMVREF_B_DDR3 67 DQ<16> 22 M_DATA_B17 SMVREF_B_DDR3 67 DQ<16> 22 M_DATA_B17
18 SMVREF_B_DDR3 1 VREFCA DQ<17> 27 18 SMVREF_B_DDR3 1 VREFCA DQ<17> 27
SMVREFDQ_B M_DATA_B18 SMVREFDQ_B M_DATA_B18
18 SMVREFDQ_B 118 VREFDQ DQ<18> 28 18 SMVREFDQ_B 118 VREFDQ DQ<18> 28
M_DATA_B19 M_DATA_B19
7,16,22,23,29,31 SMB_CLK_RESUME 238 SCL DQ<19> 140 M_DATA_B20 7,16,22,23,29,31 SMB_CLK_RESUME 238 SCL DQ<19> 140 M_DATA_B20
7,16,22,23,29,31 SMB_DATA_RESUME 237 SDA DQ<20> 141 M_DATA_B21 7,16,22,23,29,31 SMB_DATA_RESUME 237 SDA DQ<20> 141 M_DATA_B21
SA1 SA0 SA1 DQ<21>
SA1 SA0 SA1 DQ<21>
117 146 M_DATA_B22 117 146 M_DATA_B22
1 0 SA0 DQ<22> 147 M_DATA_B23 1 1 SA0 DQ<22> 147 M_DATA_B23
DQ<23> 30 M_DATA_B24 DQ<23> 30 M_DATA_B24
DQ<24> 31 M_DATA_B25 DQ<24> 31 M_DATA_B25
13 M_BS_B[2..0] DQ<25> 13 M_BS_B[2..0] DQ<25>
M_BS_B2 52 36 M_DATA_B26 M_BS_B2 52 36 M_DATA_B26
M_BS_B1 190 BA2 DQ<26> 37 M_DATA_B27 M_BS_B1 190 BA2 DQ<26> 37 M_DATA_B27
M_BS_B0 71 BA1 DQ<27> 149 M_DATA_B28 M_BS_B0 71 BA1 DQ<27> 149 M_DATA_B28
BA0 DQ<28> 150 M_DATA_B29 BA0 DQ<28> 150 M_DATA_B29
DQ<29> 155 M_DATA_B30 DQ<29> 155 M_DATA_B30
13 M_SCKE_B[3..0] DQ<30> 13 M_SCKE_B[3..0] DQ<30>
M_SCKE_B1 169 156 M_DATA_B31 M_SCKE_B3 169 156 M_DATA_B31
M_SCKE_B0 50 CKE1 DQ<31> 81 M_DATA_B32 M_SCKE_B2 50 CKE1 DQ<31> 81 M_DATA_B32
CKE0 DQ<32> 82 M_DATA_B33 CKE0 DQ<32> 82 M_DATA_B33
76 DQ<33> 87 M_DATA_B34 76 DQ<33> 87 M_DATA_B34
13 M_SCS_B1J S1* DQ<34> 13 M_SCS_B3J S1* DQ<34>
193 88 M_DATA_B35 193 88 M_DATA_B35
13 M_SCS_B0J S0* DQ<35> 13 M_SCS_B2J S0* DQ<35>
200 M_DATA_B36 200 M_DATA_B36
DQ<36> 201 M_DATA_B37 DQ<36> 201 M_DATA_B37
64 DQ<37> 206 M_DATA_B38 64 DQ<37> 206 M_DATA_B38
13 CK_M_200M_N_DDR2_B CK1/NU* DQ<38> 13 CK_M_200M_N_DDR4_B CK1/NU* DQ<38>
63 207 M_DATA_B39 63 207 M_DATA_B39
13 CK_M_200M_P_DDR2_B CK1/NU DQ<39> 13 CK_M_200M_P_DDR4_B CK1/NU DQ<39>
185 90 M_DATA_B40 185 90 M_DATA_B40
13 CK_M_200M_N_DDR0_B CK0* DQ<40> 13 CK_M_200M_N_DDR3_B CK0* DQ<40>
184 91 M_DATA_B41 184 91 M_DATA_B41
13 CK_M_200M_P_DDR0_B CK0 DQ<41> 13 CK_M_200M_P_DDR3_B CK0 DQ<41>
96 M_DATA_B42 96 M_DATA_B42
13 M_MAA_B[14..0] M_MAA_B0 188 DQ<42> 97 M_DATA_B43 13 M_MAA_B[14..0] M_MAA_B0 188 DQ<42> 97 M_DATA_B43
M_MAA_B1 181 A0 DQ<43> 209 M_DATA_B44 M_MAA_B1 181 A0 DQ<43> 209 M_DATA_B44
M_MAA_B2 61 A1 DQ<44> 210 M_DATA_B45 M_MAA_B2 61 A1 DQ<44> 210 M_DATA_B45
M_MAA_B3 180 A2 DQ<45> 215 M_DATA_B46 M_MAA_B3 180 A2 DQ<45> 215 M_DATA_B46
M_MAA_B4 59 A3 DQ<46> 216 M_DATA_B47 M_MAA_B4 59 A3 DQ<46> 216 M_DATA_B47
M_MAA_B5 58 A4 DQ<47> 99 M_DATA_B48 M_MAA_B5 58 A4 DQ<47> 99 M_DATA_B48
M_MAA_B6 178 A5 DQ<48> 100 M_DATA_B49 M_MAA_B6 178 A5 DQ<48> 100 M_DATA_B49
M_MAA_B7 56 A6 DQ<49> 105 M_DATA_B50 M_MAA_B7 56 A6 DQ<49> 105 M_DATA_B50
A M_MAA_B8 177 A7 DQ<50> 106 M_DATA_B51 M_MAA_B8 177 A7 DQ<50> 106 M_DATA_B51 A
M_MAA_B9 175 A8 DQ<51> 218 M_DATA_B52 M_MAA_B9 175 A8 DQ<51> 218 M_DATA_B52
M_MAA_B10 70 A9 DQ<52> 219 M_DATA_B53 M_MAA_B10 70 A9 DQ<52> 219 M_DATA_B53
M_MAA_B11 55 A10/AP DQ<53> 224 M_DATA_B54 M_MAA_B11 55 A10/AP DQ<53> 224 M_DATA_B54
M_MAA_B12 174 A11 DQ<54> 225 M_DATA_B55 M_MAA_B12 174 A11 DQ<54> 225 M_DATA_B55
M_MAA_B13 196 A12 DQ<55> 108 M_DATA_B56 M_MAA_B13 196 A12 DQ<55> 108 M_DATA_B56
M_MAA_B14 172 A13 DQ<56> 109 M_DATA_B57 M_MAA_B14 172 A13 DQ<56> 109 M_DATA_B57
171 A14 DQ<57> 114 M_DATA_B58 171 A14 DQ<57> 114 M_DATA_B58
A15 DQ<58> 115 M_DATA_B59 A15 DQ<58> 115 M_DATA_B59
168 DQ<59> 227 M_DATA_B60 168 DQ<59> 227 M_DATA_B60
13,16 DRAMRSTJ 74 RESET* DQ<60> 228 13,16 DRAMRSTJ 74 RESET* DQ<60> 228
M_DATA_B61 M_DATA_B61 Title
13 M_CAS_BJ 192 CAS* DQ<61> 233 M_DATA_B62 13 M_CAS_BJ 192 CAS* DQ<61> 233 M_DATA_B62
13 M_RAS_BJ
13 M_WE_BJ
73 RAS*
WE*
DQ<62>
DQ<63>
234 M_DATA_B63 13 M_RAS_BJ
13 M_WE_BJ
73 RAS*
WE*
DQ<62>
DQ<63>
234 M_DATA_B63 DDRIII Channel B DIMM 2, 4
DDR III ddr240_ddr3h260 DDR III ddr240_ddr3h260 DWG NO Rev
A01
Arrowhead

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www.advancerepairlaptop.blogspot.com
4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 17 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

1D5V_STR

1D5V_STR

D D
C25712
* 0.1uF *R363
1K VTT_DDR

16V, X7R, +/-10%

C148 C152 C144 C149 +/-1%
1uF 1uF 1uF 1uF
* * * *
10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

SMVREF_A_DDR3 SMVREF_A_DDR3
SMVREF_A_DDR3 16

*R364
1K * C151
0.1uF * C413
1uF * C504
0.1uF

16V, X7R, +/-10%

10V, X5R, +/-10%

16V, X7R, +/-10%

+/-1%

C404 C407 C5471 C5391

* 4.7uF * 4.7uF * 0.1uF * 0.1uF

16V, X7R, +/-10%

16V, X7R, +/-10%

c0805h14 c0805h14

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

close to DIMM pin close to DIMM pin
Channel A DIMM 1 1.5V high-frequency decoupling caps. Width 10 mils minimum, Spacing 10 mils minimum. Width 10 mils minimum, Spacing 10 mils minimum.
place as close to DIMM power pins as possible

1D5V_STR
Channel A VTT_0.75V Mid Range decoupling caps.
Placed in termination Island
1D5V_STR

C145
1uF
C146
1uF
C147
1uF
C150
1uF
*R3631
1K
+/-1% VTT_DDR
* * * *
10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

C * C2571
0.1uF SMVREFDQ_A
SMVREFDQ_A 16
C

16V, X7R, +/-10%

R3641 C1511 C4131 C5041
* 1K * 0.1uF * 1uF * 0.1uF

16V, X7R, +/-10%

10V, X5R, +/-10%

16V, X7R, +/-10%

+/-1%

* C523
4.7uF * C528
4.7uF * C5441
0.1uF * C5491
0.1uF

16V, X7R, +/-10%

16V, X7R, +/-10%

c0805h14 c0805h14

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

close to DIMM pin
Channel A DIMM II 1.5V high-frequency decoupling caps. Width 10 mils minimum, Spacing 10 mils minimum.
place as close to DIMM power pins as possible

1D5V_STR Channel B VTT_0.75V Mid Range decoupling caps.

1D5V_STR
Placed in termination Island

* C28412 *R365
1K
0.1uF +/-1%
16V, X7R, +/-10%

C378 C387 C380 C385

1uF 1uF 1uF 1uF SMVREF_B_DDR3 SMVREF_B_DDR3
* * * * SMVREF_B_DDR3 17
10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

R366 C386 C502 C505

B
* 1K * 0.1uF * 1uF * 0.1uF B
16V, X7R, +/-10%

10V, X5R, +/-10%

16V, X7R, +/-10%

+/-1%
VTT_DDR

Placed close to DIMM pin close to DIMM pin

Width 10 mils minimum, Spacing 10 mils minimum. Width 10 mils minimum, Spacing 10 mils minimum.
Channel B DIMM1 1.5V high-frequency decoupling caps.
place as close to DIMM power pins as possible

C5401 C5451 C5511

* 0.1uF * 0.1uF * 0.1uF

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

1D5V_STR
1D5V_STR

*R3651
1K
+/-1%
C2841
C383 C379 C384 C382 * 0.1uF SMVREFDQ_B
SMVREFDQ_B 17
16V, X7R, +/-10%

1uF 1uF 1uF 1uF

* * * *
10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

*R3661
1K * C2812
0.1uF * C4541
1uF * C5051
0.1uF
16V, X7R, +/-10%

10V, X5R, +/-10%

16V, X7R, +/-10%

+/-1%

A A

close to DIMM pin

Width 10 mils minimum, Spacing 10 mils minimum.

Channel B DIMM II 1.5V high-frequency decoupling caps.

place as close to DIMM power pins as possible Title

DDRIII Termination
DWG NO Rev
A01
Arrowhead

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www.advancerepairlaptop.blogspot.com 4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 18 of 45
 1D1V_MCH
5 4

Trung Tâm Máy Tính AV 3 2 1

12V_SYS

1D5V_ICH

C
3D3V_SB 2D5V_REF
5VDAUL_S3#O B Q103
20 5VDAUL_S3#O MMBT3904
R200
*0 1D5V_STR

E
+/-5% 5V_SB_SYS R1312
2D5V_REF 0
+/-5%

1
12V_SYS_C 3D3V_SYS
*
2 dummy
placed near LM358 pin 8 R664
*
1

C433 C469 C170 825 Ohm

* 10uF
* 1uF U19 2D5V_REF C168
* 0.1uF +/-1% R1536

D
dummy +/-10% 0.1uF 16V, X7R, +/-10%
* 12V_SYS_C
* U7C 33
2

3
D D

4
dummy TL431CDBZR 16V, X7R, +/-10% Q58
Dummy 2D4V_REF 10 2D4V
+ 8 G
R592
7.5K 9 NTD40N03R
-
+/-1%
*R665 C446
2A

S
2.2KOhm 0.1uF LM324
U3519A
*

11
8
Q18 +/-1% 16V, X7R, +/-10% C448
3 10nF
+ 1 G * 25V, X7R, +/-10%
2 NTD40N03R
-

S
*R590 * C167 LMV358IDR 1D1V_MCH_CL

*
3.74K 4.7uF C166 R666 1K
*
C

+/-1% c0805h14 1nF 3A

*

R205 10K B Q19 6.3V, X5R, +/-10% 50V, X7R, +/-10% EC25 C171
7,20,23,38 SLP_M
C172
MMBT3904
sot23_bech11
* 470uF
+/-20% * 0.1uF
16V, X7R, +/-10% 2D4V
E

1uF 1D5V_STR
*

*
10V, X5R, +/-10% R204 1K PRN50 PRN51
12V_SYS_C
Dummy
always stuff
*
1
3
2
4
2
4 * 13
5 6 6 5
7 8 8 7

placed near LM324 pin 4 0 +/-5% 0 +/-5%

2D5V_REF Dummy
C99
0.1uF
1.1V MCH CL linear regulator circuit. *
*R183
1.8KOhm
16V, X7R, +/-10%

*PR183

D
+/-1% U7A 1K

4
+/-1% Q20
3 PR470
2D4V_REF_1 Dummy 1D5V_ICH

*
+ 1 G
1D5V_STR C100 2 NTD40N03R
-
2D5V_REF R184 0.1uF +/-5% PR298
* * * 2A

S
FSB_VTT 1.5KOhm 16V, X7R, +/-10% LM324
0
10K

11
C 12V_SYS_C +/-1% C101 +/-1% C

*R215
16.2K * 10nF
25V, X7R, +/-10%
Dummy

D
+/-1% U7B EC26 C102

4
FSB_VTT_REF 5
Q22 * 470uF
+/-20% * 0.1uF
16V, X7R C103
*

*
+ 7 G
5V_SYS FSB_VTT R185 1K 10uF
6
FSB_VTT *R209
6.8K
*
C174
1uF
-
NTD40N03R c0805h14
6.3V, X5R, +/-20%

S
+/-1% 1D5V_ICH R208 +/-10% LM324
* R211 *

11
Dummy 9.31KOhm
+/-1% C175
* R213 1K
* 5.8A
C

Dummy 1nF
1K B Q23 50V, X7R, +/-10% EC31 EC32 C173
Dummy MMBT3904 1K 470uF * * 470uF
* 0.1uF
* C176
C

Dummy R117
* +/-20% +/-20% 16V, X7R 10uF 1D1V_MCH FSB_VTT 1D1V_MCH 1D05V_ICH
E
*

*
R210 750 B Q29 R214 1K c0805h14 RN49 0 RN50 0
10 VTT_SEL
Dummy
+/-1% MMBT3904 6.3V, X5R, +/-20%
*
1
3
2
4 *
1
3
2
4
E

Dummy 5 6 5 6
Q3037 7 8 7 8
MMDT5551
Dummy
* * *

470uF +/-20%
EC57

0.1uF 16V, X7R

C447

10uF6.3V, X5R, +/-20%

C449 c0805h14
1D1V_MCH FSB_VTT
3

RN51 0 RN48 0
3D3V_SB
*
1
3
2
4
1
3 * 2
4
5 6 5 6
R354 7 8 7 8
*

Dummy Dummy
4.7K
+/-5%

5V_SYS
B B
1

* L10 3D3V_SYS
Choke 500nH
2

C104 C135 C164 EC15 EC16

C96 1uF * 10uF

+/-10% * 1uF
* 10uF
+/-10%
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
*

5V_SYS 1D1V_MCH
16V, X7R, +/-10% 10V, X5R, +/-10%
D

12V_SYS U6 L6728TR R113 Q10

R193 2.2
+/-1%
6
VCC GND
5 * 39K
+/-5% G 1D1V_MCH C139 C141 C136
C165
10uF
C106
10uF
*R188 * *

6.3V, X5R, +/-20%

6.3V, X5R, +/-20%

7 4
COMP/DIS LGATE/OC
R1021 2.2 NTD40N03R
* 1uF
* 1uF
* 1uF

10V, X5R, +/-10%

10V, X5R, +/-10%

10V, X5R, +/-10%

+/-5% C510 C511
4.7K
* 22A
S

+/-5% 8 3 R203 2.2 R580 10uF 0.1uF

1D1V_MCH FB UGATE * *

6.3V, X5R, +/-20%

+/-5% 10K L9 Choke 1.5uH 16V, X7R, +/-10%
*

R187 2.2KOhm 9 2 +/-1% 2 1

12V_SYS VSEN PHASE
EPAD

+/-1%
10 1 R189 C95 0.1uF C93 EC17 EC18
*

PGOOD BOOT
5V_SYS
1D5V_ICH R191
2.2
+/-1% 16V, X7R, +/-10% C113 * 10uF
c0805h14
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
*
11

5.6K 1nF 6.3V, X5R, +/-20%

*
D

+/-1% 50V, X7R, +/-10%

R719 Q11 Q12

1K
*10K
+/-5% G G
D

*
R133 12V_SYS D5
R720 Q84 BAT54HT1G NTD40N03R NTD40N03R
*
S

S
*

A 10K R192 0 A C A
+/-5% G +/-5% R180
Dummy 2N7002-7-F 2.2
+/-5%
S

1D1V_MCH
C

C105 3.3nF R182 2.2KOhm

* *

B Q83 16V, NPO, +/-5% +/-1%

*

MMBT3904 R131 0
*

C92 10nF R194 8.2K C163 47nF R181 33 Ohm +/-5%

E

+/-1% 16V,X7R,+/-10% +/-1%

C473 25V, X7R, +/-10% Title
0.1uF
* 16V, X7R, +/-10% *R190
5.6K 1D1V/FSB_VTT/1D5V
Dummy +/-1%
Vout=Vref(1+R187/R191) Set OCP to 1.5 * Iccmax. DWG NO Rev
Vref=0.8V OCP= 10uA* Rocset / (Lowside Rdson) A01
Arrowhead

www.advancerepairlaptop.blogspot.com
Rocset =R113
Date: Wednesday, November 24, 2010 Sheet 19 of 45

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5 4 3 2 1
 3D3V_SB 5V_SYS
5

5V_DUAL 5V_SB_SYS
5V_SB_SYS
4

Trung Tâm Máy Tính AV 3

1D5V_STR
2 1

R483 R3921 R3922

*R481
8.2K
+/-5%
* 10K * 0 3.24KOhm
+/-5% +/-5% +/-1%
dummy dummy *R470
0
3D3V_SB

0 +/-5% +/-5%

*
13 8 R3907 C88 0.1uF VT_5078_PHASE

*
PGOOD BOOT 16V, X7R
4 9 VT_5078_HDRV
5VMAIN HDRV
14 10 C85
VCC SW 470pF
*

*
D D
R3915 0 +/-5% 17 11 R468 4.99K 50V, X7R
29,32 ATXPWRGD S3# I ISNS R469 Dummy C91 C186
23 SLP_S4J
18
EN LDRV
12 VT_5078_LDRV +/-1% *1.27K
* 4.7uF
* 0.1uF
+/-1% 6.3V, X5R 16V, X7R

*R472

*
R3919 0 +/-5% 1K
23,29 SLP_S3J
dummy +/-1%
Bosen Add 01/05 Dummy

5VDAUL_SBSW 3 23
3D3V_SB SBSW FB
15 22 C187
3.3 ALW COMP 4.7nF
5VDAUL_S3#O 16
S3# O
* +/-10%

C89 *R408
33KOhm *R296
1.82KOhm

* 47pF +/-1% +/-1%

50V, NPO, +/-5%

5VDUAL_USBSW 1 7

2
SBUSB# VDDQ IN
24
*R473
18K Dummy
C87
23,29 S4_STATEJ S4ST# REF IN
6 * 10nF *R484
1K
+/-1%

25V, X7R +/-1%

VTT OUT Dummy
C97 C181 C179 C182 C492 C489 5
VTT SNS
* 10uF
* 0.1uF
16V, X7R * 4.7uF
6.3V, X5R * 1uF
10V, X5R * 0.1uF
16V, X7R * 4.7uF
6.3V, X5R C86
c0805h14 10nF
6.3V, X5R, +/-20% * 25V, X7R *R216
1K
+/-1%
20 19 Dummy
ILIM GND
21 25
SS GND1

*R409 C180

+/-1% *
51K 0.1uF VTT_DDR
C 16V, X7R VTT_DDR C

U15
FAN5078D3MPX
DDR3 VTT Power

*
R475 0

+/-5%
C90 C189 EC38 PEC231 PEC23

* 0.1uF
16V, X7R * 4.7uF
6.3V, X5R
* 1000uF
+/-20%
* 470uF
+/-20%
* 470uF
+/-20% *R295
100 Ohm 3D3V_SB
+/-5%

5VDUAL_USB_Power Dummy
7,19,23,38 SLP_M
C428 C422 C158 EC33

*4.7uF * 0.1uF
* 1uF * 470uF

16V, X7R, +/-10%

10V, X5R, +/-10%

6.3V, X5R
+/-20%

5V_SB_SYS
X02 update * R197
8.2K
+/-5%
4

U5
*

4
5VDUAL_USBSW R591 1M 3 NTGS4111PT1G U9
+/-5% USB_DUAL 3 NTGS4111PT1G

Q47
1
2
5
6

2 C178
C159
*

1
2
5
6
3 2.2nF 1uF 3D3V_CL

C
*

1 10V, X5R, +/-10%

*
EC24 R198 10K B Q39 X02 update
D

23 WOL_ONLY
BAT54C
Q31 Q16
R406
560
R478
560
* 470uF
+/-20% +/-5%

E
+/-5% +/-5%
19 5VDAUL_S3#O
5VDAUL_S3#O G G Dummy Dummy MMBT3904 * C142
NTD40N03R NTD40N03R sot23_bech11 0.1uF
Dummy
S

B B

5V_SYS

5V_DUAL

* FB6 * FB8 DDR3Power 5VDUAL Power 5V_SB_SYS

FB 600 Ohm FB 600 Ohm 3D3V_SYS

12V_SYS

4
U4
5VDAUL_SBSW 3 NTGS4111PT1G

5V_DUAL
C184 C183 EC19 EC20 *R462
8.2K

* 1uF
* 10uF
* 470uF
* 1000uF +/-5%

1
2
5
6
10V, X5R, +/-10% +/-10% 6.3V, +/-20% +/-20%

S
C188
D

2.2nF G NTD40N03R
*

Q13 1D5V_STR
R3908
D EC23
VT_5078_HDRV
0 +/-5%
G
NTD40N03R
L11
Q15 R461 R460
* 470uF
+/-20%
Q14

D
1K 1K
S

VT_5078_PHASE 2 1 5VDAUL_S3#O G
+/-1% +/-1%
*

NTD40N03R
3D3V_SB
S

C185 Choke 1.5uH EC21 EC22 EC46 EC50 EC47 EC52 C177 Max. output current = 3A
A
* 1nF
50V, X7R, +/-10%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20%
* 1000uF
+/-20% * 10uF
c0805h14
A
D

6.3V, X5R, +/-20%

Q17
5V_SYS
VT_5078_LDRV G
NTD40N03R
S

R381
2.2
+/-5% Place 5 pcs between Ch A DIMM II Title
and Ch B DIMM 1 STR1D8V/3D3_DUAL/5V_DUAL
DWG NO Rev
Place 1pcs between GMCH and DIMM A01
Arrowhead

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Date: Wednesday, June 02, 2010
1
Sheet 20 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

D D

3D3V_SYS

2
3 Q56
BAV99
Fine Tune for filter option between bandwidth and EMI

1
L13

*
RED 1 2 R510 0
12 RED

R329,R324,R328 CLOSE TO CRT CONNECTOR, FB 47Ohm C251

R511 C252 3.3pF
THE TRACE IMPEDANCE BETWEEN TWO * *

2
150 10pF C248 50V, NPO, +/-0.25pF
150R RESISTORS SHOULD BE 50R+/-15% , +/ -1% * 50V, NPO, +/-5% * 3.3pF
THE TRACE IMPEDANCE BETWEEN 150R 3 Q45 50V, NPO, +/-0.25pF
RESISTOR AND CONNECTOR SHOULD BE BAV99
75R+/-15%

1
L14

*
GREEN 1 2 R538 0
12 GREEN
3D3V_SYS 12V_SYS 5V_SYS
FB 47Ohm C253
C239 3.3pF
*

2
DDCA_CLK AND DDCA_DATA
* R513 * R505 *R540
150 * 10pF
50V, NPO, +/-5% * C249
3.3pF
50V, NPO, +/-0.25pF

PULL-UP SUGGESTION FROM 2.2K 2.2K 3 Q43 +/ -1% 50V, NPO, +/-0.25pF
G

C BAV99 C
+/-5% +/-5%
INTEL 2.2K-3.6K-------
S D

1
12 DDCA_CLK
L15

*
2N7002-7-F BLUE 1 2 R539 0
Q33 12 BLUE

FB 47Ohm C247
5V_SYS
3D3V_SYS 12V_SYS C243
* 3.3pF

*R541
150
+/ -1%
* 10pF
50V, NPO, +/-5% * C250
3.3pF
50V, NPO, +/-0.25pF
50V, NPO, +/-0.25pF

* R509 * R515
2.2K 2.2K
G

+/-5% +/-5%
5V_SYS
S D
12 DDCA_DATA 5V_SYS
F3
2N7002-7-F FUSE_1.1A VGA_9D1
Q44 * C240

2
C237 0.1uF
5V_SYS * 0.1uF *
3 Q37 3 Q78 3 Q46 3 Q42 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
BAV99 BAV99 BAV99 BAV99

C241
*

1
0.1uF VGA_SERIAL1A
5

U11 16V, Y5V, +80%/-20% VGA

1 DAC_SCL_C R514 VGA_15 B15 SCL GND B5
4 +/-1% 100 B10 GND
12 3V_VSYNC 2 B14 VSYNC B4
5V_VSYNC +/-5% 0 R507 VSYNC_C ID0
GPI_VGA_CBL_DETJ 25
B9 NC
74AHCT1G08GW 5V_HSYNC +/-5% 0 R512 HSYNC_C B13 HSYNC B B3 VGA_B
3

B8 GND
DAC_SDAT_C R506 VGA_12 B12 SDA G B2 VGA_G
5V_SYS +/-1% 100 B7 GND
B B
B11 ID1 R B1 VGA_R
B6 GND
5

U12
1 CONN - Dual port

1
2
12 3V_HSYNC 4
2
C244 C236 C242 C238
74AHCT1G08GW 100pF 12pF 12pF 100pF
* * * *
3

50V, NPO, +/-5% 50V, NPO, +/-5%

50V, NPO, +/-5%
50V, NPO, +/-5%

A A

Title

VGA Connector
DWG NO Rev
A01
Arrowhead

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www.advancerepairlaptop.blogspot.com 4 3 2
Date: Friday, July 30, 2010
1
Sheet 21 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

3D3V_SYS

D D

follow Intel MOW51 * R1343

8.2K
Dummy +/-5%
23,30 PEG_PINB7_R R2011 +/-5%
0
12 PEG_PINB7 R2004 ** +/-5%
0 Dummy
X16_B4
R1344

*
X16_B4 PEG_PINB81_R

8.2K
+/-5%

R2017 +/-5%
Slot-PCIE-16X
0
**

R2016 +/-5%
0 Dummy

3D3V_SB 3D3V_SYS 12V_SYS 12V_SYS 3D3V_SYS

SLOT1

B1 A1
B2 12V1 PRSNT1# A2
B3 12V2 12V3 A3
X16_B4 R2015 +/-5% B4 RSVD8 12V4 A4
PCIE16_SCLK 0 B5 GND1 GND68 A5
* *

PCIE16_SDATA B6 SMCLK JTAG2 A6

SMDAT JTAG3 Modified in A01 1209 2008
R2014 +/-5% B7 A7
Dummy 0 B8 GND2 JTAG4 A8
C B9 3.3V3 JTAG5 A9 C
B10 JTAG1 3.3V1 A10 3D3V_SB
GPI_S1_WAKEJ B11 3.3VAUX 3.3V2 A11 SIO_G_PLTRSTJ
23 GPI_S1_WAKEJ WAKE# PWRGD SIO_G_PLTRSTJ 29

B12
B13 RSVD1
KEY

GND67
A12
A13 CK_PE_100M_P_16PORT
*R312 R311
4.7K *4.7K
+/-5% +/-5%
B14 GND3 REFCLK+ A14 CK_PE_100M_P_16PORT 7
EXP_TXP15 C232 0.1uF 16V, X7R, +/-10% EXP_TXP15_C CK_PE_100M_N_16PORT
CK_PE_100M_N_16PORT 7
**

12 EXP_TXP15 EXP_TXN15 EXP_TXN15_C B15 HSOP0 REFCLK- A15

C233 0.1uF 16V, X7R, +/-10% dummy dummy
12 EXP_TXN15 B16 HSON0 GND66 A16 EXP_RXP15
B17 GND4 HSIP0 A17 EXP_RXN15 EXP_RXP15 12
12 SDVO_CTRLCLK

*
B18 PRSNT2_B17# HSIN0 A18 EXP_RXN15 12 PCIE16_SCLK R573 0 +/-5%
GND5 GND65 SMB_CLK_RESUME 7,16,17,23,29,31

EXP_TXP14 C230 0.1uF 16V, X7R, +/-10% EXP_TXP14_C B19 A19

** ** **

12 EXP_TXP14 EXP_TXN14 EXP_TXN14_C B20 HSOP1 RSVD7 A20

C231 0.1uF 16V, X7R, +/-10%

*
12 EXP_TXN14 B21 HSON1 GND64 A21 EXP_RXP14 PCIE16_SDATA R572 0 +/-5%
B22 GND6 HSIP1 A22 EXP_RXP14 12 SMB_DATA_RESUME 7,16,17,23,29,31
EXP_RXN14
EXP_TXP13 EXP_TXP13_C B23 GND7 HSIN1 A23 EXP_RXN14 12
C228 0.1uF 16V, X7R, +/-10%
12 EXP_TXP13 EXP_TXN13 C229 0.1uF 16V, X7R, +/-10% EXP_TXN13_C B24 HSOP2 GND63 A24
12 EXP_TXN13 B25 HSON2 GND62 A25 EXP_RXP13
B26 GND8 HSIP2 A26 EXP_RXN13 EXP_RXP13 12
EXP_TXP12 C226 0.1uF 16V, X7R, +/-10% EXP_TXP12_C B27 GND9 HSIN2 A27 EXP_RXN13 12
12 EXP_TXP12 EXP_TXN12 C227 0.1uF 16V, X7R, +/-10% EXP_TXN12_C B28 HSOP3 GND61 A28
12 EXP_TXN12 B29 HSON3 GND60 A29 EXP_RXP12
B30 GND10 HSIP3 A30 EXP_RXN12 EXP_RXP12 12
B31 RSVD2 HSIN3 A31 EXP_RXN12 12
12 SDVO_CTRLDATA B32 PRSNT2_B31# GND59 A32
GND11 RSVD6 12V_SYS 3D3V_SYS 3D3V_SB
EXP_TXP11_GFX C224 0.1uF 16V, X7R, +/-10% EXP_TXP11_GFX_C B33 A33
30 EXP_TXP11_GFX
** ** ** **

EXP_TXN11_GFX C225 0.1uF 16V, X7R, +/-10% EXP_TXN11_GFX_C B34 HSOP4 RSVD5 A34
30 EXP_TXN11_GFX B35 HSON4 GND58 A35 EC27
EXP_RXP11 EC28

1
GND12 HSIP4 EXP_RXP11 12
EXP_TXP10_GFX C222 0.1uF 16V, X7R, +/-10% EXP_TXP10_GFX_C
B36
B37 GND13 HSIN4
A36
A37
EXP_RXN11
EXP_RXN11 12 * 220uF
+/-20% * C201
* 120uF
+/-20% * C202 * C203
30 EXP_TXP10_GFX B38 HSOP5 GND57 A38
EXP_TXN10_GFX C223 0.1uF 16V, X7R, +/-10% EXP_TXN10_GFX_C 0.1uF 0.1uF 0.1uF

2
30 EXP_TXN10_GFX B39 HSON5 GND56 A39 EXP_RXP10 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
B40 GND14 HSIP5 A40 EXP_RXN10 EXP_RXP10 12
B GND15 HSIN5 EXP_RXN10 12 B
EXP_TXP9_GFX C220 0.1uF 16V, X7R, +/-10% EXP_TXP9_GFX_C B41 A41
30 EXP_TXP9_GFX B42 HSOP6 GND55 A42
EXP_TXN9_GFX C221 0.1uF 16V, X7R, +/-10% EXP_TXN9_GFX_C
30 EXP_TXN9_GFX B43 HSON6 GND54 A43 EXP_RXP9_SW
B44 GND16 HSIP6 A44 EXP_RXN9_SW EXP_RXP9_SW 30
EXP_TXP8_GFX C218 0.1uF 16V, X7R, +/-10% EXP_TXP8_GFX_C B45 GND17 HSIN6 A45 EXP_RXN9_SW 30
30 EXP_TXP8_GFX B46 HSOP7 GND53 A46
EXP_TXN8_GFX C219 0.1uF 16V, X7R, +/-10% EXP_TXN8_GFX_C
30 EXP_TXN8_GFX B47 HSON7 GND52 A47 EXP_RXP8_SW
B48 GND18 HSIP7 A48 EXP_RXN8_SW EXP_RXP8_SW 30
12 EXP_PRSNT B49 PRSNT2_B48# HSIN7 A49 EXP_RXN8_SW 30
GND19 GND51

EXP_TXP7 C216 0.1uF 16V, X7R, +/-10% EXP_TXP7_C B50 A50

12 EXP_TXP7
** ** ** ** ** ** ** **

EXP_TXN7 C217 0.1uF 16V, X7R, +/-10% EXP_TXN7_C B51 HSOP8 RSVD4 A51
12 EXP_TXN7 B52 HSON8 GND50 A52 EXP_RXP7
B53 GND20 HSIP8 A53 EXP_RXN7 EXP_RXP7 12
EXP_TXP6 C214 0.1uF 16V, X7R, +/-10% EXP_TXP6_C B54 GND21 HSIN8 A54 EXP_RXN7 12
12 EXP_TXP6 B55 HSOP9 GND49 A55
EXP_TXN6 C215 0.1uF 16V, X7R, +/-10% EXP_TXN6_C
12 EXP_TXN6 B56 HSON9 GND48 A56 EXP_RXP6
B57 GND22 HSIP9 A57 EXP_RXN6 EXP_RXP6 12
EXP_TXP5 C212 0.1uF 16V, X7R, +/-10% EXP_TXP5_C B58 GND23 HSIN9 A58 EXP_RXN6 12
12 EXP_TXP5 B59 HSOP10 GND47 A59
EXP_TXN5 C213 0.1uF 16V, X7R, +/-10% EXP_TXN5_C
12 EXP_TXN5 B60 HSON10 GND46 A60 EXP_RXP5
B61 GND24 HSIP10 A61 EXP_RXN5 EXP_RXP5 12
EXP_TXP4 C210 0.1uF 16V, X7R, +/-10% EXP_TXP4_C B62 GND25 HSIN10 A62 EXP_RXN5 12
12 EXP_TXP4 B63 HSOP11 GND45 A63
EXP_TXN4 C211 0.1uF 16V, X7R, +/-10% EXP_TXN4_C
12 EXP_TXN4 B64 HSON11 GND44 A64 EXP_RXP4
B65 GND26 HSIP11 A65 EXP_RXN4 EXP_RXP4 12
EXP_TXP3 C208 0.1uF 16V, X7R, +/-10% EXP_TXP3_C B66 GND27 HSIN11 A66 EXP_RXN4 12
12 EXP_TXP3 HSOP12 GND43
12 EXP_TXN3 EXP_TXN3 C209 0.1uF 16V, X7R, +/-10% EXP_TXN3_C B67 A67
B68 HSON12 GND42 A68 EXP_RXP3
B69 GND28 HSIP12 A69 EXP_RXN3 EXP_RXP3 12
EXP_TXP2 EXP_TXP2_C B70 GND29 HSIN12 A70 EXP_RXN3 12
12 EXP_TXP2 C206 0.1uF 16V, X7R, +/-10%
EXP_TXN2 C207 0.1uF 16V, X7R, +/-10% EXP_TXN2_C B71 HSOP13 GND41 A71
12 EXP_TXN2 HSON13 GND40
B72 A72 EXP_RXP2
B73 GND30 HSIP13 A73 EXP_RXN2 EXP_RXP2 12 X16_Latch
EXP_TXP1 C204 0.1uF 16V, X7R, +/-10% EXP_TXP1_C B74 GND31 HSIN13 A74 EXP_RXN2 12
12 EXP_TXP1 HSOP14 GND39
EXP_TXN1 C205 0.1uF 16V, X7R, +/-10% EXP_TXN1_C B75 A75
12 EXP_TXN1 HSON14 GND38
A B76 A76 EXP_RXP1 A
B77 GND32 HSIP14 A77 EXP_RXN1 EXP_RXP1 12 G G
GND33 HSIN14 EXP_RXN1 12

2
12 EXP_TXP0 EXP_TXP0 C199 0.1uF 16V, X7R, +/-10% EXP_TXP0_C B78 A78
EXP_TXN0 C200 0.1uF 16V, X7R, +/-10% EXP_TXN0_C B79 HSOP15 GND37 A79 CONN-PCIE-RM
12 EXP_TXN0

2
B80 HSON15 GND36 A80 EXP_RXP0
*

R2012 1K B81 GND34 HSIP15 A81 EXP_RXN0 EXP_RXP0 12

24,30 PEG_PINB81_R B82 PRSNT2_B81# HSIN15 A82 EXP_RXN0 12
Dummy +/-5%
RSVD3 GND35

Slot-PCIE-16X
Title

PCI-E 16X / 1X Slot

DWG NO Rev
A01
Arrowhead

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www.advancerepairlaptop.blogspot.com
4 3 2
Date: Friday, July 30, 2010
1
Sheet 22 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

*
*
3D3V_SB 3D3V_SYS R2372 10K MFG_MODE
R236 10K L_DRQ1J
3D3V_SYS SERVICE_MODE

2
4.7K R336 ICH_SPI_MOSI 1
3D3V_CL
2

*
+/-5% Q30
* R397 dummy R238 10K L_DRQ0J BAT54C
1K
dummy
TPM_PHY_PRNT
* R393
FVS
Header_1X2
1K

3
dummy R3112 10K GPI_SRVC_MODE_OVERRIDE
3D3V_SB
1 L_DRQ1J
1
*R395
4.7K
+/-5%
ICH10 dummy
ICH10
TEST POINT L_DRQ1J J3
DMI_TXN0 W28 AD6 L_AD0 K3 LDRQ1B_GP23 N7 PECI_REQ#
12 DMI_TXN0 W26 DMIORXN USBP0N AD5 USB0N 37 29,34 L_AD0 H1 FWH0/LAD_0 GP0 PECI_REQ# 29
DMI_TXP0 L_AD1
12 DMI_TXP0 V30 DMIORXP USBP0P AE3 USB0P 37 29,34 L_AD1 M7 FWH1/LAD_1
DMI_RXN0 Front Panel L_AD2
D 12 DMI_RXN0 V29 DMIOTXN USBP1N AE2 USB1N 37 29,34 L_AD2 J1 FWH2/LAD_2 D
DMI_RXP0 L_AD3

*
12 DMI_RXP0 DMI_TXN1 AA26 DMIOTXP USBP1P AD1 USB1P 37 29,34 L_AD3 L6 FWH3/LAD_3 A20 R4101 33+/-5%
12 DMI_TXN1 DMI1RXN USBP2N USB2N 35 29 L_DRQ0J LDRQ0B GP8 DDR3_DRAM_PWROK 13
DMI_TXP1 AA28 AD2 L5 A18 WOL_ONLY
12 DMI_TXP1 Y30 DMI1RXP USBP2P AB6 USB2P 35 29,34 L_FRAMEJ FWH4/LFRAMEB GP9_WOL_EN C17 WOL_ONLY 20
DMI_RXN1 USB Header CPU_SKTOCC#

LPC
12 DMI_RXN1 Y29 DMI1TXN USBP3N AB5 USB3N 35 GP10/CLGPIO1 A8 CPU_SKTOCC# 10,29

**
DMI_RXP1
12 DMI_RXP1 DMI_TXN2 AC26 DMI1TXP USBP3P AC3 USB3P 35 R241 33 ICH_AUD_BCLK_R AH3 GP12 A19 GPI_WAKE_S4# GPIO_LAN_DISABLEJ 27
12 DMI_TXN2 AC28 DMI2RXN USBP4N AC2 USB4N 36 28 ICH_AUD_BCLK AJ1 HDA_BIT_CLK GP13 A9
DMI_TXP2 R240 33 ICH_AUD_RSTJ_R
12 DMI_TXP2 GPI_NB_HS_DETJ 15

DMI
DMI_RXN2 AB30 DMI2RXP USBP4P AB1 USB4P 36 Rear Panel 1 28 ICH_AUD_RSTJ AK3 HDA_RSTB GP14_CLGPIO2 C15
12 DMI_RXN2 AB29 DMI2TXN USBP5N AB2 USB5N 36 AH4 HDA_SDI0 STP_PCIB/GP15 M2 CK_PCI_STOP 7
DMI_RXP2
PEG_PINB7_R 22,30

**
12 DMI_RXP2 DMI_TXN3 AF26 DMI2TXP USBP5P Y6 USB5P 36 AH1 HDA_SDI1 GP16 K1 R407 0 +/-5% dummy

AUDIO
12 DMI_TXN3 AE26 DMI3RXN USBP6N Y5 USB6N 36 28 ICH_AUD_SDIN2 AJ3 HDA_SDI2 GP18 AF5 CPU_GTLREF_CTRL2 9

**
DMI_TXP3 R596 0 +/-5%
12 DMI_TXP3 AD29 DMI3RXP USBP6P AA3 USB6P 36 AJ2 HDA_SDI3 GP20 A14
DMI_RXN3 Rear Panel 2 R242 33 ICH_AUD_SDOUT_R
12 DMI_RXN3 AD30 DMI3TXN USBP7N AA2 USB7N 36 28 ICH_AUD_SDOUT AK1 HDA_SD0UT GP24/MEM_LED B18 GPI_FLOPPY_DETECTJ 37
DMI_RXP3 R243 33 ICH_AUD_SYNC_R CK_CPU_STOP 7
12 DMI_RXP3 DMI3TXP USBP7P Y1 USB7P 36 28 ICH_AUD_SYNC M5 HDA_SYNC STP_CPUB/GP25 C11 S4_STATEJ
USBP8N USB8N 36 7 CK_14M_ICH CLK14 GP26_S4_STATEB S4_STATEJ 20,29
Y2 A11
D29 USBP8P V6 USB8P 36 GP27_QRT_STATE0 G18 GPI_SKU2 24
HSI_N6 Rear Panel 3
To LAN 27 HSI_N6 HSI_P6 D30 PER6N_GLAN_RXN USBP9N V5 USB9N 36 F25 GP28_QRT_STATE1 K2
27 HSI_P6 E26 PER6N_GLAN_RXP USBP9P W2 USB9P 36 27 ICH_LAN_JCLK E14 GLAN_CLK GP32 AF6 GPI_SKU0 24
HSO_N6 MFG_MODE
PER6N_GLAN_TXN USBP10N TP80 27 ICH_LAN_JRSTSYNC LAN_RSTSYNC GP33
HSO_P6 E28 W3 LAN_PWROK C21 AH5 GPI_ICH_HS_DETJ
P30 PER6N_GLAN_TXP USBP10P V1 TP86 G15 LAN_RSTB GP34 L1
PER1N USBP11N TP87 27 ICH_LAN_JRX0 LAN_RXD0 SATACLKREQB_GP35 X8_PCIE_DET# 12
P29 V2 H14 F16 GPI_SRVC_MODE_OVERRIDE

USB
PER1P USBP11P TP88 27 ICH_LAN_JRX1 LAN_RXD1 GP56
R26 E13 C12 TPM_PHY_PRNT
PET1N 27 ICH_LAN_JRX2 LAN_RXD2 CLGPIO5_GP57
R28 F15 AD23 CPU_PWRG

LAN
PET1P 27 ICH_LAN_JTX0 LAN_TXD0 CPUPWRGD CPU_PWRG 10
M30 F14 E21 ICH_LAN100SLP_EN
PER2N 27 ICH_LAN_JTX1 LAN_TXD1 LAN100_SLP
M29 G14 AK26 ICH_THRM
PER2P 27 ICH_LAN_JTX2 LAN_TXD2 THRMB ICH_THRM 24
N26 P5 C22 ICH_VRMPWRGD
N28 PET2N OC0B_GP59 N3 USB_OCJ_FRONT_1 37 ICH_RTCX1 A21 VRMPWRGD AH25 ICH_SYNCJ_R
K30 PET2P OC1B_GP40 P7 ICH_RTCX2 B21 RTCX1 MCH_SYNCB T3
K29 PER3N OC2B_GP41 R7 USB_OCJ_FRONT_2 35 A25 RTCX2 PWRBTNB G19 PWR_BTN# 29,37
RTCRSTJ L_PMEJ
PER3P OC3B_GP42 24,32 RTCRSTJ RTCRSTB RIB L_PMEJ 29

RTC
L26 N2 SRTCRSTB H20 R1 LPCPDJ
L28 PET3N OC4B_GP43 N1 USB_OCJ_BACK_1 36 SRTCRSTB SUS_STATB/LPCPD R5 LPCPDJ 29
TP_SUSCLK
H30 PET3P OC5B_GP29 N5 SUSCLK F19 TP24
FP_RSTJ

MISC
H29 PER4N OC6B_GP30 M1 USB_OCJ_BACK_2 36 GPI_S1_WAKEJ C16 SYS_RESETB C14 PLTRSTJ FP_RSTJ 10,34,37
J26 PER4P OC7B_GP31 P3 22 GPI_S1_WAKEJ H16 SMBALERTB_GP11 PLTRSTB E20 WAKEJ PLTRSTJ 26
J28 PET4N OC8B_GP44 R6 USB_OCJ_BACK_LAN 36 7,16,17,22,29,31 SMB_CLK_RESUME E16 SMBCLK WAKEB G21

*
INTRUDERJ
F30 PET4P OC9B_GP45 T7 7,16,17,22,29,31 SMB_DATA_RESUME F18 SMBDATA INTRUDERB C25 INTRUDERJ 32
R517 3D3V_SB PWRGD_3V

**
F29 PER5N OC10B_GP46 P1 9 CPU_GTLREF_CTRL1 SMLINK0 A15 LINKALERTB/GP60/CLGPIO4 PWROK F22 ICH_RSMRSTJ PWRGD_3V 12,29,30
10K 3D3V_SB R245 10K
C G26 PER5P OC11B_GP47 R246 10K SMLINK1 B15 SMLINK0 RSMRSTB E23 INTVRMEN C
PCI-E

1D5V_PE_ICH G28 PET5N SMLINK1 INTVRMEN N8 SPKR

SMB
PET5P SPKR SPKR 32
R247
AG1 USBRBIAS_ICH 22.6
R248 24.9 DMI_COMP_ICH AF28 USBRBIASN AG2 +/-1% USBRBIAS connection ICH_SPI_MOSI C26 A13 SLP_S3J
AF30 DMIRCOMPO USBRBIASP 37 ICH_SPI_MOSI B26 SPI_MOSI SLP_S3B B13 SLP_S3J 20,29
+/-1% 4 mils width, length no longer than 500 mils ICH_SPI_MISO SLP_S4J
DMICOMPI 37 ICH_SPI_MISO E25 SPI_MISO SLP_S4B G17 SLP_S4J 20
Trace tied together close to pins. ICH_SPI_CS0J SLP_S5J
37 ICH_SPI_CS0J TP25

** *
CK_DMI_N_ICH U26 ICH_SPI_CLK G23 SPI_CS0B SLP_S5B/GPIO63 F17 R345 0 ICH_SLP_M_N
7 CK_DMI_N_ICH U25 DMICLK100N AG3 37 ICH_SPI_CLK F23 SPI_CLK SLP_MB T8
CK_DMI_P_ICH CK_48M_ICH ICH_SPI_CS1J CK_PWRGD

SP1
7 CK_DMI_P_ICH DMICLK100P CLK48 CK_48M_ICH 7 SPI_CS1B/GPIO58/CLGP6 CK_PWRGD C13 CK_PWRGD 7
GP72 AK28 GPI_SKU3 24
R343 0
2 OF 6 3D3V_SB DPRSTPB
DPSLPB
AE24 R344 0
PM_DPRSTP#
DPSLP#
10,12
10,29
ICHB F20 TP_ICH_3 TP28
TP3
4 of 6
*R252
300
X02 update
3D3V_SB +/ -1% ICHD
1D5V_ICH
3D3V_SYS
3D3V_SYS SLP_M 7,19,20,38
*R250

****
R262 X8_PCIE_DET# R2010 10K
* *

dummy 3.3KOhm ICH_AUD_SDOUT_R PECI_REQ# R2009 10K

*

D
10K R251 +/-1% Dummy 3D3V_CL R2005 10K
22,30 PEG_PINB7_R
1K R263 Q24 GPI_ICH_HS_DETJ R667 10K
WOL_ONLY dummy 3.3KOhm ICH_AUD_SYNC_R 2N7002-7-F
+/-1% Dummy 10K R258 G
29 ICH_SLP_M_N *R264 3D3V_SB
*

*
R254 0 +/-5% ICH_SYNCJ_R 32.4K Ohm
* 12 ICH_SYNCJ

** ***
R256 C254 +/-1% L_PMEJ R280 10K

S
100KOhm 1uF CPU_SKTOCC# R259 10K
ICH10 Hardware Straps *

*
10V, X5R, +/-10%
+/-1% LAN_PWROK R401 GPI_NB_HS_DETJ R260 10K
1K
dummy C259 GPI_FLOPPY_DETECTJ R1669 10K

D
PWRGD_3V 1uF VCCRTC CPU_GTLREF_CTRL1 R1670 10K
*

10V, X5R, +/-10%

ICH_AUD_SDOUT_R Q111
2N7002-7-F VCCRTC
SLP_M G
R1278 3D3V_SB R257 *

**
ALL AC Coupling caps. should be close to ICH10 R1279
* 10K 180K R265 330K INTVRMEN

S
B * B
10K +/-1%
R266 330K ICH_LAN100SLP_EN
X02 update * 10K
R2018
X02 update SRTCRSTB
INTVRMEN: enable internal VccSus1_05, VccSus1_5 and
C255 VccCL1_5 regulators when connect to VccRTC
0.1uF
3D3V_SB * LAN100_SLP: enable internal VccLAN1_05 and
2N7002-7-F VccCL1_05 regulators when connect to VccRTC
2N7002-7-F Q113

D
Q112

*
*

R271 R272 0 +/-5% 3D3V_SB

1K dummy WOL_ONLY G G
dummy

*****
Q25 R273 1K WAKEJ

S
C261 E MMBT3906
C ICH_RSMRSTJ
29 SIO_RSMRSTJ
HSO_N6 R274 10K GPI_S1_WAKEJ
* *

27 HSO_N6_LAN 0.1uF 16V, X7R, +/-10% To LAN 3D3V_SB

*

C263 R276 R277 10K GPI_WAKE_S4#

B

* *
C262 HSO_P6 1uF R275 10K SMLINK1 R268 0 +/-5%SMB_DATA_RESUME
27 HSO_P6_LAN * 10V, X5R, +/-10% 4.7K
* 3D3V_SYS 3D3V_SB dummy R278 10K DDR3_DRAM_PWROK
1

dummy +/-5% Dummy

0.1uF D7 SMLINK0 R270 0 +/-5%SMB_CLK_RESUME R283 10K ICH_SPI_CS1J
16V, X7R, +/-10% Place near ICH10 3 dummy
*R281 *R282 dummy for second SPI
for reset issue when testing BAV99 10K 10K
place near ICH10 dummy ICH_AUD_BCLK
1 2

VCCRTC

ICH_RTCX2 All RTC-well inputs(RSMRST#,RTCRST#,INTRUDER#,PWROK) D8

must either pull up to VccRTC or pulled down 3 BAV99
* C264 3D3V_SB 3D3V_SYS * C265 1M
to ground while in G3 for preventing from dummy 0.1uF 22pF +/-5% *
ICH_RTCX1
R284
floating in G3 and will prevent IccRTC leakage *R287
2.2K
16V, Y5V

* *
50V, NPO R288
2

10M that can cause excessive +/-5% R285 R286 INTRUDERJ

coin-cell drain. ICH_VRMPWRGD 29
+/-5% 1K 1K
C

Q26 dummy
A B MMBT3904 A
XTAL 32.768KHz sot23_bech11
sot23_bech11
C
E

X2 MMBT3904
1 4 B Q27
* C266 * R289
C267 C268 1uF 100KOhm
E
2

10pF 10pF +/-1%

* 50V, NPO, +/-5% * 50V, NPO, +/-5%
16V, X7R, +/-10%
*

SLP_S3J R290 10K

dummy Title

ICH10 -1
*

R291 10K
8,10 P_VRM_GD
DWG NO Rev
*

R292 0 +/-5% A01

dummy Arrowhead

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www.advancerepairlaptop.blogspot.com
4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 23 of 45
 5

ICH10
4

Trung Tâm Máy Tính AV 3 2

ID2
1

CHASSIS ID

ID1 ID0 NAME

SATA0RXN
AK17
AJ17
SATA_RXN0
SATA_RXP0 SATA_TXP0 C269 10nF 25V, X7R SATA_TXP0_C 2
SATA_0 SATA0 0 0 0 CYPHER

** **
SATA0RXP TX+
4 mils width, length no longer than 500 mils SATA0TXN
AK19
AJ19
SATA_TXN0
SATA_TXP0 SATA_TXN0 C270 10nF 25V, X7R SATA_TXN0_C 3 BLUE 0 0 1 NEO
SATA0TXP AJ15 SATA_RXN1 TX-
Trace tied together close to pins.
SATA1RXN 0 1 0 SMITH
AK15 SATA_RXP1 8
1D5V_PE_ICH SATA1RXP AH16 SATA_TXN1 SATA_RXN0 C271 10nF 25V, X7R SATA_RXN0_C 5 NC#8
SATA1TXN AF16 SATA_TXP1 RX- 3D3V_SYS
SATA1TXP AJ13 SATA_RXN2 SATA_RXP0 C272 10nF 25V, X7R SATA_RXP0_C 6
SATA2RXN AK13 SATA_RXP2 RX+ 9
R293 24.9 +/-1% A29 SATA2RXP AH14 SATA_TXN2 NC#9
B29 GLAN_COMPO SATA2TXN AF14 SATA_TXP2 1
D 12 CL_CLK
G22
C18
GLAN_COMPI
CL_CLK0
SATA2TXP
SATA3RXN
AJ11
AK11
SATA_RXN3
SATA_RXP3
4
7
GND
GND#4
*R396 *R418 *R427 D
10K 10K 10K
TP29 H21 TP5 SATA3RXP AF12 GND#7
SATA_TXN3 Dummy Dummy Dummy
12 CL_DATA E19 CL_DATA0 SATA3TXN AH12 SATA_TXP3 CONN-SATA
TP30 C27 TP4 SATA3TXP AJ9
CL_VREF_ICH GPI_CHASSIS_ID0
CL_VREF0 SATA4RXN

SATA
A16 AK9 SATA_1 GPI_CHASSIS_ID1
TP31
MCH_CLPWROK_R T6 TP6 SATA4RXP AF10 SATA_TXP1 C273 10nF 25V, X7R SATA_TXP1_C 2 SATA1 GPI_CHASSIS_ID2

** **
12 MCH_CLPWROK_R B16 CLPWROK SATA4TXN AH9 TX+
TP32 TP7 SATA4TXP
12 CL_RST
CL_RST G20
CL_RST0b SATA5RXN
AJ7
AK7
SATA_RXN5
SATA_RXP5
SATA_TXN1 C274 10nF 25V, X7R SATA_TXN1_C 3
TX- BLACK R2346 R2347 R2349
SATA5RXP AF8 SATA_TXN5 8
* 220
* 220
* 220
SATA5TXN AH7 SATA_TXP5 SATA_RXN1 C275 10nF 25V, X7R SATA_RXN1_C 5 NC#8
SATA5TXP AF18 CK_SATA_100M_N_ICH RX-
SATACLKN AF19 CK_SATA_100M_N_ICH 7 6
CK_SATA_100M_P_ICH SATA_RXP1 C276 10nF 25V, X7R SATA_RXP1_C
AJ21 SATACLKP CK_SATA_100M_P_ICH 7 RX+ 9
AJ22 PWM0 NC#9
AK22 PWM1 AE7 SATA_LED 1
PWM2 SATALEDB AK6 SATARBIAS_ICH R297 24.9 +/-1% 4 GND BOARD REV ID
*

R1573 10K AUDIO_CBL_DETJ_NC AH21 SATARBIASN AJ6 7 GND#4

NC_FIOUSB2_CBL_DETJ AK21 GP17_TACH0 SATABIASP GND#7 REV1 REV0 BOARD TYPE
NC_FIOUSB1_CBL_DETJ AH22 GP1_TACH1 CONN-SATA
GP6_TACH2 0 0 Default
GPI_SKU1 AK23 AK25 GPI_BRD_REV0 SATA_2
GP7_TACH3 GP21_SATA0GP AE20 GPI_ESATA_DETECTJ SATA_TXP2 C277 10nF 25V, X7R SATA_TXP2_C 2 SATA2 0 1 Reserved

** **
GP19_SATA1GP AE21 GPI_CHASSIS_ID0 TX+
GP36_SATA2GP
GP37_SATA3GP
AE22
AF22
GPI_CHASSIS_ID1
SATA4GP_PU
SATA_TXN2 C278 10nF 25V, X7R SATA_TXN2_C 3
TX- WHITE 1 0 Reserved
C19 SATA4GP AD21 SATA5GP_PU 8
SST SATA5GP SATA_RXN2 C279 10nF 25V, X7R SATA_RXN2_C 5 NC#8 1 1 TCM
RX-
X02 update
P8 SATA_RXP2 C280 10nF 25V, X7R SATA_RXP2_C 6
A20GATE AJ28 A20GATE 29 RX+ 9 3D3V_SYS
A20Mb A20MJ 10 NC#9
AC22 1 X02 update
IGNNEb M3 IGNNEJ 10 4 GND
INT3_3VB AE23 INIT3_3# 34 7 GND#4
GPI_BRD_REV1 AJ24
GP22_SCLOCK
INTb
INTR
AH27 INITJ
INTR
9
10
GND#7 *R2324 *R3334

HOST
3D3V_SYS GPI_CHASSIS_ID2 AK24 AJ27 CONN-SATA 10K 10K
AH23 GP38_SLOAD FERRb AF24 FERRJ 10
dummy dummy
C
22,30 PEG_PINB81_R AD20 GP39_SDATAOUT0 NMI L3 NMI
KBRSTJ
10
29
SATA_3 SATA3 GPI_BRD_REV1 POP9 POP9 C
*

32 PSWD_CLR R1574 2.2K AJ25 GP48_SDATAOUT1 RCINb N6 SATA_TXP3 C281 10nF 25V, X7R SATA_TXP3_C 2 GPI_BRD_REV0
*R2006 SERIRQ 29,34

** **
GPIO49 SERIRQ TX+
10K
+/-5%
dummy
SMIb
AH26
AJ29 STPCLKB
SMIJ 10
SATA_TXN3 C282
Dummy
10nF 25V, X7R SATA_TXN3_C 3 BLACK
Dummy STPCLKb AD24 Dummy TX- R2001 R2334
3 OF 6 THERMTRIPJ 10

*
THRMTRIPB AC23 R302 0 +/-5% 8
PECI PECI 10,29 5 NC#8 * *
dummy SATA_RXN3 C283 10nF 25V, X7R SATA_RXN3_C 220 220
PEG_PINB81_R 22,30 RX-
ICHC Dummy
SATA_RXP3 C284 10nF 25V, X7R SATA_RXP3_C 6
Dummy RX+ 9
NC#9
1
3D3V_CL 3D3V_SYS 4 GND
7 GND#4
**

dummy
INIT3_3# R385 10K GND#7 Dummy
SKU2 SKU1 SKU0 BOARD TYPE
CONN-SATA
R303 GPI_ESATA_DETECTJ R317 10K
0 0 0 ROW
@Cypher. NEO Dummy SATA_3, SATA_2
**

3.24KOhm 0.405V
+/-1% NC_FIOUSB2_CBL_DETJ R1013 10K C281, C282, C283, C284,C277,C278,C279,C280 0 0 1 TCM
NC_FIOUSB1_CBL_DETJ R1012 10K
CL_VREF_ICH
0 1 0 None
R304
0 1 1 Reserved
453 C289
+/-1% dummy * 0.1uF
1 X X Reserved
16V, Y5V
X02 update
4 mils width, 10 mils spacing
place cap. near pin 3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS

NOTE: ESATA1 IS REAR PANEL eSATA CONNECTOR

*R340 *R2576 *R2313 * R307 * R1311
10K
10K 10K 10K 10K
*R339

*
R2008 0 +/-5% dummy dummy dummy Dummy
10K GPI_SKU1
C

FSB_VTT ICH_THRM 23
Dummy dummy
B 23 GPI_SKU0
B
Q69 eSATA1 B
23 GPI_SKU2

*
MMBT3904 8 P1 R2007 0 +/-5% GPI_ESATA_DETECTJ
C

23 GPI_SKU3
**

9 P2

*
R309 62 THERMTRIPJ sot23_bech11 SATA_TXP5_C C452 10nF SATA_TXP5
E
*

B 10 P3

**
R335 10K Q70 Dummy SATA_TXN5_C 25V, X7R C453 10nF SATA_TXN5
R323 62 FERRJ 8,10,29 PROCHOTJ MMBT3904 11 P4 25V, X7R R2577 R2013 R2335
Dummy sot23_bech11 P5 SATA_RXP5_C C455 10nF SATA_RXN5 R2582
E

P6
* * *

*
Dummy SATA_RXN5_C C454 10nF 25V, X7R SATA_RXP5 220 220 220
P7 25V, X7R
* 220

3D3V_SYS
*

R69 0 +/-5%
dummy 3D3V_SYS
This Circuit will follow fleming design
(R1311 pin 2 connect to 3D3V_SB)
* *

R306 10K SATA4GP_PU

on version that will change LAYOUT FILE
3D3V_SYS
R308 10K SATA5GP_PU *R315
10K

29 ICH_SATA2_HDLEDJ
*R269
4.7K
+/-5%

*
SATA_LED R51 1K

3D3V_SB

VCCRTC
Q28
3D3V_SYS
VCCRTC_SIO 2 width 20 mils
D10 3
C A 1 HDD_LED 37
*R267

3
3D3V_SYS 4.7K
BAT54C
1N4148W *R321
20K
+/-5%
*

R305 10K AUDIO_CBL_DETJ_NC +/-1%

dummy BAT1_1 Q3040
C290 MMDT5551

4
Empty when using ICH10 FSC 1uF
A
* * A
*

R314 10K PSWD_CLR LITHIUM BATT R322 10V, X5R, +/-10%

1K c0603h9 RTCRSTJ
RTCRSTJ 23,32
Battery C291
1uF
* 10V, X5R, +/-10%
+

c0603h9
For battery cell. BATTERY
Battery Holder
Title
-

ICH10 -2
*

STPCLKB 0
STPCLKJ 10
R576 DWG NO Rev
A01
Arrowhead

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Date: Wednesday, June 02, 2010
1
Sheet 24 of 45
 5 4

Trung Tâm Máy Tính AV 3D3V_SB

*R530
237Ohm
3

REF5V_SUS
2 1

+/-1% REF5V 3D3V_CL

dummy
ICH10
VccSusHDA B23
A6 VccCL3_3_2 C23
ICH10 AD[31..0] 3D3V_SB V5REF VccCL3_3_1
AD[31..0] 31 AF1
31 PAR
PAR E3
C6 PAR AD_0
C10
C8
AD0 *R519
200
A26
V5REF_Sus
Vcc1_5_A_25
AA7
AA8
1D5V_ICH * C292
0.1uF
DEVSELJ AD1 +/-1% VccCL1_5
31
7
DEVSELJ
CK_33M_ICH CK_33M_ICH B3
R2
DEVSELB
PCICLK
AD_1
AD_2
E9
C9
AD2
AD3
dummy *R714
0
VccCL1_05 A23
VccCL1_5 Vcc1_5_A_26
Vcc1_5_A_27
AB7
AB8
16V, Y5V

+/-5%
IRDYJ J8 PCIRSTB AD_3 A5 AD4 1D5V_ICH VccCL1_05 Vcc1_5_A_28 T1
31 IRDYJ IRDYB AD_4 Vcc1_5_A_29
PMEJ R3 E12 AD5 VccSusHDA AC9 AC14
31 PMEJ K5 PMEB AD_5 E10 VccSusHDA Vcc1_5_A_30 AC15
SERRJ AD6
D 31 SERRJ SERRB AD_6 Vcc1_5_A_31 1D05V_ICH D
STOPJ F10 B7 AD7 VccHDA AC10 AC16
31 STOPJ STOPB AD_7 VccHDA Vcc1_5_A_32
LOCKJ H8 B6 AD8
31 LOCKJ PLOCKB AD_8
TRDYJ E6 B4 AD9 VccCL1_5 VCCSATAPLL AK5 A24
31 TRDYJ TRDYB AD_9 VccUSBPLL Vcc1_05_1
PERRJ F5 E7 AD10 B24
31 PERRJ PERRB AD_10 Vcc1_05_2
FRAMEJ G12 A4 AD11 AK20 C24
31 FRAMEJ FRAMEB AD_11 VccSATAPLL Vcc1_05_3
H12 AD12 C293 E24
AD_12 F8 AD13 * 0.1uF VCCDMIPLL T30 Vcc1_05_4 F24

PCI Slot
31,34 GNT0J
H5
A7 GNTB0
PCI AD_13
AD_14
AD_15
C5
D2
E5
AD14
AD15
AD16
16V, Y5V
VCCGLANPLL A28
VccDMIPLL

VccGLANPLL
Vcc1_05_5
Vcc1_05_6
Vcc1_05_7
G24
H23
H24
31 GNT1J GNTB1_GP51 AD_16 Vcc1_05_8
C7 G7 AD17 VccCL1_05 B10 J23
F7 GNTB2_GP53 AD_17 E11 AD18 C294 A10 VccLAN1_05_2 Vcc1_05_9 M12
GNTB3_GP55 AD_18
AD_19
G10 AD19
* C295 * 0.1uF VccLAN1_05_1 Vcc1_05_10
Vcc1_05_11
M13
G6 AD20 0.1uF 16V, Y5V M15
PCI Slot K7 AD_20 D3 AD21 16V, Y5V C30 Vcc1_05_12 M17
31 PREQ0J REQB_0 AD_21 VccGLAN1_5_1 Vcc1_05_13
31 PREQ1J
G13 H6 AD22 C29 M18
F13 REQB1_GP50 AD_22 G5 AD23 C28 VccGLAN1_5_2 Vcc1_05_14 M19
31 PREQ2J REQB2_GP52 AD_23 1D5V_PE_ICH VccGLAN1_5_3 Vcc1_05_15
G8 C1 AD24 B30 N12
31 PREQ3J REQB3_GP54 AD_24 VccGLAN1_5_4 Vcc1_05_16
C2 AD25 N19
AD_25 C3 AD26 Vcc1_05_17 R12
J5 AD_26 D1 AD27 1D5V_PE_ICH Vcc1_05_18 R19
31 INTAJ PIRQAB AD_27 Vcc1_05_19
E1 J7 AD28 VccSusHDA U12
31 INTBJ PIRQBB AD_28 Vcc1_05_20
GNT0J F1 F3 AD29 AA23 U19
31 INTCJ PIRQCB AD_29 Vcc1_5_B_1 Vcc1_05_21
A3 G1 AD30 AA24 V12
31 INTDJ
31 GPI_RISER_ID0
K6 PIRQDB
GP2_PIRQEB
AD_30
AD_31
H3 AD31 * C351 AA25 Vcc1_5_B_2
Vcc1_5_B_3
Vcc1_05_22
Vcc1_05_23
V19
L7 0.1uF AB24 W12
31 GPI_RISER_ID1 F2 GP3_PIRQFB F11 AB25 Vcc1_5_B_4 Vcc1_05_24 W13
CBEJ0
* R301
21 GPI_VGA_CBL_DETJ
35 USB_HDR_CBL_DETJ
G2 GP4_PIRQGB
GP5_PIRQHB
CXBEB_0
CXBEB_1
G9
C4
CBEJ1
CBEJ2
CBEJ0
CBEJ1
31
31
AC25
AD25
Vcc1_5_B_5
Vcc1_5_B_7
Vcc1_05_25
Vcc1_05_26
W15
W17
1K
CXBEB_2 E8 CBEJ3 CBEJ2 31 AD26 Vcc1_5_B_8 Vcc1_05_27 W18
CXBEB_3 CBEJ3 31 AD28 Vcc1_5_B_9 Vcc1_05_28 W19 FSB_VTT
1 OF 6 AE28 Vcc1_5_B_10 Vcc1_05_29
Boot Device *GNT0 *SPI_CS1# AE29 Vcc1_5_B_11 AH28
SPI 0 X AE30 Vcc1_5_B_12 V_CPU_IO_1 AJ30
ICHA Vcc1_5_B_13 V_CPU_IO_2
PCI 1 0 3D3V_SYS J24

* *
FWH 1 1 R716 0 J25 Vcc1_5_B_14
+/-5% 1D5V_ICH K23 Vcc1_5_B_15
C *internal pull-up K24 Vcc1_5_B_16 C
VccHDA R715 0 K25 Vcc1_5_B_17 3D3V_SYS
1D5V_ICH 1D1V_MCH 1D1V_ICH +/-5% L24 Vcc1_5_B_18
C350 Dummy L25 Vcc1_5_B_19

L17
VccSATAPLL LC Filter * 0.1uF M23 Vcc1_5_B_20
Vcc1_5_B_21 VccGLAN3_3
A27
16V, Y5V M24 3D3V_CL
*

R326 0 +/-5% VCCSATAPLL R324 0 M25 Vcc1_5_B_22 A12

r0805h6 N24 Vcc1_5_B_23 VccLAN3_3_1 B12 place cap. near pin AF1
10uH@2.52MHz C296 C297 N25 Vcc1_5_B_24 VccLAN3_3_2 5V_SB_SYS 3D3V_SB
P23 Vcc1_5_B_25
* 10uF
c0805h14 * 1uF
10V, X5R, +/-10% P24 Vcc1_5_B_26
Vcc1_5_B_27
3D3V_SYS

10V, Y5V, +80%/-20% P25 AH24

R24 Vcc1_5_B_28 Vcc3_3_5 AF21
*R327

C
R25 Vcc1_5_B_29 Vcc3_3_4 AC21 100 Q89
1D5V_ICH VccGLANPLL LRC Filter T23 Vcc1_5_B_30 Vcc3_3_3 AC19 +/-1% B MMBT3904
T24 Vcc1_5_B_31 Vcc3_3_2 AD10 Dummy
T25 Vcc1_5_B_32 Vcc3_3_1 AH30
L18

E
Place LC near pin AK20 T26 Vcc1_5_B_33 Vcc3_3_6 AK4 REF5V_SUS
*

*
R328 0 +/-5% VCCGLANPLL T28 Vcc1_5_B_34 Vcc3_3_7 A2 REF5V_SUS
U24 Vcc1_5_B_35 Vcc3_3_8 B1 C300
C298 C299 U28 Vcc1_5_B_36 Vcc3_3_9 B9 1uF
1D05V_ICH 1uH
* 10uF
* 2.2uF
* C430 U29 Vcc1_5_B_37
Vcc1_5_B_38
Vcc3_3_10
Vcc3_3_11
G11 * 10V, X5R, +/-10%
Rated at least 100mA c0805h14 6.3V, Y5V, +80%/-20% 4.7uF U30 G3
10V, Y5V, +80%/-20% c0603h9 c0805h14 V23 Vcc1_5_B_39 Vcc3_3_12 H7
6.3V, X5R, +/-10% V24 Vcc1_5_B_40 Vcc3_3_13 J2
V25 Vcc1_5_B_41 Vcc3_3_14 K8
W24 Vcc1_5_B_42 Vcc3_3_15 L8
W25 Vcc1_5_B_43 Vcc3_3_16 3D3V_SB
* C301 * C302 Y23 Vcc1_5_B_44
Vcc1_5_B_45
V5REF_SUS / 3D3V_SB Power Sequencing
22nF 0.1uF Place LRC near pin A25 Y24 AF2
1D1V_ICH Y25 Vcc1_5_B_46 VccSus3_3 U1
50V, X7R, +/-10% Vcc1_5_B_47 VccSus3_3_1 U2
AG29 VccSus3_3_2 U3
1D5V_ICH AG30 VccDMI_1 VccSus3_3_3 U5
1D5V_ICH VccDMIPLL LRC Filter VccDMI_2 VccSus3_3_4 U6
H10 VccSus3_3_5 U7
H11 Vcc1_5_A_1 VccSus3_3_6 U8
L19 AC11 Vcc1_5_A_2 VccSus3_3_7 V8
*

B B
*

R329 0 +/-5% VCCDMIPLL AB23 Vcc1_5_A_3 VccSus3_3_8 W7

AC18 Vcc1_5_A_4 VccSus3_3_9 W8
ICH10 Core decoupling caps. C303 C304 AC20 Vcc1_5_A_5 VccSus3_3_10 Y8
1uH 10uF 10nF AC13 Vcc1_5_A_6 VccSus3_3_11 A17
Rated at least 100mA * c0805h14 * 25V, X7R AD11 Vcc1_5_A_7
Vcc1_5_A_8
VccSus3_3_12
VccSus3_3_13
B20
10V, Y5V, +80%/-20% AD12 C20
AD13 Vcc1_5_A_9 VccSus3_3_14 E17
AE11 Vcc1_5_A_10 VccSus3_3_15 H15
AF11 Vcc1_5_A_11 VccSus3_3_16 VCCRTC
3D3V_SYS AH10 Vcc1_5_A_12
AH11 Vcc1_5_A_13 A22
Place LRC near pin T30 AJ10 Vcc1_5_A_14 VccRTC 3D3V_SYS
AK10 Vcc1_5_A_15
AC17 Vcc1_5_A_16 AC7 1D05V_ICH_SB
C305 AD17 Vcc1_5_A_17 VccSus1_05_1 H17
* 0.1uF AE17 Vcc1_5_A_18
Vcc1_5_A_19
VccSus1_05_2
16V, Y5V 1D5V_ICH AF17
PCI-E (VCC1_5_B) Filter AH17 Vcc1_5_A_20 H18 1D5V_ICH_SB C306
1D5V_PE_ICH AH18 Vcc1_5_A_21
Vcc1_5_A_22
VccSus1_5_1
VccSus1_5_2
AD8 * 0.1uF
AJ18 16V, Y5V
1D5V_PE_ICH AK18 Vcc1_5_A_23 C307
Vcc1_5_A_24 * 0.1uF
*
5 OF 6 16V, Y5V C308
0.1uF
C309 C310 C311
PCI-E decoupling caps. * * * ICHE
6.3V, Y5V, +80%/-20%

22uF 22uF 2.2uF

6.3V, X5R, +/-10% 6.3V, X5R, +/-10% c0603h9

5V_SYS 3D3V_SYS

1D1V_ICH
A

3D3V_SYS 3D3V_SYS

*R330
10
D12

A *R1393 *R1385
27KOhm
+/-5% SD103AW
A
C

C312 5V_SYS
10K +/-5%
* 22uF REF5V
6.3V, X5R, +/-10% GPI_VGA_CBL_DETJ REF5V
USB_HDR_CBL_DETJ

C313
* 0.1uF
* C314
* C315
16V, Y5V 0.1uF 0.1uF
place cap. near pin A15 16V, Y5V 16V, Y5V
Placed near AG30 Title

DMI decoupling caps. ICH10 -3

V5REF / 3D3V_SYS Power Sequencing
DWG NO Rev
A01
Arrowhead

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4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 25 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

ICH10
G30 H13
G29 VSS_100 VSS_099 H19
G25 VSS_101 VSS_098 H2 3D3V_SB 3D3V_SYS FSB_VTT FSB_VTT
G16 VSS_102 VSS_097 H22 1D5V_ICH 1D5V_ICH
F9 VSS_103 VSS_096 H25 1D5V_ICH 1D5V_ICH
F6 VSS_104 VSS_095 H26
F28 VSS_105 VSS_094 H28
F26 VSS_106 VSS_093 H9
F21 VSS_107 VSS_092 J29 C316 C317
F12 VSS_108 VSS_091 J30 * *

6.3V, X5R, +/-10%

1uF 1uF C322 C324 C325
D
E30 VSS_109
VSS_110
VSS_090
VSS_089
J6 * 10V, X5R, +/-10% * 10V, X5R, +/-10% * C318 * C319
* * * 4.7uF 0.1uF 0.1uF
D
E29 K26 0.1uF 0.1uF C320 C321 c0805h14
E22 VSS_111 VSS_088 K28 0.1uF 0.1uF
E2 VSS_112 VSS_087 L2
E18 VSS_113 VSS_086 L23
E15 VSS_114 VSS_085 L29
D28 VSS_115 VSS_084 L30
B8 VSS_116 VSS_083 M14
B5 VSS_117 VSS_082 M16 3D3V_SB
B28 VSS_118 VSS_081 M26
VSS_119 VSS_080 Placed near AH28 and AJ30
B25 M28 3D3V_SYS
B22 VSS_120 VSS_079 M6
B2 VSS_121 VSS_078 M8
B19 VSS_122 VSS_077 N13
B17 VSS_123 VSS_076 N14 Audio decoupling caps. CPU decoupling caps.
B14 VSS_124 VSS_075 N15
B11 VSS_125
VSS_126
VSS_074
VSS_073
N16 * C323 C332
AK8 N17
AK30 VSS_127
VSS_128
VSS_072
VSS_071
N18
0.1uF
* C331 * 22nF
50V, X7R
AK29 N23 0.1uF
AK2 VSS_129 VSS_070 N29
AK16 VSS_130 VSS_069 N30
AK14 VSS_131 VSS_068 P12 SATA decoupling caps.
AK12 VSS_132 VSS_067 P13
AJ8 VSS_133 VSS_066 P14 VCCRTC VCCRTC
AJ5 VSS_134 VSS_065 P15
AJ26 VSS_135 VSS_064 P16
AJ23 VSS_136 VSS_063 P17
AJ20 VSS_137 VSS_062 P18 3D3V_CL
AJ16 VSS_138 VSS_061 P19 C328
AJ14 VSS_139 VSS_060 P2 1uF USB decoupling caps.
AJ12 VSS_140
VSS_141
VSS_059
VSS_058
P26 * C326 * C327 * 10V, X5R, +/-10%
AH8 P28 X02 update 0.1uF 0.1uF c0603h9
AH6 VSS_142 VSS_057 P6
AH20 VSS_143 VSS_056 R13 3D3V_SYS
AH2 VSS_144 VSS_055 R14
AH19 VSS_145
VSS_146
VSS_054
VSS_053
R15 * C329
AH15 R16 0.1uF
C AH13 VSS_147 VSS_052 R17 C
AG28 VSS_148 VSS_051 R18
AF9 VSS_149 VSS_050 R23 Placed near A22
AF7 VSS_150 VSS_049 R29
AF29 VSS_151 VSS_048 R30
AF25 VSS_152 VSS_047 R8
AF23 VSS_153
VSS_154
VSS_046
VSS_045
T12 * C330
RTC decoupling caps.
AF20 T13 0.1uF
AF15 VSS_155 VSS_044 T14
AF13 VSS_156 VSS_043 T15 LAN decoupling caps.
AE9 VSS_157 VSS_042 T16
AE8 VSS_158 VSS_041 T17
AE6 VSS_159 VSS_040 T18
AE5 VSS_160 VSS_039 T19
AE25 VSS_161 VSS_038 T2
AE19 VSS_162 VSS_037 T29
AE18 VSS_163 VSS_036 T5
AE16 VSS_164 VSS_035 U13
AE15 VSS_165 VSS_034 U14
AE14 VSS_166 VSS_033 U15 PCI decoupling caps.
AE13 VSS_167 VSS_032 U16
AE12 VSS_168 VSS_031 U17
AE10 VSS_169 VSS_030 U18
AE1 VSS_170 VSS_029 U23
AD9 VSS_171 VSS_028 V13
AD7 VSS_172 VSS_027 V14
AD3 VSS_173 VSS_026 V15
AD22 VSS_174 VSS_025 V16
AD19 VSS_175 VSS_024 V17
AD18 VSS_176 VSS_023 V18
AD16 VSS_177 VSS_022 V26
AD15 VSS_178 VSS_021 V28
AD14 VSS_179 VSS_020 V3
AC8 VSS_180 VSS_019 V7
AC6 VSS_181 VSS_018 W1
AC5 VSS_182 VSS_017 W14
AC30 VSS_183 VSS_016 W16
AC29 VSS_184 VSS_015 W23
B VSS_185 VSS_014 B
AC24 W29
AC12 VSS_186 VSS_013 W30
AC1 VSS_187 VSS_012 W5
AB3 VSS_188 VSS_011 W6
AB28 VSS_189 VSS_010 Y26
AB26 VSS_190 VSS_009 Y28
AA6 VSS_191 VSS_008 Y3
AA5 VSS_192 VSS_007 Y7
VSS_193 VSS_006 AA30
AK27 VSS_005 AA29
AH29 VSS_194 VSS_004 AA1
AJ4 VSS_195 VSS_003 A30
AF3 VSS_196 VSS_002 A1
B27 VSS_197 VSS_001

*
VSS_198 PLTRSTJ R11 33
23 PLTRSTJ SIO_PLTRSTJ 29,34
ICHF 6 OF 6 for TPM

*
R161 33
MCH_PLTRSTJ 12

*dummy
R627
for GMCH/SIO

49.9
+/-1%

dummy
C35
* 10pF
50V, NPO, +/-5%

A A

Title

ICH10 -4
DWG NO Rev
A01
Arrowhead

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4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 26 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

U37 BOAZ

23 HSI_P6 C574 0.1uF 16V, X7R, +/-10% HSI_P6_LAN 52 26

TRD0- 36

**
C575 0.1uF 16V, X7R, +/-10% HSI_N6_LAN 53 GLAN_TXP MDI_N_0 27
23 HSI_N6 GLAN_TXN MDI_P_0 TRD0+ 36
55 22
23 HSO_P6_LAN GLAN_RXP MDI_N_1 TRD1- 36
56 23
23 HSO_N6_LAN GLAN_RXN MDI_P_1 TRD1+ 36
20 D3011
TRD2- 36

*
D MDI_N_2 D
+/-1% R43 33 Ohm ICH_LAN_JCLK_R 45 21 LAN_LED1 1
23 ICH_LAN_JCLK JKCLK MDI_P_2 TRD2+ 36
50 3
23 ICH_LAN_JRSTSYNC JRSTSYNC FP_LAN_LED_GRN_N 37
16 LAN_LED2 2
MDI_N_3 TRD3- 36
ICH_LAN_JTX0 42 17
23 ICH_LAN_JTX0 JTXD_0 MDI_P_3 TRD3+ 36
ICH_LAN_JTX1 43
23 ICH_LAN_JTX1 JTXD_1 BAT54A
ICH_LAN_JTX2 44 3 3D3V_CL
23 ICH_LAN_JTX2 JTXD_2 VDDO_33_3 46
ICH_LAN_JRX0 47 VDDO_33_46 28 LAN_1D0V
23 ICH_LAN_JRX0 JRXD_0 AVDD_33_28
ICH_LAN_JRX1 48
23 ICH_LAN_JRX1 JRXD_1
ICH_LAN_JRX2 49 5
23 ICH_LAN_JRX2 JRXD_2 DVDD_10_5 8
DVDD_10_8 33
DVDD_10_33 38 LAN_1D8V
4 DVDD_10_38
36 LAN_LED0 LED_0
2 11
36 LAN_LED1 LED_1 AVDD_18_11
36 LAN_LED2
1 14
LED_2 AVDD_18_14 19
AVDD_18_19 18
LAN_RSET 15 AVDD_18_18 24
RSET AVDD_18_24 25
IEEE_TEST AVDD_18_25 41
1 IEEE_TEST_P 12 AVDD_18_41 54
2 IEEE_TEST_N 13 IEEE_TEST_P AVDD_18_54 32
IEEE_TEST_N AVDD_18_32 30
Header_1X2 LAN_DIS_REG10 34 AVDD_18_30
DIS_REG10 29 LAN_1P8_CTRL
LAN_TEST0 37 CTRL18 31 LAN_1P0_CTRL
Dummy LAN_DISABLE_N CTRL10
LAN_TESTEN 36 51
TEST_EN RESERVED_NC

JTAG_TRST

JTAG_TDO
JTAG_TMS
JTAG_TCK
LAN_XTL_DP 9

JTAG_TDI
LAN_XTL_DN 10 XTAL2 57
XTAL1 GND_PAD

3D3V_CL
BOAZ

35
40
39
7
6
? R555 and R649 modified by follow Intel Place near Transistor
C ? C
ICH10 SR Rev 5 Final documentatiton(

6.3V, X5R, +/-10%

X02 update

4.7uF C411
TP_LAN_JRST
TP_LAN_TCK
to be fixed in future)

1
TP_LAN_TMS
TP_LAN_TDI R693 * * C412
TP_LAN_TDO 5.1KOhm 0.1uF

2
+/-1%
dummy
1P0V VREG

E
LAN_1P0_CTRL B Q34
BCP69T1G
3D3V_CL 3D3V_SB dummy
LAN_1D0V

C
4
LAN_1D0V
* *R649

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

R641 10K

4.7uF C414

4.7uF C418

0.1uF C415

0.1uF C416
1K

1
dummy R555
* * * *

*
0 LAN_TEST0
23 GPIO_LAN_DISABLEJ
LAN_DIS_REG10 +/-5%

2
R625
1K
*

LAN_XTL_DP

LAN_XTL_DN 3D3V_CL
Place near Transistor

LAN_TESTEN

R626 X6 C421 C486

*

1
10K 1 2
B
+/-5% R694 *10uF *10uF B

XTAL 25MHz 5.1KOhm

2
+/-1%
C419 C420
27pF 27pF
* *

E
+/-5% +/-5%
LAN_1P8_CTRL B Q38
1P8V VREG
LAN_RSET BCP69T1G

R616 LAN_1D8V
*

C
4
C1021 4.99K
*

16V, Y5V, +80%/-20%

10nF +/-1%

10uF C424

0.1uF C493
10V, Y5V, +80%/-20%
25V, X7R
dummy C425 C426 C427

1
0.1uF 0.1uF 0.1uF
X02 update * * * * *

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

2

2
X02 update
3D3V_CL 3D3V_CL 3D3V_CL 3D3V_CL close to transistor

* R1015 * R1016 * R1022 * R1020

51 51 51 51
Dummy
TP_LAN_TDI
TP_LAN_TMS

TP_LAN_TDO
TP_LAN_TCK
TP_LAN_JRST

* R1017 * R1018 * R1019

51 51 51

A Dummy A

For LAN ESD improvement

Title

Intel BOAZMAN LAN

DWG NO Rev
A01
Arrowhead

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Date: Friday, July 30, 2010
1
Sheet 27 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

L8, L9, L6, L7 should be FBs rated 470 or 600 ohms

@100MHz.
L8, L9 should be rated >200mA DC for low distortion.

L23
FB 600 Ohm

*
PROTD_L

L21

* *
R419 0 PROTA_R 37 FB 600 Ohm

*
+/-5% PROTD_R
D D

R425 0 PROTA_L 37
+/-5%
3D3V_AVDD
place C359 close
to pin38. MIC_BIAS_C AUDIO
22 INSULATOR
23
Mic bias resistor R417 R428 SA_D 24
EC68 PROTD_R must be place close 3K 3K 25

*
C359 C375 +/-1% +/-1% 26
* 0.1uF
*
4.7uF 4.7uF 6.3V, +/-20%
to codec.
L16
27
FB 600 Ohm 28

*
*
EC69 PROTD_L PORTC_L R415 0 29

*
+/-5% 2
4.7uF 6.3V, +/-20% 3
SA_C 4
SENSE_B 5
L22 1
SPDIF_OUT ANGND FB 600 Ohm

*
*
PORTC_R R422 0

*R186 +/-5%

TP106
TP107
TP108

TP109

TP110
4.7K 3D3V_AVDD CONN-Audio Port

TP89
TP85
+/-5% ANGND
Dummy
R230
* 22
+/-5%

49

48
47
46
45
44
43
42
41
40
39
38
37
ANGND
U3
1 1

SPDIF-OUT

DM_CLK
PAD

GPIO_0/EAPD

PORT-A_R
NC7
NC6
NC5
AVSS2

NC4
PORT-A_L
AVDD2
NC3
R423 R431 C134 C129
22K 22K C112
* C138 +/-5% +/-5% * *C68 **
3D3V_AUD_DIG 4.7uF 470pF 470pF 470pF 470pF
AUD_DVCORE 1 36 2 2
2 DVCORE PORT-D_R 35
TP83 3 DM_1/2 PORT-D_L 34 ANGNDANGND
C 4 DVI/O SENSE_B/SRC_A 33 ANGND C

23 ICH_AUD_SDOUT
TP84 5
6
DM_3/4
SDATA_OUT
AD1984 MIC_BIAS_IN
MONO_OUT
32
31
MONO_OUT
MONO_OUT 32
ICH_AUD_BCLK TP90
23 ICH_AUD_BCLK 7 BIT_CLK GPIO_1/MIC_BIAS-E 30 TP97 3D3V_SYS 3D3V_AUD_DIG Audio Jack
*

R414 33 +/-5% 8 DVSS GPIO_2 29 MIC_BIAS_C

23 ICH_AUD_SDIN2 9 SDATA_IN MIC_BIAS-C 28 MIC_BIAS_B
10 DVDD MIC_BIAS-B 27

CD_GND (PORT F)
23 ICH_AUD_SYNC SYNC VREF_FILT
SENSE_A/SRC_B

11 26 LINE OUT
23 ICH_AUD_RSTJ 12 RESET# AVSS1 25 FB12
D

*
TP93 PCBEEP AVDD1 (UAJ)
C286
* * C137

PORT-C_R
PORT-E_R

PORT-B_R
PORT-F_R

PORT-C_L
PORT-E_L

PORT-B_L
PORT-F_L

0.1uF 0.1uF
FB 600 Ohm
C360 C58 C131 C130 C366 C133
* * * * * * LINE IN & MIC
NC1

NC2

Place close to pin3 and pin9 each. 0.1uF 0.1uF 1uF 0.1uF 10uF 0.1uF C
10V, X5R, +/-10% c0805h14 (UAJ)
AD1984JCPZ-REEL 6.3V, X5R, +/-20%
13
14
15
16
17
18
19
20
21
22
23
24

MIC_BIAS_B

3D3V_AVDD ANGND
TP81
TP82
TP91
TP92
TP94

TP105

place R413 and R412 close to codec.

C111 2.2uF 10V, X5R, +/-10% PORTC_R R413 R412
****

R416
2.67K Ohm * *R420
2.67K Ohm * C110 2.2uF 10V, X5R, +/-10% PORTC_L
3K
+/-1%
3K
+/-1%
C355
0.1uF

37 SA_A R1260 39.2K Ohm +/-1% +/-1%, +/-1%,

dummy C72 2.2uF 10V, X5R, +/-10% PORTB_R
PROTB_R 37
**

37 SA_B R1259 20K +/-1%

SENSE_A C71 2.2uF 10V, X5R, +/-10% PORTB_L
PROTB_L 37
SA_C R426 10K +/-1%
R234 R433 R411
SA_D R430 5.1KOhm +/-1% * 0 ANGND 33K 33K AUD_DVCORE 3D3V_AUD_DIG
+/-5% +/-5% +/-5%
Dummy Dummy Dummy

1
C374 C109
SENSE_B Q48
*
4.7uF * 0.1uF *R300
4.7K
B
tbd PESD5V0L2BT +/-5% B
C140 C361 dummy
* 1uF * 1uF ANGND ICH_AUD_RSTJ
CP8 CP5
place C109 close to pin1 and C374 right next it.
2 1 2 1

3
ANGND ANGND
COPPER COPPER

ANGND
ANGND ANGND 3D3V_AVDD 3D3V_SB

3D3V_AVDD

4
5V_SB_SYS 5V_SYS
*

SEE NOTE 2
R457 0 +/-5% dummy ICH_AUD_BCLK

Vout 4
ADJ

Vin
U10 R235
C352 C353 C354 C357 RC1117ST
* 1nF * 1nF * 1nF * 1nF dummy FB14
* 47

* * R421 +/-5%

3
ANGND Dummy Dummy Dummy Dummy R410
Dummy
0
+/-5%
0
dummy * *
*

R459 0 +/-5% C132

C365 FB 30 Ohm
ANGND R434 * 10uF
10nF
Dummy
* 301
NOTE 1. +/-1%

6.3V, X5R, +/-20%

AVDD must be +3.3V +/- 5%. ANGND dummy
For best audio performance and low noise, use a linear voltage regulator such Optional stitch caps for EMI, 3D3V_AVDDADJ
as LM1117 or AME8800A. LOCATE UNDER CODEC.USE 80 distributed along the moat and PLACE NEAR CODEC
NOTE 2. MILLS WIDE TRACEBRIDGING AGND in particular at the rear jacks.
C1345 C356
The regulator can be powered from +12V or +5V (if using LDO type like LM1117
or AME8800A).
AND DGND PLANES,
10uF * * 0.1uF *R516
499
* C362
For reduced power ON/OFF pop, suggest installing option to power LDO type dummy dummy +/-1% 0.1uF
regulator from +5V_STBY.
A dummy A
NOTE 3.
R19 option is for higher MIC bias voltage compliance (normally not required).
and is exclusive of R5.
ANGND ANGND ANGND
NOTE 4.
L1 and L2 should be rated 300mA or higher (for low THD+N).
NOTE 5
Systems with 2 rear jacks must only implement J1A and J1-B jacks.
In this configuration MIC jack is retaskable as LINE_IN.
Also change R10 and R19 to 150 ohms.
NOTE 6. Title
Systems with 3 rear jacks must implement J1-A, J1-B and also J1-C as the Layout Note
LINE_IN jack. 1. Use double via close to pin 7 and directly to DGND plane. HDA Codec AD1984
In this configuration J1-B functions as MIC input only. 2. place C18 close to pin1 and C38 right next it.
3. place c19 close to pin3. DWG NO Rev
4. place C21 close to pin9. A01
5. Place a couple of stitch caps(C30,C31,C32,C33) very close to audio jacks. Arrowhead

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6. C4 close to pin38.
Date: Wednesday, June 02, 2010 Sheet 28 of 45

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5 4 3 2 1
 5 4

3D3V_SYS Trung Tâm Máy Tính AV VCCRTC_SIO

3 2

SCH5524 Decoupling
1

1
3D3V_SB 3D3V_SB *R3903
2MOhm *
C451
1uF
VCCRTC_SIO
+/-5% c0603h9 3D3V_SYS 3D3V_SB 3D3V_SB 3D3V_SB

2
3D3V_SB
3D3V_SB 16V, X7R, +/-10% 16V, X7R, +/-10%

122
106
U3501 C108 C49 C50 C52 C53 C54 C47 C48 C51

79
57
34
24

23

47
6
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
R3075 R3076 * * * * * * * * 16V, X7R, +/-10% * 16V, X7R, +/-10%

VBAT
VCC

HVTR
VTR1
VTR2
VTR3
VTR4
VTR5
VTR6
8.2K 8.2K 78 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
* * 37 DENSEL GP40/DRVDEN0/GP8051_31
+/-5% +/-5%
76 80
37 INDEX# 75 INDEX# SLCT/KDAT 81 SLCT 32
37 MTRA# 74 MTR0# PE/KCLK 82 PE 32
D 40 COM_SER2_DET# GP21/SMB_DAT/GP8051_39 BUSY/FALE1 BUSY 32 D

Floppy
73 83
37 DRVA# 72 DS0# ACK#/FALE0 84 ACKJ 32
PD7
32 INTRUD_CABLE_DET# 71 GP22/SMB_CLK/GP8051_38 PD7/FD7_FA7 85 PD6

Parallel Port
37 DIR# 70 DIR# PD6/FD6_FA6 86 PD5
37 STEP# 68 STEP# PD5/FD5_FA5 87 PD4
37 WDATA# 67 WDATA# PD4/FD4_FA4 88 PD3
37 WGATE# 66 WGATE# PD3/FD3_FA3 89 PD2 3D3V_SB 3D3V_SB 3D3V_SYS 1D1V_MCH

I/F
37 TRK0# 65 TRK0# PD2/FD2_FA2 90 PD1
37 WPT# 64 WRTPRT# PD1/FD1_FA1 91 PD0 POP3
37 RDATA# 63 RDATA# PD0/FD0_FA0 93 PD[7..0]
37
37
HDSEL#
DSKCHG#
62 HDSEL#
DSKCHG#
SLCTIN#/FWR#
INIT#/FRD#
94
95
SLINJ
INIT
32
32
PD[7..0] 32
*R229
30K *R220
30K SIO_PWRGD_3V *R3882
8.25K
+/-1% +/-1% +/-1%
ERROR#/FPGM 96 ERRJ 32
POP3 Dummy POP3
9 ALF#/MCLK/FCS# 97 AFDJ 32
Dummy
7 CK_14M_SIO 10 CLOCKI STROBE#/MDAT STBJ 32
DTR2# COM2_SOUT_SPLIT_N
23,34 L_AD0 LAD0

LPC INTERFACE
11
23,34 L_AD1 12 LAD1 98
23,34 L_AD2 DCD1# 35

3
0 13 LAD2 DCD1#/GP8051_10 99
DSR1# 35
*

R3904 23,34 L_AD3 14 LAD3 DSR1#/GP8051_11 100 Q3030 R3889

LFRAME# RXD1/GP8051_12 SIN1 35 *

3
23 LPCPDJ +/-5% 23,34 L_FRAMEJ 15 101 POP3 7.15K

Serial Port 1/2

23 L_DRQ0J 16 LDRQ# RTS1#[SYSOPT]/GP8051_58 102 RTS1# 35
MMDT5551 +/-1%
SOUT1 35
*

R3849 26,34 SIO_PLTRSTJ SIO_LPCPD 17 LRESET# (5V_PRSNT)GP8051_14/TXD1 103 Dummy POP3 1D1V_MCH_CL
3D3V_SYS LPCPD# CTS1#/GP8051_15 CTS1# 35
8.2K +/-5% 18 104

4
7 CK_33M_SIO 1 PCICLK DTR1#[FLASH_EN]/GP8051_16 105 DTR1# 35 Q3032
SERIRQ
Dummy 24,34 SERIRQ SER_IRQ RI1#/GP8051_17 RI1# 35
77 SOUT2 MMDT5551
23 L_PMEJ

4
GP41/IO_PME#/GP8051_23 POP3
107 SIO_PWRGD_3V COM2_SOUT_SPLIT_N
GP51/DCD2#/GP8051_9 108 DCD2# 40
GP54/DSR2#GP8051_8 109 DSR2# 40
27 GP52/RXD2/GP8051_32 110 RXD2 40
7,34 SMB_DATA_MAIN SDAT_1/GP42/IO_SMI#/GP8051_24 (12V_PRSNT)GP8051_34/GP55/RTS2# RTS2# 40 PREVENTS LEAKAGE

SMB
28 111 SOUT2
7,16,17,22,23,31 SMB_DATA_RESUME 29 SDAT/GP35/GP8051_25 (MB_REG_PG)GP8051_33/GP53/TXD2 112 SOUT2 40
7,34 SMB_CLK_MAIN
7,16,17,22,23,31 SMB_CLK_RESUME
30 SCLK_1/GP26/GP8051_26
SCLK/GP25/GP8051_27
GP56/CTS2#/GP8051_7
(MEM_REG_PG)GP8051_35/GP57/DTR2#
113 DTR2#
CTS2#
DTR2#
40
40
TO RAILS THROUGH
114
GP50/RI2#/GP8051_6 RI2# 40 BJT EMITTERS
SCH5524-NS This Circuit will follow fleming design
4 3D3V_SYS
C
37 DIAG_LED_3 5 (DIAG_LED3#)GP8051_3 121 and change R221 & R223 to 30K C
37 DIAG_LED_1 (DIAG_LED1#)GP8051_1 GP37/A20M/GP8051_37 A20GATE 24
7 120 R3090 on version that will change LAYOUT FILE
*

KB/MS
37 DIAG_LED_2 8 (DIAG_LED2#)GP8051_2 GP36/KBDRST#/GP8051_36 118 KBRSTJ 24
4.7K
37 DIAG_LED_4 36 (DIAG_LED4#)GP8051_4 MDAT 117 SIO_MDAT 40
+/-5%
23,37 PWR_BTN# PWRBTN#/GP8051_47/GP33 MCLK 116 SIO_MCLK 40
1D5V_ICH
21 KDAT 115 SIO_KBDAT 40
3D3V_SYS
32 AUD_PCSPKR_DET# 25 LATCHED_BF_CUT/GP23/GP8051_18 KCLK SIO_KBCLK 40
PSU_FAN_CTRL
37 SIO_YELLOW_N 26 YELLOW#
37 SIO_GREEN_N GREEN#
Miscellaneous
52 R3856
37 FP_CBL_DETECT#
22 SIO_G_PLTRSTJ
53
54
(FP_CBL_DET#)GP8051_28/GP75
PCI_RST_SYS#/GP76/GP8051_29
* 8.25K 3D3V_SYS 1D5V_STR 3D3V_SB
31 SIO_P_PCIRSTJ +/-1%
55 PCI_RST_SLOTS#/GP77/GP8051_30 39 POP3
32 PS_ONJ
TP98
NC_PIN56 56
58
PS_ON#/GP80/GP8051_20
BACKFEED_CUT#/GP81/GP8051_19
TACH1
TACH2
40
41
SIO_FAN_SEN_CPU
SIO_FAN_SEN_SYS
33
33
COM2_SOUT_SPLIT_N *R3886
8.25K POP3
+/-1% R222
10,23 CPU_SKTOCC# SIO_PWRGD_3V 59 (SKT_OCC#)GP8051_13/GP82
PWR_GOOD_3V/GP83/GP8051_21 Hardware Monitoring
TACH3/GP8051_42
PWM1
49 PSU_FAN_TACH
FAN_PWM_CPU 33
32
*R217 3D3V_SYS POP3 +/-1% *

3
60 50 10K COM2_SOUT_SPLIT_N 30K
23 SIO_RSMRSTJ 123 RSMRST#/GP84/GP8051_22 PWM2 51 SIO_FAN_PWM_SYS 33
+/-1%
20,23 SLP_S3J 124 SLP_S3#/GP10/GP8051_56 PWM3/GP8051_43 PSU_FAN_CTRL 32 D14
20,23 S4_STATEJ POP3
125 SLP_S4_S5#/GP11/GP8051_57 22 C A Q3031 R3871
20,32 ATXPWRGD PECI_REQ# 23 *R298

3
PWER2_PRSNT# 126 PWRGD_PS/GP8051_51 PWM_BLANK/GP8051_44(H_CPURST#) 48 MMDT5551 10K
(PWR2_PRSNT)GP8051_46/GP31 FAN_ID FAN_ID 33 2KOhm
SIO_PIN127 127 POP3 +/-1%
+/-1%

4
SIO_PIN128 128 SPEAKER[DIAG_EN#]/GP8051_45/GP14 43 THERMDA_SIO BAT54HT1G COM2_SOUT_SPLIT_N POP3 POP3
(SLP_M#)GP8051_5 REMOTE1+ +/-5%
44 THERMDC_SIO
REMOTE1- 45 * 8.2K Q3033
PWM_IN/GP8051_0

FIO_SYSTEM_TDA
SIO_PIN33 33 REMOTE2+ 46 FIO_SYSTEM_TDC R3852 @5524 rev.C * R227 MMDT5551

4
32 PECI READY (H_CPURST#) LVSMB_DAT REMOTE2- POP4 3D3V_CL POP3
10,24 PECI R3852 dummy 33K
FSB_VTT 31 PECI/LVSMB_CLK DTR2#
PECI VREF +/-1%
35 SIO_FORCEPHJ
FORCE_PROCHOT# 38 POP3
PROCHOT_I# PROCHOTJ 8,10,24 ICH_VRMPWRGD 23
HVSS

AVSS
CAP1

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6

C3510 5524 PRE-POST DIAG PG GENERATION

69
2

3
19
37
61
92
119
42

20

0.1uF
@5514 @5514
@5514 R3893 , R3902 dummy Only used For 5524 dummy all in this block
R3870
B
R3870 dummy 10K
+/-5%
* * C3744
4.7uF
R3894 stuff FSB_VTT
B
@5524 rev.C
3D3V_SB
POP3 R3893 , R3894 dummy R3875

POP3 POP3
R3902 stuff * 100
+/-1%
R547
R546
2.7K +/-5%
2.7K +/-5%
SMB_DATA_RESUME
SMB_CLK_RESUME
**

**

0 R3896 SIO_PIN128 SPEAKER 0 R3898 SIO_PIN127

23 ICH_SLP_M_N
3D3V_SYS

*
0 R3895 0 R3897 3D3V_SB 3D3V_SB SIO_PECI_READY 0 R3894 SIO_PIN33
24 ICH_SATA2_HDLEDJ 37 SIO_FP_HDLEDJ
POP4 @5514 POP4 @5514 R549 2.7K +/-5% SMB_DATA_MAIN FIO_SYSTEM_TDC FIO_SYSTEM_TDC 37
R548 2.7K +/-5% SMB_CLK_MAIN
R3896 dummy R3898 dummy @5524 @5524
R3895 stuff R3897 stuff *R2232
88.7KOhm *R2212
88.7KOhm * C2813

+/-1% +/-1% 2.2nF

3D3V_SB FIO_SYSTEM_TDA FIO_SYSTEM_TDA 37
3D3V_SB 3D3V_SB 3D3V_SB 3D3V_SB
3D3V_SYS 3D3V_SYS SOUT2 DTR2# THERMDA_SIO
Dummy Dummy
R3081 R3085 R3082
@5524 @5524 *R404 *R405
30K
FSB_VTT
Header_1X2

2
8.2K 8.2K 8.2K
* +/-5%
POP4
* +/-5%
POP4
* +/-5%
Dummy
*R223
88.7K
+/-1%
*R221
88.7K
+/-1% 12V_VRM
30K
+/-1%
C
+/-1%

PWER2_PRSNT#
1
*
C2811
330pF

SPEAKER RTS1# DTR1# SOUT2 DTR2#

B Q77
MMBT3904
* 1K
R435
JTHERMD
THERMDC_SIO
32 SPEAKER *R3885 sot23_bech11 dummy
THERMAL SENSOR
E

Dummy
8.2K R3891

*
@5514 +/-5% SIO_FORCEPHJ 0 +/-5%
R3086 PROCHOTJ 8,10,24
*R3084 @5514
*R3083 3D3V_SYS
C

R3084 dummy

**
422 30K 3D3V_SYS SOUT2 0 R3869 COM2_SOUT_SPLIT_N
R3081 stuff 8.2K
R3086 dummy * +/-1% +/-1% B Q79 +/-5%
+/-5% R3085 stuff dummy MMBT3904 SIO_PWRGD_3V 0 R3868
POP3 *R3887 R3079 3D3V_SYS
PWRGD_3V 12,23,30
* *R3910 sot23_bech11 +/-5%
E

8.2K 4.7K 698 VTT_OUT_RIGHT VTT_OUT_RIGHT C587

+/-5% +/-5% +/-1% 100pF *
dummy R402 50V, NPO, +/-5% place close to SIO
SERIRQ DIAG_LED_4 * 30K
SPEAKER RTS1# DTR1# +/-1% * R440 * R441
A 3D3V_SYS 3D3V_SYS 1K 1K A
RTS2#
Q3041
Diag_En Sysopt strap Flash_en Dummy
R3872 R3080 3 4
* 10K * 4.7K
5
R439

PULL +/-5%
2 PM_SLP 10,12
Disable 0 X 4E Flash Enable +/-5% dummy 1K

*
HIGH A20GATE DIAG_LED_1 3D3V_SYS
3D3V_SB 1 6 0 dummy
HCPURSTJ 8,9,10,12,34

**
DEFAULT DEFAULT DEFAULT 3D3V_SYS R3893
0 dummy
PULL *R432
30K
MMDT5551 R3902
DPSLP# 10,23 Title

LOW Enable 0 X 2E Parallel

* R3864 +/-1% Super I/O--SMSC5524/5514E
*

Enable R3873
* 8.2K SIO_PECI_READY 0 R3920
10K SOUT1 DWG NO Rev
+/-5%
+/-5% Dummy A01
SIO STRAPING KBRSTJ AUD_PCSPKR_DET# Arrowhead

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1
Sheet 29 of 45
 GENII SWITCH
5 4

Trung Tâm Máy

DISPLAY PORTTính AV
3

TX0P
TX0N
10
9
2

O1
U3523

IN1
1
2
1

8 O2 IN2 3
TX1P 7 GND_2 GND_1 4
3D3V_SYS U53 TX1N 6 O3 IN3 5
O4 IN4
RCLAMP0524P.TCT
6 43 Dummy
17 VDD1 TX0+ 42 EXP_TXP11_GFX 22
U3524
C400 C401 C399 C388 C377 C376 22 VDD2 TX0- EXP_TXN11_GFX 22
1uF * 0.1uF * 0.1uF * 0.1uF * 0.1uF * 0.1uF * 27 VDD3
VDD4 TX1+
41
EXP_TXP10_GFX 22
TX2P 10
O1 IN1
1
10V, X5R, +/-10% 16V, Y5V 16V, Y5V 16V, Y5V 16V, Y5V 16V, Y5V 34 40 TX2N 9 2
50 VDD5 TX1- EXP_TXN10_GFX 22 8 O2 IN2 3
55 VDD6 39 TX3P 7 GND_2 GND_1 4
VDD7 TX2+ 38 EXP_TXP9_GFX 22 TX3N 6 O3 IN3 5
D TX2- EXP_TXN9_GFX 22 O4 IN4 D

37 RCLAMP0524P.TCT
4 TX3+ 36 EXP_TXP8_GFX 22 Dummy U3525
12 EXP_TXP11 5 IN_0+ TX3- EXP_TXN8_GFX 22
12 EXP_TXN11 IN_0- 54 6 1
TX0P_C C3750 0.1uF TX0P DPC_AUX_DN

** ** ** **
7 D0+ 53 TX0N_C C3749 0.1uF TX0N O2 IN1
12 EXP_TXP10 8 IN_1+ D0- 5 2
DPC_AUX_DP
12 EXP_TXN10 IN_1- 52 O1 IN2
TX1P_C C3752 0.1uF TX1P
9 D1+ 51 TX1N_C C3751 0.1uF TX1N 4 3
12 EXP_TXP9 10 IN_2+ D1- GND_2 GND_1 DP_PORT1
12 EXP_TXN9 IN_2- 47 23 22
TX2P_C C3753 0.1uF TX2P RCLAMP0522P.TCT
12 D2+ 46 TX2N_C C3754 0.1uF TX2N Dummy HOLE3 HOLE2
12 EXP_TXP8 13 IN_3+ D2- 1
U3526 TX0P
12 EXP_TXN8 IN_3- 45 2 ML_Lane0_P
TX3P_C C3756 0.1uF TX3P
D3+ 44 TX3N_C C3755 0.1uF TX3N DP_P13 6 1 TX0N 3 GND1
D3- O2 IN1 TX1P 4 ML_Lane0_N
26 HPD_DP 5 2 5 ML_Lane1_P
14 RX0+ 25 EXP_RXP9_SW 22 O1 IN2 TX1N 6 GND2
12 EXP_RXP9 15 OUT+ RX0- EXP_RXN9_SW 22 4 3 TX2P 7 ML_Lane1_N
12 EXP_RXN9 OUT- 24 GND_2 GND_1 8 ML_Lane2_P
18 RX1+ 23 EXP_RXP8_SW 22 RCLAMP0522P.TCT TX2N 9 GND3
12 EXP_RXP8 19 X+ RX1- EXP_RXN8_SW 22 Dummy TX3P 10 ML_Lane2_N
12 EXP_RXN8 X- 11 ML_Lane3_P
33 SW_DPC_AUX_DP C3747 0.1uF SW_C_DPC_AUX_DP TX3N 12 GND4

**
AUX+ 32 SW_DPC_AUX_DN C3748 0.1uF SW_C_DPC_AUX_DN DP_P13 13 ML_Lane3_N
GEN_SEL 2 AUX- 14 GND5
SEL 31 HPD_DP_SW DPC_AUX_DP 15 GND6
*

R403 0 LE# 3 HPD 16 AUX_CH_P

12,23,29 PWRGD_3V LE# 30 17 GND7
1M DPC_AUX_DN
Dummy
*
NC +/-5%* 3D3V_SYS HPD_DP 18
19
AUX_CH_N
H_P_DETECT
R615 R3888 F2
1 29 20 RETURN
0
11 GND1 GND7 35 * C516 C499 C246 DP_PWR

1
16 GND2 GND8 48 Fuse 500mA 0.1uF 10uF 22uF 24 21
20 GND3
GND4
GND9
GND10
49 * * c0805h14 * HOLE4 HOLE1
21 56

2
28 GND5 GND11 57 Dummy Dummy CONN - Display port
GND6 GND_PAD

6.3V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%
C C

6.3V, X5R, +/-20%

PI3PCIE2612-BZFEX

DDPC_CTRLDATA SW_C_DPC_AUX_DN

D
DDPC_CTRLCLK SW_C_DPC_AUX_DP
Stitching Cap For DP

D
Q90 Q92 2N7002-7-F Q94 Q96 2N7002-7-F
2N7002-7-F 2N7002-7-F 3D3V_SYS
3D3V_SYS 12V_SYS 3D3V_SYS 12V_SYS 3D3V_SYS 12V_SYS 5V_SYS 12V_SYS 5V_SYS G DP_P13_POS G DP_P13_INV 3D3V_SYS
DP_P13_POS G DP_P13_INV G

S
S

S
C1023 C1022 C1024 C1026
1M 1M
* C1027 * +/-5% * +/-5% *R3901
100KOhm *
R3913
100KOhm
*

10nF 25V, X7R 25V, X7R 25V, X7R 25V, X7R 1M R3890 1M R3909 +/-1% +/-1%
25V, X7R 10nF 10nF 10nF 10nF
*
+/-5% *
+/-5% dummy
R3892 R3912

S
G G G G

2N7002-7-F 2N7002-7-F
2N7002-7-F Q93 2N7002-7-F Q99 DPC_AUX_DN
Q91 Q95

D
DPC_AUX_DP
*

R3899 0 DPC_AUX_DP DPC_AUX_DN DPC_AUX_DP DPC_AUX_DN

*

R653 12V_SYS
22,24 PEG_PINB81_R 1K Dummy
R3911 R3900
3D3V_SYS 12V_SYS
*8.2K 100KOhm * * 100KOhm
B
R544 +/-1% +/-1% B
5V_SYS R451
GEN_SEL 4.7K * X02 update +/-5% dummy
* R465 dummy
+/-5%
R674 0
DP_P13_POS
8.2K

*
DP_P13_INV
+/-5%
*
1

Dummy 1K

D
MMDT5551 R650
Q76 Q86
R648
2N7002-7-F 2N7002-7-F
*

Q3042 DP_P13 G G
6

Dummy C1002

S
1M 8.2K 1uF 3D3V_SYS 3D3V_SYS
* *
10V, X5R, +/-10%
+/-5% +/-5%
R3884
Dummy R676 R669
R608
2.2K * *2.2K
*

+/-5% +/-5%
1K Dummy

Stuff R3899 and un-pop the buffer circuit

DDPC_CTRLCLK
12 DDPC_CTRLCLK
DDPC_CTRLDATA
3D3V_SYS 12 DDPC_CTRLDATA
3D3V_SYS 1D1V_MCH PEG_PRESENCE_OVERRIDEJ

R1004 3D3V_SYS
R607 R466
Display Port Hotplug Detect * 4.7K
* *
D

4.7K 4.7K +/-5% DDPC_CTRLDATA

+/-5% +/-5% Q81
Dummy 2N7002-7-F
G 1K*

D
HPD_DP_SW R654
A Q85 A
S

5V_SYS 2N7002-7-F
PEG_PRESENCE_OVERRIDEJ G
C
*

HPD_DP_SW R456 10K B Q87 PEG_PINB7_R 22,23

*R652
D

S
1K MMBT3904
D

Q68 +/-5%
D
E

R657
*

2N7002-7-F Dummy Q88

G HPD_DP Q82 2N7002-7-F
1K 2N7002-7-F G
G 22,24 PEG_PINB81_R
Title
S

R255
GenII Switch / DP
S

+/-1%
*
S

100KOhm DWG NO Rev

A01
Arrowhead

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Date: Wednesday, June 02, 2010
1
Sheet 30 of 45
 5

PCI SLOT W/ RISER ONLY FOR NEO

PCI SLOT W/O RISER FOR SMITH & CYPHER
4

Trung Tâm Máy Tính AV 3 2 1

5V_SYS

3D3V_SYS 3D3V_SYS

-12V_SYS 5V_SYS 12V_SYS

SLOT2
Note: 20-24 mils
B1 A1
D -12V TRST# D
B2 A2
B3 TCK +12V A3
B4 GND#B3 TMS A4
B5 TDO TDI A5
B6 +5V#B5 +5V#A5 A6 INTAJ
+5V#B6 INTA# INTAJ 25
INTBJ B7 A7 INTCJ
25 INTBJ INTB# INTC# INTCJ 25
INTDJ B8 A8
25 INTDJ INTD# +5V#A8
B9 A9 3D3V_SB
B10 PRSNT1# RESERVED#A9 A10
B11 RESERVED#B10 +5Vi/o#A10 A11
B12 PRSNT2# RESERVED#A11 A12
B13 GND#B12 GND#A12 A13
B14 GND#B13 GND#A13 A14
B15 RESERVED#B14 3.3Vaux A15
B16 GND#B15 RESET# A16 SIO_P_PCIRSTJ 29
7 CK_33M_PCI1 CLK +5Vi/o#A16
B17 A17
B18 GND#B17 GNT# A18 GNT0J 25,34
PREQ0J
B19 REQ# GND#A18 A19
B20 +5Vi/o#B19 PME# A20 PMEJ 25
AD31 AD30
AD29 B21 AD31 AD30 A21
B22 AD29 +3.3V#A21 A22 AD28
AD27 B23 GND#B22 AD28 A23 AD26
AD25 B24 AD27 AD26 A24
B25 AD25 GND#A24 A25 AD24
CBEJ3 B26 +3.3V#B25 AD24 A26 IDSEL0
25 CBEJ3 B27 C/BE#3 IDSEL A27
AD23
B28 AD23 +3.3V#A27 A28 AD22
AD21 B29 GND#B28 AD22 A29 AD20
AD19 B30 AD21 AD20 A30
B31 AD19 GND#A30 A31 AD18
AD17 B32 +3.3V#B31 AD18 A32 AD16
B33 AD17 AD16 A33
B34 C/BE#2 +3.3V#A33 A34 FRAMEJ
25 CBEJ2 GND#B34 FRAME# FRAMEJ 25
IRDYJ B35 A35
25 IRDYJ B36 IRDY# GND#A35 A36 TRDYJ
B37 +3.3V#B36 TRDY# A37 TRDYJ 25
DEVSELJ
25 DEVSELJ B38 DEVSEL# GND#A37 A38 STOPJ
B39 GND#B38 STOP# A39 STOPJ 25
C LOCKJ C
25 LOCKJ B40 LOCK# +3.3V#A39 A40
PERRJ P1SCLK
25 PERRJ B41 PERR# RESERVED#A40 A41 P1SDATA
SERRJ B42 +3.3V#B41 RESERVED A42
25 SERRJ B43 SERR# GND#A42 A43 PAR
B44 +3.3V#B43 PAR A44 PAR 25
CBEJ1 AD15
25 CBEJ1 AD14 B45 C/BE#1 AD15 A45
B46 AD14 +3.3V#A45 A46 AD13
AD12 B47 GND#B46 AD13 A47 AD11
AD10 B48 AD12 AD11 A48
B49 AD10 GND#A48 A49 AD9
GND#B49 AD9

AD8 B50 A50 CBEJ0

B51 AD8 C/BE#0 A51 CBEJ0 25
AD7
B52 AD7 +3.3V A52 AD6
AD5 B53 +3.3V#B54 AD6 A53 AD4
AD3 B54 AD5 AD4 A54
B55 AD3 GND A55 AD2
AD1 B56 GND#B57 AD2 A56 AD0
B57 AD1 AD0 A57
ACK64J B58 +5Vi/o#B59 +5Vi/o A58 REQ64_1J
B59 ACK64# REQ64# A59
B60 +5V#B61 +5V#A61 A60
+5V#B62 +5V

B61 A61
B62 12 1 A62 PREQ1J
B63 13 2 A63
B64 14 3 A64 GNT1J 25
Pin 61 to Pin 71 are for Raiser B65 15 4 A65
B66 16 5 A66 CK_33M_PCI2 7
card for Neo. For cypher and B67 17 6 A67
12V_SYS

Smith BOM Use EH06017-SHW-DF B68 18 7 A68

B69 19 8 A69
for Slot2 B70 20 9 A70 GPI_RISER_ID0
GPI_RISER_ID1
25
25
B71 21 10 A71
22 11
B B
5V_SYS 12V_SYS 3D3V_SYS
Slot-PCI -12V_SYS

AD[31..0]
AD[31..0] 25
EC36 EC37

1
EC35
* C464
* C465 * 120uF * 470uF
* C466 16V, Y5V
* 470uF
+/-20%
0.1uF
16V, Y5V
0.1uF
16V, Y5V
+/-20% +/-20% 0.1uF
16V, Y5V
* 0.1uF
C467

2
5V_SYS

3D3V_SYS 3D3V_SYS

RN24 R449 2.7K REQ64_1J R1342 8.2K GPI_RISER_ID0

* *

*1 INTBJ
INTBJ 25
+/-5% +/-5%

*
2 INTCJ 3D3V_SYS IDSEL0 R508 330 AD16
3 4 INTCJ 25
R1379 8.2K GPI_RISER_ID1 +/-5%
5 6 PREQ2J 25
+/-5%
7 8 PREQ3J 25
R450 2.7K ACK64J
8.2K +/-5% C460 3D3V_SB
+/-5% * 0.1uF
16V, Y5V
RN25
*1 2 INTDJ
PREQ1J
INTDJ
25
25
*R318 R313
4.7K *4.7K
3 4 +/-5% +/-5%
5 6 PREQ0J 25
INTAJ EMI cap, placed near PCI Slot dummy dummy
7 8 INTAJ 25
for 33M clock layer change
8.2K

**
3D3V_SYS P1SCLK R575 0 +/-5%
SMB_CLK_RESUME 7,16,17,22,23,29
RN26 P1SDATA R574 0 +/-5%
SMB_DATA_RESUME 7,16,17,22,23,29
A
*1 2
SERRJ
PERRJ
5V_SYS 5V_SYS 5V_SYS
A
3 4 LOCKJ
5 6 STOPJ
7 8 C461 C462 C463
8.2K * 0.1uF * 0.1uF * 0.1uF
16V, Y5V 16V, Y5V 16V, Y5V

RN28
*1 2
DEVSELJ
TRDYJ Placed near EC9 Placed DIMM4 Placed near Codec Title
3 4 IRDYJ
5
7
6
8
FRAMEJ PCI Slot
8.2K EMI CAP. DWG NO Rev
A01
Arrowhead

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1
Sheet 31 of 45
 5V_SYS
5

5V_SB_SYS
4

Trung Tâm Máy Tính AV

-12V_SYS
3

5V_SB_SYS
2 1

3D3V_SYS
12V_SYS
*R477 5V_SYS
12V_SYS
Chassis Intruder Header
10K X02 update
*R476 3D3V_SYS 5V_SYS
4.7K
+/-5% Micro_PWR
13 1 INTRUDER
14 GND5 GND1 2 PSU_FAN_CTRL_P 3
29 INTRUD_CABLE_DET#

*
15 GND6 F_CTRL 3 2 3

*
ATXPWRGD PS_ONJ PSU_FAN_TACH_P 0 +/-5%
16 +3.3V2 F_TACH 4 PSU_FAN_TACH 29 1 2
+3.3V3 +3.3V1
R3091 Dummy 23 INTRUDERJ
R376 10K
1
17 5
20,29 ATXPWRGD 18 PWROK GND2 6 Header_1X3
D GND7 GND3 D
C475 19 7 C488
* 0.1uF
* C474 20 +12V_2 +12V_1
-12V +5V_AUX
8 * 0.1uF
16V, Y5V dummy 0.1uF 21 9 16V, Y5V
16V, Y5V 22 GND8 GND4 10
29 PS_ONJ PSON +5V_1
23 11
24 +5V4 +5V_2 12
+5V5 +5V_3 R3089 Dummy PSU_FAN_CTRL_P
29 PSU_FAN_CTRL

*
Header_2X12 1K +/-5%

C2031
* 0.1uF
Clear CMOS
RTCRST
16V, Y5V 1-2:CLEAR CMOS
Dummy 1
R479 EMPTY: NORMAL 2
* 23,24 RTCRSTJ
470
Header_1X2
*

A
AUX_PWR R482
RTCRST_JUMPER(1-2) 1K
LED_Yellow

-12V_SYS 12V_SYS 5V_SYS 3D3V_SYS 5V_SB_SYS

C
Jumper_2P_Blu
C479 C480 EC39
* 0.1uF * 0.1uF
* C481
* C482
* C476
* C477
* C478
* 470uF Dummy Clear Password
16V, Y5V 16V, Y5V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +/-20%
16V, Y5V 16V, Y5V 16V, Y5V 16V, Y5V 16V, Y5V
PSWD1_JUMPER(1-2) 3D3V_SB

1-2: NORMAL
*R3033
8.2K
EMPTY: CLEAR PASSWORD Jumper_2P_Blu +/-5%
PSWD1
5V_SYS 1
24 PSWD_CLR 2
C C
C4801 5V_SYS
* 0.1uF D22 Header_1X2
16V, Y5V C A 5V_SYS 5V_SB_SYS
C512
1N4148W 0.1uF
RN32 RN36 RN33 RN34 *
*
2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8
1K R552 1K 1K 1K 16V, Y5V, +80%/-20%
+/-5% 1K +/-5% +/-5% +/-5% RN42 POP3 @5514
*1
3
5
7

* 13
5
7

* 13
5
7

* 13
5
7
*1 2 RN42 dummy
3 4 RN29 stuff
5 6
7 8
100 Ohm
P_D0 P_D4 RN29 POP4 BEEP

PD[7..0] RN31 33 +/-5%

P_D1
P_D2
P_D5
P_D6
*1 2
PCBEEP_PWR +
29 PD[7..0] PD0 P_D3 P_D7 3 4
BUZZER
PD1 8 7 5 6 PCBEEP_SINK -
RN30 +/-5% PD2 6 5 7 8
4 3
29 STBJ *1 2
33 PD3
RN35 2 1
*
+/-5%
100 Ohm Buzzer
29 AFDJ 3 4 PD4
* 13 33
* C487

*
29 INIT 5 6 PD5 2 R487 1K 0.1uF
29 SLINJ 7 8 4 23 SPKR
PD6 25V, X5R
PD7 5 6
7 8

3
29 ERRJ

Q3034
29 ACKJ MMDT5551

*
6

4
29 BUSY 1K
29 PE SPEAKER 29
R3004
29 SLCT

B PRT PORT B

PARALLEL

1
AFD1- 14
P_D0 2
ERR- 15
P_D1 3
INIT1- 16
P_D2 4 5V_SYS
SLIN1- 17
P_D3 5
18 INT_SPKR
P_D4 6 1
19 2
7 28 29 AUD_PCSPKR_DET# 3
P_D5
20 27
P_D6 8 26 R3841 20K 5
28 MONO_OUT
21 +/-5%
P_D7 9 C3015 Header_1X5_K4
22
ACKJ 10 * 1uF
10V, X5R, +/-10% C3746
23 C3030 1uF
BUSY 11 * 0.1uF * 10V, X5R, +/-10%
24

16V, Y5V
PE 12
25
SLCT 13

PARALLEL

CN2 CN3 CN4 CN5

220pF 220pF 220pF 220pF
50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
A * * * * 220pF
A

* C2821

Title

BTX, PRT, MISC Connector

DWG NO Rev
A01
Arrowhead

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1
Sheet 32 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

3D3V_SYS 3D3V_SYS

D D
R3065
* 1K *R3837
4.7K
+/-5%
12V_SYS
+/-5%

*
0 R3874 EC49

dummy
+/-5% * 120uF
16V, +/-20%

*
3D3V_SYS R383 220

C
29 SIO_FAN_SEN_CPU
Q3017 R3838

*
MMBT3904 B 4.7K +/-5%
3D3V_SYS
*R3842
4.7K
sot23_bech11
* C3022
12V_SYS

E
+/-5% 0.1uF
R3843 5V_SYS 16V, Y5V, +80%/-20%
*
4.7K
+/-5% FAN_CPU
1
* R3066 2

B
1K 3

*
+/-5% PWM_CPU R3051 4

*
E C PWM_CPU R3840 100 +/-1% 5
29 FAN_PWM_CPU 29 FAN_ID
+/-1% 33K
Q3018
MMBT3904
* C3031 *R3839
20K
*
Hearer_1X5

sot23_bech11 0.1uF +/-1% Dummy C64

16V, Y5V, +80%/-20% 25V,Y5V,+80/-20% 4.7uF

C C

12V_SYS

3D3V_SYS 3D3V_SYS

EC29
* 120uF

* R3088 *R3854
4.7K
+/-5%
16V, +/-20%

1K
+/-5%

*
0 R3878
+/-5%
Dummy

*
R338 220
29 SIO_FAN_SEN_SYS
3D3V_SYS

C
Q3026 R3855

*
MMBT3904 B 4.7K +/-5%
3D3V_SYS
*R3845
4.7K
sot23_bech11
* C3023
12V_SYS

E
+/-5% 0.1uF
R3844 16V, Y5V, +80%/-20%
*4.7K
+/-5% FAN_HDD
1
2
B

*
HDD_PWM R3052 4
E C HDD_PWM 100 +/-5% 5
29 SIO_FAN_PWM_SYS
Q3019 Hearer_1X5
B B
MMBT3904
sot23_bech11 * C368
25V,Y5V,+80/-20% 4.7uF

Dummy

@CYPHER STUFF
FAN_HDD, R3052, R3087, R3854,
C3023, R3088, R3855, Q3026, R338

A A

Title

CPU / System Fan

DWG NO Rev
A01
Arrowhead

www.advancerepairlaptop.blogspot.com
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5 4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 33 of 45
 TPM, TCM
5

3D3V_SYS
4

Trung Tâm Máy Tính AV 3D3V_SYS

3

12V_SYS
2 1

* R207
C513 C515 8.2K
0.1uF 0.1uF C514 C65 C56 C55
* * * 10uF
* 0.1uF
* 0.1uF
* 0.1uF
* C57
+/-1%
10uF

G
6.3V, X5R, +/-20%

close to Pin 10

close to Pin 19

close to Pin 24
POP5
Z

6.3V, X5R, +/-20%

POP9

POP9
Dummy Dummy D S TPM_PLTRSTJ Base Address BA1 PIN3 BA0 PIN9
26,29 SIO_PLTRSTJ

POP6 POP7 POP8

Dummy

2N7002-7-F Q36
EE/EF 0 0
Dummy * R237 7E/7F 0 1
Dummy 8.2K

*
D D
POP9 R536 33
POP6 dummy
+/-1% 2E/2F 1 0
LPCPDJ_TPM
4E/4F 1 1
Winbond: C65, C55 pop 1uF
3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS
Default set EE/EF as Amy recommended,
3D3V_SYS
*R399 R34
Pin 3 and Pin 9 have internal PU in Z.
10K * 0 +/-5% R112

41
40
39
38
37
36
35
34
33
32
31
POP9 POP5 POP6 POP7 * 0 POP6 POP7 POP8
TCM Dummy X02 update TPM/TCM +/-5%
3D3V_SYS POP5
J
GND9
GND8
NC9
BADD1
NC8
NC7
NC6
NC5
NC4
NC3
LPCPD#
26 10 Dummy
23,29 L_AD0 23 LAD0 VPS1 19 TPM_PIN19
23,29 L_AD1 LAD1 NC6 TESTEN
30 20 24 STATUS RUNMODES PIN9
1 SERIRQ 29 SERIRQ 24,29 23,29 L_AD2 17 LAD2 VPS2 PIN8
2 GND1 LAD0 28 L_AD0 23,29 23,29 L_AD3 LAD3
*

Dummy
0 R494 3 NC1 GND7 27 5 TPM_PIN5 NORMAL MODE 0 X
*

10K R400 4 GP103 GND6 26 LPCPDJ_TPM 28 NC1 12 TPM_PIN12

Dummy POP9 5 PP VCC3_6 25 22 LPCPD# NC3
BADD0 VCC3_5 23,29 L_FRAMEJ LFRAME# JTAG MODE 1 0
6 24 Dummy 3

**

*
TPM_PIN3
7 VCC3_1 LAD1 23 33 POP9 L_AD1 23,29 16 VNC 7 TP95
R212 TPM_PLTRSTJ 0 R598 TPM_PP_PIN7 NORMAL MODE
*R377 8 VCC3_2 LFRAME# 22 0 POP9 R1537
L_FRAMEJ 23,29 LRESET# PP 6 TPM_PIN6
TP112 1 1
9 GND2 LCLK 21 CK_33M_TPM 7 GPIO3 1 TP113
10K Dummy POP5 POP6 POP7 POP8 TPM_PIN1
10 GND3 LAD2 L_AD2 23,29 GPIO1 2 TP114
POP9 TCM_TESTI TPM_PIN2
CLKRUN#

J has internal PD with PIN8,

LRESET#

GPIO15 GPIO2 TP115

VCC3_3
VCC3_4

21 9
GPIO16

Dummy TPM_PIN9
7 CK_33M_TPM LCLK GPIO4
GND4
GND5
NC_P

27 8 TPM_PIN8 internal PU with PIN9

LAD3
NC2

24,29 SERIRQ 15 SERIRQ NC2 TP116

TPM_CLKRUN-
R334 * X02 update
4
GPIO5
4.7K
11
12
13
14
15
16
17
18
19
20

Dummy TCM 11 GND1

POP9 3D3V_SYS 18 GND2 13
25 GND3 NC4 14 CK_14M_TPM 7
Dummy R1003 0 SB19NP18BR28PVLR
NC7 NC5

*
+/-5%
POP6 POP7 POP8 C84
J
C
Dummy * 0.1uF
POP6
1(default) 0 C
*

BSEL
0 R492 Dummy PIN12
L_AD3 23,29 FLASH SRAM
*

Dummy
0 R480 POP9 TPM_PLTRSTJ
Dummy
TCM_CLKRUN-
J has internal PU with PIN12

3D3V_SYS 3D3V_SB 3D3V_SB 3D3V_SYS 3D3V_SYS 3D3V_SYS 3D3V_SYS

Power trace =20 mil Power trace =20 mil

R10 R70 R224 J z z
* R3906 Winbond
* 0 * 0 Winbond * 4.7K *R1001 *R1002 *R3862
100KOhm +/-5% +/-5% POP8 +/-5% 10K 10K 8.2K
+/-1% Dummy dummy dummy +/-5%
TCM_CLKRUN- Dummy TPM_PIN5 Dummy TPM_PIN12 Dummy TPM_PIN8 TPM_PIN9 TPM_PIN3 TPM_CLKRUN- LPCPDJ_TPM POP5 POP6 POP7

C257 C256 R218

*R455 POR function for J
* 1uF
* 1uF * 1K Winbond *R226
4.7K J *R444
1K z *R443
1K z * R1314
10K Winbond 10V, X5R, +/-10% 10V, X5R, +/-10% Dummy POP8 +/-5% STM dummy dummy 4.7K
Dummy dummy dummy Dummy POP6 POP6
+/-5%

B XDP Connector VTT_OUT_RIGHT

LPC DEBUG B

HTCK C495
HTCK 10 * 0.1uF
HTRSTJ 16V, Y5V
*R499 *R500 *R501 *R496

*
HTRSTJ 10 dummy CK_33M_TPM R542 0 ROM_DEBUG_CLK
62 62 62 62 POP1 +/-5%
*R498 *R497 POP1 Dummy
62 62 XDP_TESTIN

Dummy HTDO
HTDO 10 3D3V_SYS 5V_SYS
HTDI
HTDI 10
HTMS POP1
HTMS 10 LPC_DEBUG Dummy

**
ROM_DEBUG_CLK 1 2 R219 0
3 4 INIT3_3# 24
SIO_PLTRSTJ POP1
XDP POP1 VTT_OUT_RIGHT L_AD0 5 6 FWH_ID0 R294 0
9 23 7 8 GNT0J 25,31
HBPM0J HTDO L_AD1 POP1
10 HBPM0J HBPM1J 7 BPM0# TDO 29 HTDI L_AD2 9
10 HBPM1J BPM1# TDI X Dummy
HBPM2J 6 31 HTMS 11 12
10
10
HBPM2J
HBPM3J
HBPM3J
HBPM4J
4
3
BPM2#
BPM3#
TMS
TCK
30
25
HTCK
HTRSTJ
*R503
1.5KOhm
L_AD3
L_FRAMEJ 13 14
+/-1% Dummy
10 HBPM4J HBPM5J 1 BPM4# TRST# POP1
10 HBPM5J BPM5# 10 XDP_PWRGD POP1 Hearer_2X7_K10
*

16 PWRGOOD 19 XDP_CPURSTJ R504 1K C234 POP1

18 100M_CLK_DP RESET# 21 HCPURSTJ 8,9,10,12,29
POP1 Dummy 22pF C235
100M_CLK_DN DBR#
TESTIN#
12 XDP_TESTIN
FP_RSTJ 10,23,37 * 10nF Dummy
13
10 CPU_CK_XDP_P 15 XDP_H_CLK_DP 2
10 CPU_CK_XDP_N XDP_H_CLK_DN GND_1 5
22 GND_2 8
7,29 SMB_CLK_MAIN SCL GND_3 @proto stuff
24 11
A 7,29 SMB_DATA_MAIN SDA GND_4 17 Dummy A
14 GND_5 20 Dummy
VTT GND_6 26
GND

GND

VTT_OUT_RIGHT 28 GND_7 27
NC GND_8
DF9-31S-1V(32)
32

33

Dummy Title
@proto
R503 stuff
R504
KB/MS, TPM, XDP,LPC CONN.
U47 DWG NO Rev
A01
Arrowhead

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5

www.advancerepairlaptop.blogspot.com 4 3 2
Date: Wednesday, June 02, 2010
1
Sheet 34 of 45
 USB
5 4

Trung Tâm Máy Tính AV 3 2 1

USB_DUAL
F1503
1 2
*
Fuse 2.0A EC67 C1514

R490
* 470uF
+/-20% * 0.1uF
16V, X7R, +/-10%

*
23 USB_OCJ_FRONT_2 1 10K +/-1%
D * C2826 R488
D

25V, X7R, +/-10% 0.1uF 15K

+/-1% INT_USB
2 1 2
3 4
5 6
7 8
10
X USB_HDR_CBL_DETJ 25
+/-5% 0 R134 USB2N_R
23 USB2N +/-5% 0 R135 USB2P_R Header_2X5_K9
23 USB2P +/-5% 0 R173 USB3N_R
90-OHM DIFFERENTIAL IMPEDANCE 23 USB3N +/-5% 0 R175 USB3P_R
23 USB3P

(PIN 9: KEY)
CUT PIN-9

U3510
USB3N_R 1 6 USB3P_R

2 5
USB_DUAL
L20 dummy
USB2N_R 4 3 USB2P_R 3 4 USB2N_R
USB2N 23
USB2P_R 1 2
USB2P 23 IP4220CZ6
Common Choke 90 Ohm_2L
L12 dummy
USB3P_R 1 2
USB3P 23
USB3N_R 4 3
USB3N 23
Common Choke 90 Ohm_2L
LEFT USB PORT 2 RIGHT USB PORT 3
C C
CO-LAY with Four 0603 Serial Resistors

USB HEADER PIN

ASSIGNMENT

COM 1

CP6
1 2

4
CONN - Dual port COPPER
U28
20 1 SER1_12V NDCDA T1
5V_SYS VCC +12V D25
NDSRA T6 dummy
B B
16 5 NRTSA NSINA T2 A C SER1_12V
29 RTS1# DA1 DY1 12V_SYS
15 6 NDTRA NRTSA T7
29 DTR1# 13 DA2 DY2 8 NSOUTA NSOUTA T3 C348
29 SOUT1 19 DA3 DY3 2 NRIA NCTSA T8 1N4148W 10nF
29 RI1# 18 RY1 RA1 3 NCTSA NDTRA T4
29 CTS1# 17 RY2 RA2 4 NDSRA NRIA T9 M3
29 DSR1# 14 RY3 RA3 7 NSINA T5 M2
29 SIN1 12 RY4 RA4 9 M1 CP7
NDCDA
29 DCD1# RY5 RA5 3 1 2
11 10 SER1_12V#
GND -12V
VGA_SERIAL1B COPPER
GD75232
D29
dummy
C A SER1_12V#
-12V_SYS
C358
1N4148W 10nF
NDCDA
NDSRA
placed near GD75232 NSINA
NRTSA
-12V_SYS 5V_SYS 12V_SYS NSOUTA
NCTSA
NDTRA
C498 C497 NRIA
* 0.1uF * C496 * 0.1uF
* *
16V, Y5V
16V, Y5V, +80%/-20%

0.1uF 16V, Y5V

CN7 CN6
150pF 150pF
50V, NPO, +/-10% 50V, NPO, +/-10%

Dummy Dummy

A A
placed near connector

Title

USB Header / COM Port

DWG NO Rev
A01
Arrowhead

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5

www.advancerepairlaptop.blogspot.com4 3 2
Date: Friday, July 30, 2010
1
Sheet 35 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

3D3V_CL LAN_1D8V

C503 C501 R642

* * *0+/-5% NIC_USB
120pF 120pF Dummy
50V,NPO,+/-5% 50V,NPO,+/-5%
D D

28
14 29

GRN_LED

ORG_LED
VCT 30
31

USB-2

USB-1
USB_DUAL_LAN USB_DUAL
R1337 150 +/ -1% 13
27 LAN_LED2

**
R1338 150 +/ -1% 15 F1500
27 LAN_LED1
16 2

* C490
* C491 6 20 *1
TRD0+ 2 C1502 EC64 Fuse 2.0A
27 TRD0+
*

RJ45-MJ2
470pF 470pF TRD0- 3 17 USB9N_R 0.1uF 470uF
27
27
TRD0-
TRD1+
TRD1+ 4 21 USB8N_R 16V, X7R, +/-10% * +/-20%
5

*
27 TRD1- TRD1- R471
TRD2+ 7 18 USB9P_R +/-1% 10K
27 TRD2+ USB_OCJ_BACK_LAN 23
TRD2- 8 22 USB8P_R
27 TRD2-
27 TRD3+ TRD3+ 9 1
TRD3- 10 19
27 TRD3-
1 23 R474 C2823 *
15K 0.1uF 25V, X7R, +/-10%

YLW_LED
* +/-1%
R1336 12 24 2
3D3V_CL
150 +/ -1% 11 25
27 LAN_LED0
26
27 U3507
USB9P_R
*C169 USB9N_R
R141
R138
0
0
+/-5%
+/-5% USB9P
USB9N
23
23
USB9N_R 1 6 USB9P_R
470pF USB8P_R R176 0 +/-5%
C1312 CONN - USBx2_RJ45 USB8N_R R369 0 +/-5% USB8P 23 2 5
USB8N 23 USB_DUAL
0.1uF
dummy USB8P_R 3 4 USB8N_R

IP4220CZ6
3D3V_CL

L28 dummy
USB8P_R 4 3
C USB8P 23 C
U3522 USB8N_R 1 2
USB8N 23
1 5 VCT Common Choke 90 Ohm_2L
2 VIN VOUT L27 dummy
3 GND USB9N_R 1 2
EN 4 USB9N 23
C500 ADJ C417 C1315 USB9P_R 4 3

* 4.7uF LD39015M25R * 4.7uF 0.1uF USB9P 23

6.3V, X5R C494 6.3V, X5R Dummy Common Choke 90 Ohm_2L
0.1uF

X02 update

USB_DUAL

F1501
1 2
R454 *
*

1 10K +/-1%
Fuse 2.0A EC65 C1506
23 USB_OCJ_BACK_1
* C2824 R453
* 470uF
+/-20% * 0.1uF
16V, X7R, +/-10%
25V, X7R, +/-10% 0.1uF 15K
+/-1%
2

B B
L30 dummy
USB4P_R 4 3
USB4P 23
USB4N_R 1 2
USB4N 23
Common Choke 90 Ohm_2L
L29 dummy +/-5% 0 R384 USB4P_R
USB5N_R 1 2 23 USB4P +/-5% 0 R378 USB4N_R
USB5N 23 23 USB4N USB5P_R USB
+/-5% 0 R392
USB5P_R 4 3 23 USB5P +/-5% 0 R394 USB5N_R
USB5P 23 23 USB5N 41
Common Choke 90 Ohm_2L 42 VCC1
43 USB0-

CO-LAY with Four 0603 Serial Resistors

44 USB0+
GND1
UP
U3508
31
USB_DUAL 32 VCC2 USB4N_R 1 6 USB4P_R
33 USB1-
F1502
1
* 2 34 USB+
GND2
Second 2 5 USB_DUAL
Fuse 2.0A EC66 C1510 USB5P_R 3 4 USB5N_R

R467
* 470uF
+/-20% * 0.1uF
16V, X7R, +/-10% 21
IP4220CZ6
*

10K +/-1% 22 VCC3

1
23 USB_OCJ_BACK_2
* C2825 R458
23
24
USB2-
USB2+
Third U3509

25V, X7R, +/-10% 15K GND3 USB6N_R 1 6 USB6P_R

0.1uF
+/-1%
2 45 2 5
GND5 USB_DUAL
L32 dummy 11 46
USB7P_R 4 3 12 VCC4 GND6 47 USB7P_R 3 4 USB7N_R

USB7N_R 1 2
USB7P 23 13
14
USB3-
USB3+
Down GND7
GND8
48
49
USB7N 23 GND4 GND9 IP4220CZ6
50
Common Choke 90 Ohm_2L +/-5% 0 R442 USB7P_R GND10
A L31 dummy 23 USB7P +/-5% 0 R429 USB7N_R A
23 USB7N CONN-USBx4
USB6N_R 1 2 +/-5% 0 R424 USB6P_R
USB6N 23 23 USB6P +/-5% 0 R398 USB6N_R
USB6P_R 4 3 23 USB6N
USB6P 23
Common Choke 90 Ohm_2L

CO-LAY with Four 0603 Serial Resistors

Title

LAN / Rear USB Connector

DWG NO Rev
A01
Arrowhead

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www.advancerepairlaptop.blogspot.com 4 3 2
Date: Friday, July 30, 2010
1
Sheet 36 of 45
 ⑨⑥⒆
5

close to SPI within 500 mils

4

Trung Tâm Máy Tính AV 3 2

3D3V_CL
1

3D3V_CL
R548,R605 change to 0ohm for single SPI

U3521 C560
ICH_SPI_HOLDJ 1 16 ICH_SPI_CLK_R * 0.1uF

* **

**
R565 15Ohm +/-1% R566 47 +/-5% ICH_SPI_MOSI_R 2 HOLD# C 15 ICH_SPI_MOSI_R 16V, Y5V
23 ICH_SPI_MOSI 3 VCC D 14
R567 15Ohm +/-1% R568 47 +/-5% ICH_SPI_CLK_R
23 ICH_SPI_CLK 4 DU1 DU8 13 3D3V_CL
R569 15Ohm ICH_SPI_CS0J_R 5 DU2 DU7 12
23 ICH_SPI_CS0J
+/-1% 6
7
DU3
DU4
DU6
DU5
11
10 1
U29 POP1
8
* R563 * R564
1
J_SPI POP1
2
ICH_SPI_CS0J_R ICH_SPI_CS0J_R 1K 1K
ICH_SPI_MISO_R 8 S# VSS 9 ICH_SPI_WPJ ICH_SPI_CLK_R 6 CS# VCC 7 ICH_SPI_HOLDJ ICH_SPI_CS0J_R 3 C1 C2 4
close to ICH10 within 500 mils Q W# SCK HOLD# C3 C4
ICH_SPI_MOSI_R 5 3 ICH_SPI_WPJ ICH_SPI_MISO_R 5 6 ICH_SPI_HOLDJ
D SI WP# C5 C6 D
M25P64-VMF6TP ICH_SPI_MISO_R 2 4 7 8 ICH_SPI_CLK_R
SO GND 9 C7 C8 10 ICH_SPI_MOSI_R
C9 C10
SPI Flash socket HC1105H

*
R570 15Ohm ICH_SPI_MISO_R SOP8JGH22
23 ICH_SPI_MISO
+/-1% Dummy Dummy

U29_1

SST25VF032B-50-4C-S2AF
Dummy

⒃⑧⑤④⑩ ⑥⑾④⒂② ⒃②⑤⑥⑥㈢

5V_SYS

C 3D3V_SYS 5V_SB_SYS 3D3V_SB C

C410 5V_SYS
C450 1uF
* * *R671
10V, X5R, +/-10%
1uF
10V, X5R, +/-10% 10K *R1805
1K *R1806
1K *R1807
1K *R1808
1K *R1809
1K
+/-5% +/-5% +/-5% +/-5% +/-5%
FRONTPANEL
28 PROTA_L DSKT2
1 2 27 1
28 PROTA_R 3 4 NC5 VCC1 2
28 PROTB_L 5 6 INDEX- INDEX# 29
3
28 PROTB_R 7 8 VCC2 4
28 SA_A 9 10 SA_B 28 DS0- DRVA# 29
5
29 DIAG_LED_1 11 12 DIAG_LED_2 29 VCC3 6
29 DIAG_LED_3 13 14 DIAG_LED_4 29 DSKCHG- 7 DSKCHG# 29
29 SIO_YELLOW_N 15 16 SIO_GREEN_N 29 NC1 8
29 FP_CBL_DETECT# 17 18 FIO_SYSTEM_TDA 29 NC2 9
29 FIO_SYSTEM_TDC
*

PWR_BTN#_D 33 19 20 NC3 10
FP_RSTJ 10,23,34 MTRA# 29
* *

R316 POP3 R436 21 22 5V_SYS 5V_SB_SYS MTR0- 11

24 HDD_LED 23 24 FP_LAN_LED_GRN_N 27 NC4 12
+/-5% 0
26 DIR- 13 DIR# 29
POP4 POP3
27 28 28 DRVDEN0 14 DENSEL 29
R319 POP4 FP_VCCUSB FP_VCCUSB R225 R228
29 SIO_FP_HDLEDJ
+/-5% 0 FP_VCCUSB 29
31
30
32
* 0 * 0 NC6 STEP-
GND1
15
16
STEP# 29
USB1P_R +/-5% @5514
33 34 +/-5% WDATA- WDATA# 29
@5514 USB1N_R 17
USB0P_R 35 36 USB0N_R R228 dummy GND2 18
R316 dummy C409 37 38 R225 stuff WGATE- 19 WGATE# 29
R319 stuff 1uF 39 40 GND3 20
* TRK0- TRK0# 29
10V, X5R, +/-10%

Header_2X20_K25 21 FLOPPY_DETECTJ
GND4 22
WRTPRT- 23 WPT# 29
ANGND
GND5 24
RDATA- 25 RDATA# 29
RST_SWH POP1 29 GND6 26
NC7 HDSEL- HDSEL# 29
3D3V_SB 5
dummy 1 2
FP_RSTJ C1523 0.1uF 3 4 CONN-FFC
B B
*****

R672 16V, Y5V

* 8.2K DIAG_LED_1 C1519 0.1uF Dummy
6

+/-5% 16V, Y5V CONN-Switch Slim type

DIAG_LED_2 C1520 0.1uF
FP_CBL_DETECT# 16V, Y5V
DIAG_LED_3 C1521 0.1uF Dummy
C3005 16V, Y5V
* 0.1uF DIAG_LED_4 C1522 0.1uF
16V, Y5V 16V, Y5V

USB_DUAL
F1504
1 2 FP_VCCUSB
*

*
R347 FLOPPY_DETECTJ
23 GPI_FLOPPY_DETECTJ
Fuse 2.0A 3D3V_SB 0 +/-5%
C1518 Dummy
0.1uF
R437 * 16V, X7R, +/-10% R3000 3D3V_SB R3001
*
*

1 10K +/-1% 1K
* 0
23 USB_OCJ_FRONT_1
+/-1% +/-5%
* C2827
R438
15K
r0402h4
U3517
25V, X7R, +/-10% 0.1uF +/-1% PWR_BTN#_D 1 6 Dummy
2 2 1A 1Y 5
C3004 3 GND VCC 4
* 0.1uF 2A 2Y PWR_BTN# 23,29
PWR_SWH POP1 16V, Y5V Dummy 74LVC2G14
L34 dummy
USB0N_R 4 3
5

USB0N 23
*

USB0P_R 1 2 1 2 R594 33 R595

USB0P 23 3 4 POP1 +/-5% 0
Common Choke 90 Ohm_2L
Dummy
L33 dummy
6

USB1P_R 1 2 CONN-Switch
A USB1P 23 A
U23
USB1N_R 4 3
USB1N 23 USB1N_R 1 6 USB1P_R
Common Choke 90 Ohm_2L USB_DUAL
2 5
Dummy
USB0N_R 3 4 USB0P_R
CO-LAY with Four 0603 Serial Resistors
IP4220CZ6
+/-5% 0 R581 USB0N_R Title
23 USB0N USB0P_R
+/-5% 0 R577
23
23
USB0P
USB1N
+/-5% 0 R585 USB1N_R Front Panel / SPI / Floppy
+/-5% 0 R587 USB1P_R
23 USB1P
DWG NO Rev
A01
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4 3 2
Date: Friday, July 30, 2010
1
Sheet 37 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

D D

Stuff for AMT

3D3V_CL

*
R578 1K
MCH_CLPWROK 12
C569
1uF
* 10V, X5R, +/-10%
X02 update
dummy 5V_SB_SYS

C
*R687 Q51

*
5.6K R589 2.7K B MMBT3904
7,19,20,23 SLP_M
+/-1% sot23_bech11

E
B
1D1V_MCH_CL

*
Q98

E
MMBT3904 B 10K R579
sot23_bech11
Q97

E
C MMBT3904 C585 C
sot23_bech11 1uF
* 10V, X5R, +/-10%

CL PWROK GENERATION

B B

H1 H2 H4 H5
5V_SYS FMARK FMARK FMARK FMARK
FD40 FD40 FD40 FD40
H7 H9 H10 H18 H19 H20 IMPEDANCE_1
Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole 1
2
1

1
6
5

6
5

6
5

6
5

6
5

6
5

Header_1X2
7 4 7 4 7 4 7 4 7 4 7 4 dummy
8 3 8 3 8 3 8 3 8 3 8 3
9 2 9 2 9 2 9 2 9 2 9 2
IMPEDANCE_2
1

1
mh40x80_8_dell mh40x80_8_dell mh6_35MM mh6_35MM mh40x80_8_dell mh40x80_8_dell 2

Header_1X2
A dummy A

H11 H12 H13 5V_SYS

Mounting Hole Mounting Hole Mounting Hole IMPEDANCE_3 IMPEDANCE_5
1 1 H16 H17 H21 H22 H23
2 2 FMARK FMARK FMARK FMARK FMARK
6
5

6
5

6
5

FD40 FD40 FD40 FD40 FD40

7 4 7 4 7 4 Header_1X2 Header_1X2
8 3 8 3 8 3 dummy dummy
9 2 9 2 9 2
1

IMPEDANCE_4 IMPEDANCE_6 Title

1

1 1
mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell 2 2 Reserved-1
Header_1X2 Header_1X2 DWG NO Rev
dummy dummy A01
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1
Sheet 38 of 45
 MYLAR
5 4

Trung Tâm Máy Tính AV 3 2 1

MYLAR
Mylar FOR GAO

D D

X02 update

5V_SYS
12V_SYS 12V_SYS 5V_SYS 12V_SYS 5V_SYS
3D3V_SYS 1D5V_STR 12V_SYS 5V_SYS 12V_SYS 3D3V_SYS

C1013 C1005
C1014
C1020 C1006 C1016 10nF C1001 10nF

*
10nF 10nF 10nF 25V, X7R 25V, X7R

*
25V, X7R 25V, X7R 25V, X7R
0.1uF 0.1uF
12V_SYS 3D3V_SYS 16V, X7R, +/-10% 16V, X7R, +/-10%
12V_SYS 5V_SYS

C1017
C1015 10nF STITCH CAP. FOR RGB SIGNAL

*
10nF 25V, X7R

*
25V, X7R

12V_SYS 3D3V_SYS 3D3V_SYS

C C

C1018 C1004
10nF 10nF

*
25V, X7R 25V, X7R

12V_SYS 3D3V_SYS

C1019
10nF
STITCH CAP. FOR ESATA SIGNAL

*
25V, X7R

TEST1_DUMMY _TOP
TP99

TEST2_DUMMY _TOP
TP100

VDDSPD

For CK_14M_SIO For CK_CPU_STOP For ICH_AUD_BCLK For RGB signal

12V_SYS 3D3V_SYS 3D3V_SYS 12V_SYS

3D3V_CL
C1527
dummy dummy dummy
C1524 0.1uF C1525 0.1uF C1526 0.1uF

*
R609 0 16V, Y5V 16V, Y5V 16V, Y5V
0.1uF
Stuff for AMT 5V_SYS 16V, X7R, +/-10%
12V_SYS
dummy
C1529
B
C1528 0.1uF B

*
16V, Y5V

*
0.1uF
16V, X7R, +/-10%
X02 update

A A

Title

Reserved-2
DWG NO Rev
A01
Arrowhead

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Date: Friday, July 30, 2010
1
Sheet 39 of 45
 5 4

Trung Tâm Máy Tính AV 3 2 1

KB / MS + COM2 Connector

D D

+5V_PS2 USE 15-20-MIL TRACE

ON KB/MOUSE POWER
+5V_PS2

R1900 KB WAKE
r0805h6 0+/-5%
* * USB_DUAL

*
C826 C827 R1901
+5V_PS2_F
RN90 0.1uF 0.1uF F1505 r0805h6 0+/-5% PS/2 MOUSE & KBD POWER SOURCE

8
6
4
2
5V_SYS
2K 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% Fuse 1.5A Dummy
+/-5% Dummy PS/2 ON IN STBY INSTALL R1900 DEFAULT

7
5
3
1
*
B804
FB 600 Ohm PS/2 OFF IN STBY INSTALL R1901

**
I2C_KBCLK -12V_SYS +5V_PS2
29 SIO_KBCLK
I2C_KBDAT I2C_KBDAT 5V_SYS 12V_SYS
29 SIO_KBDAT
B805 FB 600 Ohm SERIAL2
DCD2# 1 2 RXD2
SOUT2 3 4 DTR2#
5 6 DSR2#
7 8 DCD2# 29
RTS2# CTS2#
+5V_PS2_F 9 10 DSR2# 29
RI2#
11 RXD2 29
13
X
14 RTS2# 29
I2C_KBCLK
15 16 SOUT2 29
I2C_KBDAT COM_SER2_DET#
17 18 CTS2# 29
B806 FB 600 Ohm
**

19 20 DTR2# 29
I2C_MSCLK I2C_MSCLK I2C_MSCLK
29 SIO_MCLK 21 22 RI2# 29
I2C_MSDAT
23 24 COM_SER2_DET# 29
I2C_MSDAT I2C_MSDAT
29 SIO_MDAT *
B807 FB 600 Ohm CN24 Header_2X12_K12
180pF
C 50V, NPO, +/-10% C

* C828 * C829
0.1uF 0.1uF
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% SERIAL/MOUSE/KEYBOARD DONGLE HEADER
Dummy

KEYBOARD WILL BE ON BOTTOM

MOUSE WILL BE ON TOP OF THE
STACK CONNECTOR

B B

A A

Title

KB/MS/COM2
DWG NO Rev
A01
Arrowhead

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1
Sheet 40 of 45
 5 4

Trung Tâm Máy Tính AV

3 2 1

PCI Routing Summary

PCI0 PCI1
INTAJ A C
D
INTBJ B D D
INTCJ C A
INTDJ D B
INTEJ
INTFJ
INTGJ
INTHJ

C C

B B

A A

Title

IRQ Map
DWG NO Rev
A01
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Date: Wednesday, June 02, 2010
1
Sheet 41 of 45
 5

Clock Gen IDTCV184 Functional Straps

PIN NAME NET Strapping description
4

Trung Tâm Máy Tính AV

3 2 1

1 Overclocking DISABLED DEFAULT

PCI2/TME CK_PIN4
(PIN4) 0 Overclocking ENABLED

1 CGF TABLE ENABLED

PCI3/CFGP CK_PIN5
(PIN5) 0 CGF TABLE DISABLED DEFAULT

1 SRC5
PCI4/SRC5_EN CK_PIN6
(PIN6) 0 CPU_STOP# and PCI_STOP# DEFAULT

D 1 CPU_ITP DEFAULT D
PCI_F5/ITP_EN CK_PIN7
(PIN7) 0 SRC8

SIO SMSC5524 Functional Straps

PIN NAME NET Strapping description
SPEAKER[DIAG_EN#] 1 Diag_En Disable
/GP8051_45/GP14 SPEAKER
(PIN127) 0 Diag_En Enable DEFAULT
RTS1#[SYSOPT] 1 Sysopt strap 0 X 4E
/GP8051_58 RTS1#
(PIN101) 0 Sysopt strap 0 X 2E
DTR1#[FLASH_EN] 1 Flash Enable
/GP8051_16 DTR1#
(PIN104) 0 Parallel Enable DEFAULT

Intel ICH10 Functional Straps

PIN NAME NET Strapping description
1 Danbury Technology Enable Internal Pull-up
TP3 TP68
0 XOR Chain Entrance

1 NoReboot mode Internal Pull-up

SPKR SPKR
0 Reboot mode

C
1 MEenable DEFAULT
C
GPIO33 / MFG_MODE
HDA_DOCK_EN# 0 ME disable

1 MCH TPM Enable

SPI_MOSI ICH_SPI_MOSI
0 MCH TPM disable DEFAULT

Intel MCH Eaglelake Q45 Functional Straps

PIN NAME NET Strapping description
1 TLS Enable
cen TLS
0 TLS disable

1 iTPM Enable
iTPMb ITPM_EN
0 iTPM disable

1 SELECT Display Port

DDPC_CTRLDATA DDPC_CTRLDATA
0 SELECT PCIEX16

1 SELECT Display Port

DDPC_CTRLCLK DDPC_CTRLCLK
0 SELECT PCIEX16

B B

A A

Title

Strap Pin & ID POP Table

DWG NO Rev
A01
Arrowhead

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1
Sheet 44 of 45
 B00-X00
050809/1115:stuff
5

r1311,change connection from 3D3V_SYS to 3D3V_SB;

050809/1555:Delete PQ54
4

Trung Tâm Máy Tính AV

050809/1712:Change q13 from NTD4910NT4G to NTD40N03R;change q17 from NTD4906NT4G to NTD40N03R;delete PC100,stuff EC20;change EC20 from 470uf to 1000uf;
3 2 1

051109/1040:Change c187 from 4.7nF to 6.8nF,c89 from 47pF to 56pF.

051109/1547:Change R664 from 200 to 100,R665 from 1.5k to 2.2k,and then 2.2v changed to 2.4v for thermal balence;
change back of 051109/1040

051209/08:31:Add prn50,prn51 for 1.5v_str to 1.5v_ich

remove ec57 to 1d05v_ich

D D

051209/10:13:Dummy R184,R664,R665,R666,C446,C448,Q58 for 1.5v_str converted 1.5v_ich

051209/10:13:Dummy R184,R664,R665,R666,C446,C448,Q58 for 1.5v_str converted 1.5v_ich
051209/16:00:dummy r229,r220,q3030;
change r223,r221's source from 3.3v_sb to 3.3v_sys
051309/11:07:Add pr470,PR183,PR298 for 1.5v_ich
Dummy R183,c100,c101,r185,pr470
051309/1115:change r1311 connection from 3D3V_SB to 3D3V_SYS;
051809/0829:modify the power dilivery in page 4
051809/1404:Add impedance_5,impedance_6 in page 38
051809/1413:Change r227 from 5% to 1%
051809/1900:delete tp101,tp102;change the footprint of c391,c392,c393,c395 from c0603h9_ddr to c0603h9.
051909/1131:change the power dilivery in page 4
051909/1619:add pc1014,pc1015 for emc in page39
052009/1619:dummy r1311
052009/1620:change r227 from 33 to 33k
052209/0839:change the silkname from SATA0,SATA1,SATA2,SATA3,LPC_DEBUG1 to SATA_0,SATA_1,SATA_2,SATA_3,LPC_DEBUG.
052209/1110:change symbol of DIMM
052209/1600:Dummy U29,U29_1;Stuff U3521
052309/1118:update 32Mb to 64Mb in page1&2
052609/0904:change c178&188 from 0.22uF to 2.2nF.
change Q20 to AOD452
052609/1134:add PEC23,PREC23 for VTT_DDR
060109/1359:change R5281 from 475 to 499
change PREC23 to PEC231

C
060209/1506:add c25712,c28412,c504,c5041,c505,c5051 C

060309/1545:change H6,H7,H8,H9,H11,H12,H13,H14,H19's footprint

060409/1259:add r1341
060509/0836:dummy r1341
060509/0836:add r664,r665,c446,c448,r666,q58,r183,r184,c100,pr470,c101,r185,prn50.
dumm pr183,pr298,prn51
060509/1524:add two dummy res r2232,r2212
060809/1008:add C4801 for EMI
061609:change C448,C101 to 10nf;change R252 from 150 to 300.change R589 from 1k to 2.7k.
change all the Y5V materials to X7R.

X00-A00

073109:change R149 from 475 to 464.

Dummy all the debug components.
080509:Dummy DSKT2,R347

B B

A A

Title

History
DWG NO Rev
A01
Arrowhead
Date: Wednesday , June 02, 2010 Sheet 45 of 45
5 4 3 2 1

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